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Differential D90223

[AMDGPU][GlobalISel] Combine shift + logic + shift with constant operands
ClosedPublic

Authored by mbrkusanin on Oct 27 2020, 4:41 AM.

Details

Reviewers
foad
arsenm
Commits
rG53ae95c946c0: [AMDGPU][GlobalISel] Combine shift + logic + shift with constant operands
Summary

This sequence of instructions can be simplified if they are single use and
some operands are constants. Additional combines may be applied afterwards.

Diff Detail

Event Timeline

mbrkusanin created this revision.Oct 27 2020, 4:41 AM
Herald added subscribers: kerbowa, hiraditya, t-tye and 7 others. · View Herald TranscriptOct 27 2020, 4:41 AM
mbrkusanin requested review of this revision.Oct 27 2020, 4:41 AM
Herald added a subscriber: wdng. · View Herald TranscriptOct 27 2020, 4:41 AM
mbrkusanin added a parent revision: D90217: [AMDGPU][GlobalISel] Fold a chain of two shift instructions with constant operands.Oct 27 2020, 4:42 AM
mbrkusanin added a comment.Oct 27 2020, 4:46 AM

This patch is basically a global-isel version of combineShiftOfShiftedLogic() from DAGCombiner.

llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-of-shifted-logic.ll
8–9

This can be simplified to a single instruction:
s_lshl_b32 s0, s0, 4
but that will be a different combine.

Same goes for a few more cases below.

Harbormaster completed remote builds in B76533: Diff 300945.Oct 27 2020, 5:31 AM
mbrkusanin updated this revision to Diff 300977.Oct 27 2020, 6:37 AM
  • clang-format
foad added inline comments.Oct 28 2020, 2:10 AM
llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
244–245

I know you copied this comment from SelectionDAG but I think it really improves latency, not throughput, because the new shifts are independent.

Also you don't mention the other reason for doing this, which is that one of the new shifts might constant-fold away.

llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
1622

Also handle G_USHLSAT and G_SSHLSAT?

1666–1669

I don't see why this check is necessary. All we care about is the shift amount, as a uint64_t.

1677–1679

First, it would be simpler to check this by line 1690 where you're already computing the sum. Second, I would expect the > to be >=. Third, you're comparing against BitWidth which is the width of the shift amount, not the value being shifted.

1713

Don't create this. CombinerHelper already has a MIRBuilder.

1720

ShlType is wrong here and below. You want the type of the result, not the type of the shift amount.

1730–1732

It's probably not worth doing this. I think you can rely on dead code elimination.

mbrkusanin updated this revision to Diff 301924.Oct 30 2020, 9:16 AM
mbrkusanin marked 5 inline comments as done.
  • Supported G_SSHLSAT and G_USHLSAT and addressed other comments.
  • Added .mir test for G_SSHLSAT and G_USHLSAT.
foad accepted this revision.Nov 2 2020, 7:02 AM
foad added inline comments.
llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
1622

Comment still needs updating.

This revision is now accepted and ready to land.Nov 2 2020, 7:02 AM
mbrkusanin updated this revision to Diff 302526.Nov 3 2020, 2:51 AM
  • Updated comments.
mbrkusanin added a child revision: D90674: [GlobalISel] Expand combine for (x & mask) -> x when (x & mask) == x.Nov 3 2020, 3:32 AM
arsenm accepted this revision.Nov 3 2020, 7:42 AM
mbrkusanin updated this revision to Diff 303458.Nov 6 2020, 8:50 AM
  • Rebase
mbrkusanin mentioned this in D90674: [GlobalISel] Expand combine for (x & mask) -> x when (x & mask) == x.Nov 6 2020, 8:54 AM
mbrkusanin updated this revision to Diff 304110.Nov 10 2020, 2:35 AM
  • Rebase
Closed by commit rG53ae95c946c0: [AMDGPU][GlobalISel] Combine shift + logic + shift with constant operands (authored by mbrkusanin). · Explain WhyNov 10 2020, 2:37 AM
This revision was automatically updated to reflect the committed changes.
mbrkusanin added a commit: rG53ae95c946c0: [AMDGPU][GlobalISel] Combine shift + logic + shift with constant operands.

Revision Contents

PathSize
llvm/
include/
llvm/
CodeGen/
GlobalISel/
15 lines
Target/
GlobalISel/
11 lines
lib/
CodeGen/
GlobalISel/
116 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
405 lines
348 lines

Diff 304110

llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h

Show First 20 Lines • Show All 53 Lines • ▼ Show 20 Linesstruct PtrAddChain {
Register Base; Register Base;
}; };
struct RegisterImmPair { struct RegisterImmPair {
Register Reg; Register Reg;
int64_t Imm; int64_t Imm;
}; };
struct ShiftOfShiftedLogic {
MachineInstr *Logic;
MachineInstr *Shift2;
Register LogicNonShiftReg;
uint64_t ValSum;
};
using OperandBuildSteps = using OperandBuildSteps =
SmallVector<std::function<void(MachineInstrBuilder &)>, 4>; SmallVector<std::function<void(MachineInstrBuilder &)>, 4>;
struct InstructionBuildSteps { struct InstructionBuildSteps {
unsigned Opcode = 0; /// The opcode for the produced instruction. unsigned Opcode = 0; /// The opcode for the produced instruction.
OperandBuildSteps OperandFns; /// Operands to be added to the instruction. OperandBuildSteps OperandFns; /// Operands to be added to the instruction.
InstructionBuildSteps() = default; InstructionBuildSteps() = default;
InstructionBuildSteps(unsigned Opcode, const OperandBuildSteps &OperandFns) InstructionBuildSteps(unsigned Opcode, const OperandBuildSteps &OperandFns)
: Opcode(Opcode), OperandFns(OperandFns) {} : Opcode(Opcode), OperandFns(OperandFns) {}
▲ Show 20 Lines • Show All 157 Lines • ▼ Show 20 Linespublic:
bool matchPtrAddImmedChain(MachineInstr &MI, PtrAddChain &MatchInfo); bool matchPtrAddImmedChain(MachineInstr &MI, PtrAddChain &MatchInfo);
bool applyPtrAddImmedChain(MachineInstr &MI, PtrAddChain &MatchInfo); bool applyPtrAddImmedChain(MachineInstr &MI, PtrAddChain &MatchInfo);
/// Fold (shift (shift base, x), y) -> (shift base (x+y)) /// Fold (shift (shift base, x), y) -> (shift base (x+y))
bool matchShiftImmedChain(MachineInstr &MI, RegisterImmPair &MatchInfo); bool matchShiftImmedChain(MachineInstr &MI, RegisterImmPair &MatchInfo);
bool applyShiftImmedChain(MachineInstr &MI, RegisterImmPair &MatchInfo); bool applyShiftImmedChain(MachineInstr &MI, RegisterImmPair &MatchInfo);
/// If we have a shift-by-constant of a bitwise logic op that itself has a
/// shift-by-constant operand with identical opcode, we may be able to convert
/// that into 2 independent shifts followed by the logic op.
bool matchShiftOfShiftedLogic(MachineInstr &MI,
foadUnsubmitted
Not Done
ReplyInline Actions

I know you copied this comment from SelectionDAG but I think it really improves latency, not throughput, because the new shifts are independent.

Also you don't mention the other reason for doing this, which is that one of the new shifts might constant-fold away.

foad: I know you copied this comment from SelectionDAG but I think it really improves latency, not…
ShiftOfShiftedLogic &MatchInfo);
bool applyShiftOfShiftedLogic(MachineInstr &MI,
ShiftOfShiftedLogic &MatchInfo);
/// Transform a multiply by a power-of-2 value to a left shift. /// Transform a multiply by a power-of-2 value to a left shift.
bool matchCombineMulToShl(MachineInstr &MI, unsigned &ShiftVal); bool matchCombineMulToShl(MachineInstr &MI, unsigned &ShiftVal);
bool applyCombineMulToShl(MachineInstr &MI, unsigned &ShiftVal); bool applyCombineMulToShl(MachineInstr &MI, unsigned &ShiftVal);
// Transform a G_SHL with an extended source into a narrower shift if // Transform a G_SHL with an extended source into a narrower shift if
// possible. // possible.
bool matchCombineShlOfExtend(MachineInstr &MI, RegisterImmPair &MatchData); bool matchCombineShlOfExtend(MachineInstr &MI, RegisterImmPair &MatchData);
bool applyCombineShlOfExtend(MachineInstr &MI, bool applyCombineShlOfExtend(MachineInstr &MI,
▲ Show 20 Lines • Show All 233 Lines • Show Last 20 Lines

llvm/include/llvm/Target/GlobalISel/Combine.td

Show First 20 Lines • Show All 160 Lines • ▼ Show 20 Lines
// Fold shift (shift base x), y -> shift base, (x+y), if shifts are same // Fold shift (shift base x), y -> shift base, (x+y), if shifts are same
def shift_immed_matchdata : GIDefMatchData<"RegisterImmPair">; def shift_immed_matchdata : GIDefMatchData<"RegisterImmPair">;
def shift_immed_chain : GICombineRule< def shift_immed_chain : GICombineRule<
(defs root:$d, shift_immed_matchdata:$matchinfo), (defs root:$d, shift_immed_matchdata:$matchinfo),
(match (wip_match_opcode G_SHL, G_ASHR, G_LSHR, G_SSHLSAT, G_USHLSAT):$d, (match (wip_match_opcode G_SHL, G_ASHR, G_LSHR, G_SSHLSAT, G_USHLSAT):$d,
[{ return Helper.matchShiftImmedChain(*${d}, ${matchinfo}); }]), [{ return Helper.matchShiftImmedChain(*${d}, ${matchinfo}); }]),
(apply [{ Helper.applyShiftImmedChain(*${d}, ${matchinfo}); }])>; (apply [{ Helper.applyShiftImmedChain(*${d}, ${matchinfo}); }])>;
// Transform shift (logic (shift X, C0), Y), C1
// -> logic (shift X, (C0+C1)), (shift Y, C1), if shifts are same
def shift_of_shifted_logic_matchdata : GIDefMatchData<"ShiftOfShiftedLogic">;
def shift_of_shifted_logic_chain : GICombineRule<
(defs root:$d, shift_of_shifted_logic_matchdata:$matchinfo),
(match (wip_match_opcode G_SHL, G_ASHR, G_LSHR, G_USHLSAT, G_SSHLSAT):$d,
[{ return Helper.matchShiftOfShiftedLogic(*${d}, ${matchinfo}); }]),
(apply [{ Helper.applyShiftOfShiftedLogic(*${d}, ${matchinfo}); }])>;
def mul_to_shl_matchdata : GIDefMatchData<"unsigned">; def mul_to_shl_matchdata : GIDefMatchData<"unsigned">;
def mul_to_shl : GICombineRule< def mul_to_shl : GICombineRule<
(defs root:$d, mul_to_shl_matchdata:$matchinfo), (defs root:$d, mul_to_shl_matchdata:$matchinfo),
(match (G_MUL $d, $op1, $op2):$mi, (match (G_MUL $d, $op1, $op2):$mi,
[{ return Helper.matchCombineMulToShl(*${mi}, ${matchinfo}); }]), [{ return Helper.matchCombineMulToShl(*${mi}, ${matchinfo}); }]),
(apply [{ Helper.applyCombineMulToShl(*${mi}, ${matchinfo}); }])>; (apply [{ Helper.applyCombineMulToShl(*${mi}, ${matchinfo}); }])>;
// shl ([asz]ext x), y => zext (shl x, y), if shift does not overflow int // shl ([asz]ext x), y => zext (shl x, y), if shift does not overflow int
▲ Show 20 Lines • Show All 380 Lines • ▼ Show 20 Linesdef all_combines : GICombineGroup<[trivial_combines, insert_vec_elt_combines,
hoist_logic_op_with_same_opcode_hands, hoist_logic_op_with_same_opcode_hands,
shl_ashr_to_sext_inreg, sext_inreg_of_load, shl_ashr_to_sext_inreg, sext_inreg_of_load,
width_reduction_combines, select_combines, width_reduction_combines, select_combines,
known_bits_simplifications, ext_ext_fold, known_bits_simplifications, ext_ext_fold,
not_cmp_fold, opt_brcond_by_inverting_cond, not_cmp_fold, opt_brcond_by_inverting_cond,
unmerge_merge, fabs_fabs_fold, unmerge_cst, unmerge_dead_to_trunc, unmerge_merge, fabs_fabs_fold, unmerge_cst, unmerge_dead_to_trunc,
unmerge_zext_to_zext, trunc_ext_fold, trunc_shl, unmerge_zext_to_zext, trunc_ext_fold, trunc_shl,
const_combines, xor_of_and_with_same_reg, ptr_add_with_zero, const_combines, xor_of_and_with_same_reg, ptr_add_with_zero,
shift_immed_chain]>; shift_immed_chain, shift_of_shifted_logic_chain]>;

llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

Show First 20 Lines • Show All 1,611 Lines • ▼ Show 20 Linesbool CombinerHelper::applyShiftImmedChain(MachineInstr &MI,
Register NewImm = Builder.buildConstant(ImmTy, Imm).getReg(0); Register NewImm = Builder.buildConstant(ImmTy, Imm).getReg(0);
Observer.changingInstr(MI); Observer.changingInstr(MI);
MI.getOperand(1).setReg(MatchInfo.Reg); MI.getOperand(1).setReg(MatchInfo.Reg);
MI.getOperand(2).setReg(NewImm); MI.getOperand(2).setReg(NewImm);
Observer.changedInstr(MI); Observer.changedInstr(MI);
return true; return true;
} }
bool CombinerHelper::matchShiftOfShiftedLogic(MachineInstr &MI,
ShiftOfShiftedLogic &MatchInfo) {
// We're trying to match the following pattern with any of
foadUnsubmitted
Not Done
ReplyInline Actions

Also handle G_USHLSAT and G_SSHLSAT?

foad: Also handle G_USHLSAT and G_SSHLSAT?
foadUnsubmitted
Not Done
ReplyInline Actions

Comment still needs updating.

foad: Comment still needs updating.
// G_SHL/G_ASHR/G_LSHR/G_USHLSAT/G_SSHLSAT shift instructions in combination
// with any of G_AND/G_OR/G_XOR logic instructions.
// %t1 = SHIFT %X, G_CONSTANT C0
// %t2 = LOGIC %t1, %Y
// %root = SHIFT %t2, G_CONSTANT C1
// -->
// %t3 = SHIFT %X, G_CONSTANT (C0+C1)
// %t4 = SHIFT %Y, G_CONSTANT C1
// %root = LOGIC %t3, %t4
unsigned ShiftOpcode = MI.getOpcode();
assert((ShiftOpcode == TargetOpcode::G_SHL ||
ShiftOpcode == TargetOpcode::G_ASHR ||
ShiftOpcode == TargetOpcode::G_LSHR ||
ShiftOpcode == TargetOpcode::G_USHLSAT ||
ShiftOpcode == TargetOpcode::G_SSHLSAT) &&
"Expected G_SHL, G_ASHR, G_LSHR, G_USHLSAT and G_SSHLSAT");
// Match a one-use bitwise logic op.
Register LogicDest = MI.getOperand(1).getReg();
if (!MRI.hasOneNonDBGUse(LogicDest))
return false;
MachineInstr *LogicMI = MRI.getUniqueVRegDef(LogicDest);
unsigned LogicOpcode = LogicMI->getOpcode();
if (LogicOpcode != TargetOpcode::G_AND && LogicOpcode != TargetOpcode::G_OR &&
LogicOpcode != TargetOpcode::G_XOR)
return false;
// Find a matching one-use shift by constant.
const Register C1 = MI.getOperand(2).getReg();
auto MaybeImmVal = getConstantVRegValWithLookThrough(C1, MRI);
if (!MaybeImmVal)
return false;
const uint64_t C1Val = MaybeImmVal->Value;
auto matchFirstShift = [&](const MachineInstr *MI, uint64_t &ShiftVal) {
// Shift should match previous one and should be a one-use.
if (MI->getOpcode() != ShiftOpcode ||
!MRI.hasOneNonDBGUse(MI->getOperand(0).getReg()))
return false;
// Must be a constant.
auto MaybeImmVal =
getConstantVRegValWithLookThrough(MI->getOperand(2).getReg(), MRI);
if (!MaybeImmVal)
return false;
foadUnsubmitted
Done
ReplyInline Actions

I don't see why this check is necessary. All we care about is the shift amount, as a uint64_t.

foad: I don't see why this check is necessary. All we care about is the shift amount, as a uint64_t.
ShiftVal = MaybeImmVal->Value;
return true;
};
// Logic ops are commutative, so check each operand for a match.
Register LogicMIReg1 = LogicMI->getOperand(1).getReg();
MachineInstr *LogicMIOp1 = MRI.getUniqueVRegDef(LogicMIReg1);
Register LogicMIReg2 = LogicMI->getOperand(2).getReg();
MachineInstr *LogicMIOp2 = MRI.getUniqueVRegDef(LogicMIReg2);
foadUnsubmitted
Done
ReplyInline Actions

First, it would be simpler to check this by line 1690 where you're already computing the sum. Second, I would expect the > to be >=. Third, you're comparing against BitWidth which is the width of the shift amount, not the value being shifted.

foad: First, it would be simpler to check this by line 1690 where you're already computing the sum.
uint64_t C0Val;
if (matchFirstShift(LogicMIOp1, C0Val)) {
MatchInfo.LogicNonShiftReg = LogicMIReg2;
MatchInfo.Shift2 = LogicMIOp1;
} else if (matchFirstShift(LogicMIOp2, C0Val)) {
MatchInfo.LogicNonShiftReg = LogicMIReg1;
MatchInfo.Shift2 = LogicMIOp2;
} else
return false;
MatchInfo.ValSum = C0Val + C1Val;
// The fold is not valid if the sum of the shift values exceeds bitwidth.
if (MatchInfo.ValSum >= MRI.getType(LogicDest).getScalarSizeInBits())
return false;
MatchInfo.Logic = LogicMI;
return true;
}
bool CombinerHelper::applyShiftOfShiftedLogic(MachineInstr &MI,
ShiftOfShiftedLogic &MatchInfo) {
unsigned Opcode = MI.getOpcode();
assert((Opcode == TargetOpcode::G_SHL || Opcode == TargetOpcode::G_ASHR ||
Opcode == TargetOpcode::G_LSHR || Opcode == TargetOpcode::G_USHLSAT ||
Opcode == TargetOpcode::G_SSHLSAT) &&
"Expected G_SHL, G_ASHR, G_LSHR, G_USHLSAT and G_SSHLSAT");
LLT ShlType = MRI.getType(MI.getOperand(2).getReg());
LLT DestType = MRI.getType(MI.getOperand(0).getReg());
Builder.setInstrAndDebugLoc(MI);
Register Const = Builder.buildConstant(ShlType, MatchInfo.ValSum).getReg(0);
foadUnsubmitted
Done
ReplyInline Actions

Don't create this. CombinerHelper already has a MIRBuilder.

foad: Don't create this. CombinerHelper already has a MIRBuilder.
Register Shift1Base = MatchInfo.Shift2->getOperand(1).getReg();
Register Shift1 =
Builder.buildInstr(Opcode, {DestType}, {Shift1Base, Const}).getReg(0);
Register Shift2Const = MI.getOperand(2).getReg();
Register Shift2 = Builder
foadUnsubmitted
Done
ReplyInline Actions

ShlType is wrong here and below. You want the type of the result, not the type of the shift amount.

foad: ShlType is wrong here and below. You want the type of the result, not the type of the shift…
.buildInstr(Opcode, {DestType},
{MatchInfo.LogicNonShiftReg, Shift2Const})
.getReg(0);
Register Dest = MI.getOperand(0).getReg();
Builder.buildInstr(MatchInfo.Logic->getOpcode(), {Dest}, {Shift1, Shift2});
// These were one use so it's safe to remove them.
MatchInfo.Shift2->eraseFromParent();
MatchInfo.Logic->eraseFromParent();
MI.eraseFromParent();
foadUnsubmitted
Done
ReplyInline Actions

It's probably not worth doing this. I think you can rely on dead code elimination.

foad: It's probably not worth doing this. I think you can rely on dead code elimination.
return true;
}
bool CombinerHelper::matchCombineMulToShl(MachineInstr &MI, bool CombinerHelper::matchCombineMulToShl(MachineInstr &MI,
unsigned &ShiftVal) { unsigned &ShiftVal) {
assert(MI.getOpcode() == TargetOpcode::G_MUL && "Expected a G_MUL"); assert(MI.getOpcode() == TargetOpcode::G_MUL && "Expected a G_MUL");
auto MaybeImmVal = auto MaybeImmVal =
getConstantVRegValWithLookThrough(MI.getOperand(2).getReg(), MRI); getConstantVRegValWithLookThrough(MI.getOperand(2).getReg(), MRI);
if (!MaybeImmVal || !isPowerOf2_64(MaybeImmVal->Value)) if (!MaybeImmVal || !isPowerOf2_64(MaybeImmVal->Value))
return false; return false;
ShiftVal = Log2_64(MaybeImmVal->Value); ShiftVal = Log2_64(MaybeImmVal->Value);
▲ Show 20 Lines • Show All 1,344 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-of-shifted-logic-shlsat.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
---
name: ushlsat_and_1
tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0
; CHECK-LABEL: name: ushlsat_and_1
; CHECK: liveins: $sgpr0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1073741820
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK: [[USHLSAT:%[0-9]+]]:_(s32) = G_USHLSAT [[COPY]], [[C2]](s32)
; CHECK: [[USHLSAT1:%[0-9]+]]:_(s32) = G_USHLSAT [[C1]], [[C]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[USHLSAT]], [[USHLSAT1]]
; CHECK: $sgpr0 = COPY [[AND]](s32)
; CHECK: SI_RETURN_TO_EPILOG implicit $sgpr0
%0:_(s32) = COPY $sgpr0
%2:_(s32) = G_CONSTANT i32 2
%4:_(s32) = G_CONSTANT i32 1073741820
%3:_(s32) = G_USHLSAT %0, %2(s32)
%5:_(s32) = G_AND %3, %4
%6:_(s32) = G_USHLSAT %5, %2(s32)
$sgpr0 = COPY %6(s32)
SI_RETURN_TO_EPILOG implicit $sgpr0
...
---
name: ushlsat_and_2
tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0
; CHECK-LABEL: name: ushlsat_and_2
; CHECK: liveins: $sgpr0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 536870880
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[USHLSAT:%[0-9]+]]:_(s32) = G_USHLSAT [[COPY]], [[C2]](s32)
; CHECK: [[USHLSAT1:%[0-9]+]]:_(s32) = G_USHLSAT [[C]], [[C1]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[USHLSAT]], [[USHLSAT1]]
; CHECK: $sgpr0 = COPY [[AND]](s32)
; CHECK: SI_RETURN_TO_EPILOG implicit $sgpr0
%0:_(s32) = COPY $sgpr0
%2:_(s32) = G_CONSTANT i32 5
%4:_(s32) = G_CONSTANT i32 536870880
%6:_(s32) = G_CONSTANT i32 3
%3:_(s32) = G_USHLSAT %0, %2(s32)
%5:_(s32) = G_AND %3, %4
%7:_(s32) = G_USHLSAT %5, %6(s32)
$sgpr0 = COPY %7(s32)
SI_RETURN_TO_EPILOG implicit $sgpr0
...
---
name: ushlsat_and_3
tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0
; CHECK-LABEL: name: ushlsat_and_3
; CHECK: liveins: $sgpr0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65536
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 19
; CHECK: [[USHLSAT:%[0-9]+]]:_(s32) = G_USHLSAT [[COPY]], [[C2]](s32)
; CHECK: [[USHLSAT1:%[0-9]+]]:_(s32) = G_USHLSAT [[C]], [[C1]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[USHLSAT]], [[USHLSAT1]]
; CHECK: $sgpr0 = COPY [[AND]](s32)
; CHECK: SI_RETURN_TO_EPILOG implicit $sgpr0
%0:_(s32) = COPY $sgpr0
%2:_(s32) = G_CONSTANT i32 3
%4:_(s32) = G_CONSTANT i32 65536
%6:_(s32) = G_CONSTANT i32 16
%3:_(s32) = G_USHLSAT %0, %2(s32)
%5:_(s32) = G_AND %3, %4
%7:_(s32) = G_USHLSAT %5, %6(s32)
$sgpr0 = COPY %7(s32)
SI_RETURN_TO_EPILOG implicit $sgpr0
...
---
name: ushlsat_or_1
tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0
; CHECK-LABEL: name: ushlsat_or_1
; CHECK: liveins: $sgpr0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1073741821
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK: [[USHLSAT:%[0-9]+]]:_(s32) = G_USHLSAT [[COPY]], [[C2]](s32)
; CHECK: [[USHLSAT1:%[0-9]+]]:_(s32) = G_USHLSAT [[C1]], [[C]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[USHLSAT]], [[USHLSAT1]]
; CHECK: $sgpr0 = COPY [[OR]](s32)
; CHECK: SI_RETURN_TO_EPILOG implicit $sgpr0
%0:_(s32) = COPY $sgpr0
%2:_(s32) = G_CONSTANT i32 2
%4:_(s32) = G_CONSTANT i32 -1073741821
%3:_(s32) = G_USHLSAT %0, %2(s32)
%5:_(s32) = G_OR %3, %4
%6:_(s32) = G_USHLSAT %5, %2(s32)
$sgpr0 = COPY %6(s32)
SI_RETURN_TO_EPILOG implicit $sgpr0
...
---
name: ushlsat_or_2
tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0
; CHECK-LABEL: name: ushlsat_or_2
; CHECK: liveins: $sgpr0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -536870881
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[USHLSAT:%[0-9]+]]:_(s32) = G_USHLSAT [[COPY]], [[C2]](s32)
; CHECK: [[USHLSAT1:%[0-9]+]]:_(s32) = G_USHLSAT [[C]], [[C1]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[USHLSAT]], [[USHLSAT1]]
; CHECK: $sgpr0 = COPY [[OR]](s32)
; CHECK: SI_RETURN_TO_EPILOG implicit $sgpr0
%0:_(s32) = COPY $sgpr0
%2:_(s32) = G_CONSTANT i32 5
%4:_(s32) = G_CONSTANT i32 -536870881
%6:_(s32) = G_CONSTANT i32 3
%3:_(s32) = G_USHLSAT %0, %2(s32)
%5:_(s32) = G_OR %3, %4
%7:_(s32) = G_USHLSAT %5, %6(s32)
$sgpr0 = COPY %7(s32)
SI_RETURN_TO_EPILOG implicit $sgpr0
...
---
name: ushlsat_or_3
tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0
; CHECK-LABEL: name: ushlsat_or_3
; CHECK: liveins: $sgpr0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65536
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 19
; CHECK: [[USHLSAT:%[0-9]+]]:_(s32) = G_USHLSAT [[COPY]], [[C2]](s32)
; CHECK: [[USHLSAT1:%[0-9]+]]:_(s32) = G_USHLSAT [[C]], [[C1]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[USHLSAT]], [[USHLSAT1]]
; CHECK: $sgpr0 = COPY [[OR]](s32)
; CHECK: SI_RETURN_TO_EPILOG implicit $sgpr0
%0:_(s32) = COPY $sgpr0
%2:_(s32) = G_CONSTANT i32 3
%4:_(s32) = G_CONSTANT i32 65536
%6:_(s32) = G_CONSTANT i32 16
%3:_(s32) = G_USHLSAT %0, %2(s32)
%5:_(s32) = G_OR %3, %4
%7:_(s32) = G_USHLSAT %5, %6(s32)
$sgpr0 = COPY %7(s32)
SI_RETURN_TO_EPILOG implicit $sgpr0
...
---
name: ushlsat_xor
tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0
; CHECK-LABEL: name: ushlsat_xor
; CHECK: liveins: $sgpr0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 43690
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[USHLSAT:%[0-9]+]]:_(s32) = G_USHLSAT [[COPY]], [[C2]](s32)
; CHECK: [[USHLSAT1:%[0-9]+]]:_(s32) = G_USHLSAT [[C]], [[C1]](s32)
; CHECK: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[USHLSAT]], [[USHLSAT1]]
; CHECK: $sgpr0 = COPY [[XOR]](s32)
; CHECK: SI_RETURN_TO_EPILOG implicit $sgpr0
%0:_(s32) = COPY $sgpr0
%2:_(s32) = G_CONSTANT i32 3
%4:_(s32) = G_CONSTANT i32 43690
%6:_(s32) = G_CONSTANT i32 5
%3:_(s32) = G_USHLSAT %0, %2(s32)
%5:_(s32) = G_XOR %3, %4
%7:_(s32) = G_USHLSAT %5, %6(s32)
$sgpr0 = COPY %7(s32)
SI_RETURN_TO_EPILOG implicit $sgpr0
...
---
name: sshlsat_and_1
tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0
; CHECK-LABEL: name: sshlsat_and_1
; CHECK: liveins: $sgpr0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1073741820
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK: [[SSHLSAT:%[0-9]+]]:_(s32) = G_SSHLSAT [[COPY]], [[C2]](s32)
; CHECK: [[SSHLSAT1:%[0-9]+]]:_(s32) = G_SSHLSAT [[C1]], [[C]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[SSHLSAT]], [[SSHLSAT1]]
; CHECK: $sgpr0 = COPY [[AND]](s32)
; CHECK: SI_RETURN_TO_EPILOG implicit $sgpr0
%0:_(s32) = COPY $sgpr0
%2:_(s32) = G_CONSTANT i32 2
%4:_(s32) = G_CONSTANT i32 1073741820
%3:_(s32) = G_SSHLSAT %0, %2(s32)
%5:_(s32) = G_AND %3, %4
%6:_(s32) = G_SSHLSAT %5, %2(s32)
$sgpr0 = COPY %6(s32)
SI_RETURN_TO_EPILOG implicit $sgpr0
...
---
name: sshlsat_and_2
tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0
; CHECK-LABEL: name: sshlsat_and_2
; CHECK: liveins: $sgpr0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 536870880
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[SSHLSAT:%[0-9]+]]:_(s32) = G_SSHLSAT [[COPY]], [[C2]](s32)
; CHECK: [[SSHLSAT1:%[0-9]+]]:_(s32) = G_SSHLSAT [[C]], [[C1]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[SSHLSAT]], [[SSHLSAT1]]
; CHECK: $sgpr0 = COPY [[AND]](s32)
; CHECK: SI_RETURN_TO_EPILOG implicit $sgpr0
%0:_(s32) = COPY $sgpr0
%2:_(s32) = G_CONSTANT i32 5
%4:_(s32) = G_CONSTANT i32 536870880
%6:_(s32) = G_CONSTANT i32 3
%3:_(s32) = G_SSHLSAT %0, %2(s32)
%5:_(s32) = G_AND %3, %4
%7:_(s32) = G_SSHLSAT %5, %6(s32)
$sgpr0 = COPY %7(s32)
SI_RETURN_TO_EPILOG implicit $sgpr0
...
---
name: sshlsat_and_3
tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0
; CHECK-LABEL: name: sshlsat_and_3
; CHECK: liveins: $sgpr0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65536
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 19
; CHECK: [[SSHLSAT:%[0-9]+]]:_(s32) = G_SSHLSAT [[COPY]], [[C2]](s32)
; CHECK: [[SSHLSAT1:%[0-9]+]]:_(s32) = G_SSHLSAT [[C]], [[C1]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[SSHLSAT]], [[SSHLSAT1]]
; CHECK: $sgpr0 = COPY [[AND]](s32)
; CHECK: SI_RETURN_TO_EPILOG implicit $sgpr0
%0:_(s32) = COPY $sgpr0
%2:_(s32) = G_CONSTANT i32 3
%4:_(s32) = G_CONSTANT i32 65536
%6:_(s32) = G_CONSTANT i32 16
%3:_(s32) = G_SSHLSAT %0, %2(s32)
%5:_(s32) = G_AND %3, %4
%7:_(s32) = G_SSHLSAT %5, %6(s32)
$sgpr0 = COPY %7(s32)
SI_RETURN_TO_EPILOG implicit $sgpr0
...
---
name: sshlsat_or_1
tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0
; CHECK-LABEL: name: sshlsat_or_1
; CHECK: liveins: $sgpr0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1073741821
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK: [[SSHLSAT:%[0-9]+]]:_(s32) = G_SSHLSAT [[COPY]], [[C2]](s32)
; CHECK: [[SSHLSAT1:%[0-9]+]]:_(s32) = G_SSHLSAT [[C1]], [[C]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[SSHLSAT]], [[SSHLSAT1]]
; CHECK: $sgpr0 = COPY [[OR]](s32)
; CHECK: SI_RETURN_TO_EPILOG implicit $sgpr0
%0:_(s32) = COPY $sgpr0
%2:_(s32) = G_CONSTANT i32 2
%4:_(s32) = G_CONSTANT i32 -1073741821
%3:_(s32) = G_SSHLSAT %0, %2(s32)
%5:_(s32) = G_OR %3, %4
%6:_(s32) = G_SSHLSAT %5, %2(s32)
$sgpr0 = COPY %6(s32)
SI_RETURN_TO_EPILOG implicit $sgpr0
...
---
name: sshlsat_or_2
tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0
; CHECK-LABEL: name: sshlsat_or_2
; CHECK: liveins: $sgpr0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -536870881
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[SSHLSAT:%[0-9]+]]:_(s32) = G_SSHLSAT [[COPY]], [[C2]](s32)
; CHECK: [[SSHLSAT1:%[0-9]+]]:_(s32) = G_SSHLSAT [[C]], [[C1]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[SSHLSAT]], [[SSHLSAT1]]
; CHECK: $sgpr0 = COPY [[OR]](s32)
; CHECK: SI_RETURN_TO_EPILOG implicit $sgpr0
%0:_(s32) = COPY $sgpr0
%2:_(s32) = G_CONSTANT i32 5
%4:_(s32) = G_CONSTANT i32 -536870881
%6:_(s32) = G_CONSTANT i32 3
%3:_(s32) = G_SSHLSAT %0, %2(s32)
%5:_(s32) = G_OR %3, %4
%7:_(s32) = G_SSHLSAT %5, %6(s32)
$sgpr0 = COPY %7(s32)
SI_RETURN_TO_EPILOG implicit $sgpr0
...
---
name: sshlsat_or_3
tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0
; CHECK-LABEL: name: sshlsat_or_3
; CHECK: liveins: $sgpr0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65536
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 19
; CHECK: [[SSHLSAT:%[0-9]+]]:_(s32) = G_SSHLSAT [[COPY]], [[C2]](s32)
; CHECK: [[SSHLSAT1:%[0-9]+]]:_(s32) = G_SSHLSAT [[C]], [[C1]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[SSHLSAT]], [[SSHLSAT1]]
; CHECK: $sgpr0 = COPY [[OR]](s32)
; CHECK: SI_RETURN_TO_EPILOG implicit $sgpr0
%0:_(s32) = COPY $sgpr0
%2:_(s32) = G_CONSTANT i32 3
%4:_(s32) = G_CONSTANT i32 65536
%6:_(s32) = G_CONSTANT i32 16
%3:_(s32) = G_SSHLSAT %0, %2(s32)
%5:_(s32) = G_OR %3, %4
%7:_(s32) = G_SSHLSAT %5, %6(s32)
$sgpr0 = COPY %7(s32)
SI_RETURN_TO_EPILOG implicit $sgpr0
...
---
name: sshlsat_xor
tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0
; CHECK-LABEL: name: sshlsat_xor
; CHECK: liveins: $sgpr0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 43690
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[SSHLSAT:%[0-9]+]]:_(s32) = G_SSHLSAT [[COPY]], [[C2]](s32)
; CHECK: [[SSHLSAT1:%[0-9]+]]:_(s32) = G_SSHLSAT [[C]], [[C1]](s32)
; CHECK: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[SSHLSAT]], [[SSHLSAT1]]
; CHECK: $sgpr0 = COPY [[XOR]](s32)
; CHECK: SI_RETURN_TO_EPILOG implicit $sgpr0
%0:_(s32) = COPY $sgpr0
%2:_(s32) = G_CONSTANT i32 3
%4:_(s32) = G_CONSTANT i32 43690
%6:_(s32) = G_CONSTANT i32 5
%3:_(s32) = G_SSHLSAT %0, %2(s32)
%5:_(s32) = G_XOR %3, %4
%7:_(s32) = G_SSHLSAT %5, %6(s32)
$sgpr0 = COPY %7(s32)
SI_RETURN_TO_EPILOG implicit $sgpr0
...

llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-of-shifted-logic.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -march=amdgcn -verify-machineinstrs < %s | FileCheck %s
define amdgpu_cs i32 @test_shl_and_1(i32 inreg %arg1) {
; CHECK-LABEL: test_shl_and_1:
; CHECK: ; %bb.0: ; %.entry
; CHECK-NEXT: s_lshl_b32 s0, s0, 4
; CHECK-NEXT: s_and_b32 s0, s0, -16
; CHECK-NEXT: ; return to shader part epilog
mbrkusaninAuthorUnsubmitted
Done
ReplyInline Actions

This can be simplified to a single instruction:
s_lshl_b32 s0, s0, 4
but that will be a different combine.

Same goes for a few more cases below.

mbrkusanin: This can be simplified to a single instruction: s_lshl_b32 s0, s0, 4 but that will be a…
.entry:
%z1 = shl i32 %arg1, 2
%z2 = and i32 %z1, 1073741820
%z3 = shl i32 %z2, 2
ret i32 %z3
}
define amdgpu_cs i32 @test_shl_and_2(i32 inreg %arg1) {
; CHECK-LABEL: test_shl_and_2:
; CHECK: ; %bb.0: ; %.entry
; CHECK-NEXT: s_lshl_b32 s0, s0, 8
; CHECK-NEXT: s_and_b32 s0, s0, 0xffffff00
; CHECK-NEXT: ; return to shader part epilog
.entry:
%z1 = shl i32 %arg1, 5
%z2 = and i32 %z1, 536870880
%z3 = shl i32 %z2, 3
ret i32 %z3
}
define amdgpu_cs i32 @test_shl_and_3(i32 inreg %arg1) {
; CHECK-LABEL: test_shl_and_3:
; CHECK: ; %bb.0: ; %.entry
; CHECK-NEXT: s_lshl_b32 s0, s0, 5
; CHECK-NEXT: s_and_b32 s0, s0, 0x7ffffff0
; CHECK-NEXT: ; return to shader part epilog
.entry:
%z1 = shl i32 %arg1, 3
%z2 = and i32 %z1, 536870908
%z3 = shl i32 %z2, 2
ret i32 %z3
}
define amdgpu_cs i32 @test_lshr_and_1(i32 inreg %arg1) {
; CHECK-LABEL: test_lshr_and_1:
; CHECK: ; %bb.0: ; %.entry
; CHECK-NEXT: s_lshr_b32 s0, s0, 4
; CHECK-NEXT: s_and_b32 s0, s0, 0xfffffff
; CHECK-NEXT: ; return to shader part epilog
.entry:
%z1 = lshr i32 %arg1, 2
%z2 = and i32 %z1, 1073741820
%z3 = lshr i32 %z2, 2
ret i32 %z3
}
define amdgpu_cs i32 @test_lshr_and_2(i32 inreg %arg1) {
; CHECK-LABEL: test_lshr_and_2:
; CHECK: ; %bb.0: ; %.entry
; CHECK-NEXT: s_lshr_b32 s0, s0, 8
; CHECK-NEXT: s_and_b32 s0, s0, 0x3fffffc
; CHECK-NEXT: ; return to shader part epilog
.entry:
%z1 = lshr i32 %arg1, 5
%z2 = and i32 %z1, 536870880
%z3 = lshr i32 %z2, 3
ret i32 %z3
}
define amdgpu_cs i32 @test_lshr_and_3(i32 inreg %arg1) {
; CHECK-LABEL: test_lshr_and_3:
; CHECK: ; %bb.0: ; %.entry
; CHECK-NEXT: s_lshr_b32 s0, s0, 5
; CHECK-NEXT: s_and_b32 s0, s0, 0x7ffffff
; CHECK-NEXT: ; return to shader part epilog
.entry:
%z1 = lshr i32 %arg1, 3
%z2 = and i32 %z1, 536870908
%z3 = lshr i32 %z2, 2
ret i32 %z3
}
define amdgpu_cs i32 @test_ashr_and_1(i32 inreg %arg1) {
; CHECK-LABEL: test_ashr_and_1:
; CHECK: ; %bb.0: ; %.entry
; CHECK-NEXT: s_ashr_i32 s0, s0, 4
; CHECK-NEXT: s_and_b32 s0, s0, 0xfffffff
; CHECK-NEXT: ; return to shader part epilog
.entry:
%z1 = ashr i32 %arg1, 2
%z2 = and i32 %z1, 1073741820
%z3 = ashr i32 %z2, 2
ret i32 %z3
}
define amdgpu_cs i32 @test_ashr_and_2(i32 inreg %arg1) {
; CHECK-LABEL: test_ashr_and_2:
; CHECK: ; %bb.0: ; %.entry
; CHECK-NEXT: s_ashr_i32 s0, s0, 8
; CHECK-NEXT: s_and_b32 s0, s0, 0x3fffffc
; CHECK-NEXT: ; return to shader part epilog
.entry:
%z1 = ashr i32 %arg1, 5
%z2 = and i32 %z1, 536870880
%z3 = ashr i32 %z2, 3
ret i32 %z3
}
define amdgpu_cs i32 @test_ashr_and_3(i32 inreg %arg1) {
; CHECK-LABEL: test_ashr_and_3:
; CHECK: ; %bb.0: ; %.entry
; CHECK-NEXT: s_ashr_i32 s0, s0, 5
; CHECK-NEXT: s_and_b32 s0, s0, 0x7ffffff
; CHECK-NEXT: ; return to shader part epilog
.entry:
%z1 = ashr i32 %arg1, 3
%z2 = and i32 %z1, 536870908
%z3 = ashr i32 %z2, 2
ret i32 %z3
}
define amdgpu_cs i32 @test_shl_or_1(i32 inreg %arg1) {
; CHECK-LABEL: test_shl_or_1:
; CHECK: ; %bb.0: ; %.entry
; CHECK-NEXT: s_lshl_b32 s0, s0, 4
; CHECK-NEXT: s_or_b32 s0, s0, 12
; CHECK-NEXT: ; return to shader part epilog
.entry:
%z1 = shl i32 %arg1, 2
%z2 = or i32 %z1, 3221225475
%z3 = shl i32 %z2, 2
ret i32 %z3
}
define amdgpu_cs i32 @test_shl_or_2(i32 inreg %arg1) {
; CHECK-LABEL: test_shl_or_2:
; CHECK: ; %bb.0: ; %.entry
; CHECK-NEXT: s_lshl_b32 s0, s0, 8
; CHECK-NEXT: s_or_b32 s0, s0, 0xfffffc00
; CHECK-NEXT: ; return to shader part epilog
.entry:
%z1 = shl i32 %arg1, 3
%z2 = or i32 %z1, 536870880
%z3 = shl i32 %z2, 5
ret i32 %z3
}
define amdgpu_cs i32 @test_shl_or_3(i32 inreg %arg1) {
; CHECK-LABEL: test_shl_or_3:
; CHECK: ; %bb.0: ; %.entry
; CHECK-NEXT: s_lshl_b32 s0, s0, 5
; CHECK-NEXT: s_or_b32 s0, s0, 0x7fffff80
; CHECK-NEXT: ; return to shader part epilog
.entry:
%z1 = shl i32 %arg1, 2
%z2 = or i32 %z1, 268435440
%z3 = shl i32 %z2, 3
ret i32 %z3
}
define amdgpu_cs i32 @test_lshr_or_1(i32 inreg %arg1) {
; CHECK-LABEL: test_lshr_or_1:
; CHECK: ; %bb.0: ; %.entry
; CHECK-NEXT: s_lshr_b32 s0, s0, 4
; CHECK-NEXT: ; return to shader part epilog
.entry:
%z1 = lshr i32 %arg1, 2
%z2 = or i32 %z1, 3
%z3 = lshr i32 %z2, 2
ret i32 %z3
}
define amdgpu_cs i32 @test_lshr_or_2(i32 inreg %arg1) {
; CHECK-LABEL: test_lshr_or_2:
; CHECK: ; %bb.0: ; %.entry
; CHECK-NEXT: s_lshr_b32 s0, s0, 8
; CHECK-NEXT: s_or_b32 s0, s0, 0xffffff
; CHECK-NEXT: ; return to shader part epilog
.entry:
%z1 = lshr i32 %arg1, 3
%z2 = or i32 %z1, 536870880
%z3 = lshr i32 %z2, 5
ret i32 %z3
}
define amdgpu_cs i32 @test_lshr_or_3(i32 inreg %arg1) {
; CHECK-LABEL: test_lshr_or_3:
; CHECK: ; %bb.0: ; %.entry
; CHECK-NEXT: s_lshr_b32 s0, s0, 5
; CHECK-NEXT: s_or_b32 s0, s0, 0x1fffffe
; CHECK-NEXT: ; return to shader part epilog
.entry:
%z1 = lshr i32 %arg1, 2
%z2 = or i32 %z1, 268435440
%z3 = lshr i32 %z2, 3
ret i32 %z3
}
define amdgpu_cs i32 @test_ashr_or_1(i32 inreg %arg1) {
; CHECK-LABEL: test_ashr_or_1:
; CHECK: ; %bb.0: ; %.entry
; CHECK-NEXT: s_ashr_i32 s0, s0, 4
; CHECK-NEXT: ; return to shader part epilog
.entry:
%z1 = ashr i32 %arg1, 2
%z2 = or i32 %z1, 3
%z3 = ashr i32 %z2, 2
ret i32 %z3
}
define amdgpu_cs i32 @test_ashr_or_2(i32 inreg %arg1) {
; CHECK-LABEL: test_ashr_or_2:
; CHECK: ; %bb.0: ; %.entry
; CHECK-NEXT: s_ashr_i32 s0, s0, 8
; CHECK-NEXT: s_or_b32 s0, s0, 0xffffff
; CHECK-NEXT: ; return to shader part epilog
.entry:
%z1 = ashr i32 %arg1, 3
%z2 = or i32 %z1, 536870880
%z3 = ashr i32 %z2, 5
ret i32 %z3
}
define amdgpu_cs i32 @test_ashr_or_3(i32 inreg %arg1) {
; CHECK-LABEL: test_ashr_or_3:
; CHECK: ; %bb.0: ; %.entry
; CHECK-NEXT: s_ashr_i32 s0, s0, 5
; CHECK-NEXT: s_or_b32 s0, s0, 0x1fffffe
; CHECK-NEXT: ; return to shader part epilog
.entry:
%z1 = ashr i32 %arg1, 2
%z2 = or i32 %z1, 268435440
%z3 = ashr i32 %z2, 3
ret i32 %z3
}
define amdgpu_cs i32 @test_shl_xor_1(i32 inreg %arg1) {
; CHECK-LABEL: test_shl_xor_1:
; CHECK: ; %bb.0: ; %.entry
; CHECK-NEXT: s_lshl_b32 s0, s0, 4
; CHECK-NEXT: s_xor_b32 s0, s0, -16
; CHECK-NEXT: ; return to shader part epilog
.entry:
%z1 = shl i32 %arg1, 2
%z2 = xor i32 %z1, 1073741820
%z3 = shl i32 %z2, 2
ret i32 %z3
}
define amdgpu_cs i32 @test_shl_xor_2(i32 inreg %arg1) {
; CHECK-LABEL: test_shl_xor_2:
; CHECK: ; %bb.0: ; %.entry
; CHECK-NEXT: s_lshl_b32 s0, s0, 6
; CHECK-NEXT: ; return to shader part epilog
.entry:
%z1 = shl i32 %arg1, 1
%z2 = xor i32 %z1, 4160749568
%z3 = shl i32 %z2, 5
ret i32 %z3
}
define amdgpu_cs i32 @test_shl_xor_3(i32 inreg %arg1) {
; CHECK-LABEL: test_shl_xor_3:
; CHECK: ; %bb.0: ; %.entry
; CHECK-NEXT: s_lshl_b32 s0, s0, 5
; CHECK-NEXT: s_xor_b32 s0, s0, 56
; CHECK-NEXT: ; return to shader part epilog
.entry:
%z1 = shl i32 %arg1, 2
%z2 = xor i32 %z1, 3221225479
%z3 = shl i32 %z2, 3
ret i32 %z3
}
define amdgpu_cs i32 @test_lshr_xor_1(i32 inreg %arg1) {
; CHECK-LABEL: test_lshr_xor_1:
; CHECK: ; %bb.0: ; %.entry
; CHECK-NEXT: s_lshr_b32 s0, s0, 4
; CHECK-NEXT: s_xor_b32 s0, s0, 0xfffffff
; CHECK-NEXT: ; return to shader part epilog
.entry:
%z1 = lshr i32 %arg1, 2
%z2 = xor i32 %z1, 1073741820
%z3 = lshr i32 %z2, 2
ret i32 %z3
}
define amdgpu_cs i32 @test_lshr_xor_2(i32 inreg %arg1) {
; CHECK-LABEL: test_lshr_xor_2:
; CHECK: ; %bb.0: ; %.entry
; CHECK-NEXT: s_lshr_b32 s0, s0, 6
; CHECK-NEXT: ; return to shader part epilog
.entry:
%z1 = lshr i32 %arg1, 1
%z2 = xor i32 %z1, 31
%z3 = lshr i32 %z2, 5
ret i32 %z3
}
define amdgpu_cs i32 @test_lshr_xor_3(i32 inreg %arg1) {
; CHECK-LABEL: test_lshr_xor_3:
; CHECK: ; %bb.0: ; %.entry
; CHECK-NEXT: s_lshr_b32 s0, s0, 5
; CHECK-NEXT: s_xor_b32 s0, s0, 0x18000000
; CHECK-NEXT: ; return to shader part epilog
.entry:
%z1 = lshr i32 %arg1, 2
%z2 = xor i32 %z1, 3221225479
%z3 = lshr i32 %z2, 3
ret i32 %z3
}
define amdgpu_cs i32 @test_ashr_xor_1(i32 inreg %arg1) {
; CHECK-LABEL: test_ashr_xor_1:
; CHECK: ; %bb.0: ; %.entry
; CHECK-NEXT: s_ashr_i32 s0, s0, 4
; CHECK-NEXT: s_xor_b32 s0, s0, 0xfffffff
; CHECK-NEXT: ; return to shader part epilog
.entry:
%z1 = ashr i32 %arg1, 2
%z2 = xor i32 %z1, 1073741820
%z3 = ashr i32 %z2, 2
ret i32 %z3
}
define amdgpu_cs i32 @test_ashr_xor_2(i32 inreg %arg1) {
; CHECK-LABEL: test_ashr_xor_2:
; CHECK: ; %bb.0: ; %.entry
; CHECK-NEXT: s_ashr_i32 s0, s0, 6
; CHECK-NEXT: ; return to shader part epilog
.entry:
%z1 = ashr i32 %arg1, 1
%z2 = xor i32 %z1, 31
%z3 = ashr i32 %z2, 5
ret i32 %z3
}
define amdgpu_cs i32 @test_ashr_xor_3(i32 inreg %arg1) {
; CHECK-LABEL: test_ashr_xor_3:
; CHECK: ; %bb.0: ; %.entry
; CHECK-NEXT: s_ashr_i32 s0, s0, 5
; CHECK-NEXT: s_xor_b32 s0, s0, 0xf8000000
; CHECK-NEXT: ; return to shader part epilog
.entry:
%z1 = ashr i32 %arg1, 2
%z2 = xor i32 %z1, 3221225479
%z3 = ashr i32 %z2, 3
ret i32 %z3
}