AMDGPU/GlobalISel: Add floating point med3 combine

[Petar.Avramovic]

Summary

Add floating point version of med3 combine.
Source is fminnum(fmaxnum(Val, K0), K1) or fmaxnum(fminnum(Val, K1), K0)
where K0 and K1 are constants and K0 <= K1.

[arsenm]

Missing tests for f16 and v2f16 cases

llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp

174–175

Might as well handle this now

181–182

You can directly pass the APFloat to is the overload of isInlineConstant

[Petar.Avramovic]

llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp

174–175

I am not really sure I know correct way to do it. Also this combine heavily depends on legalizer and primarily completing remaining of SNaN checks in isKnownNeverSNaN.

[foad]

llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp

172

This will probably warn that Info is unused in a Release build.

[Petar.Avramovic]

Rebase/rework.

[Petar.Avramovic]

Ping.

[arsenm]

llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp

179 ↗

(On Diff #352504)

Like in the other patches, why do you need to re-query getConstantFPVRegVal? Why doesn't the constant matcher just directly return the constant?

[Petar.Avramovic]

Use matcher that returns both VReg and APFloat from G_FCONSTANT.

[Petar.Avramovic]

Ping.

[Petar.Avramovic]

Ping.

[Petar.Avramovic]

Rebase and ping.

[arsenm]

llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp

192 ↗

(On Diff #391135)

I don't see why to make these optional if they won't be set or used if the matcher return false

209 ↗

(On Diff #391135)

This should be cached in the helper?

[Petar.Avramovic]

Cache SIInstrInfo in the helper.

[Petar.Avramovic]

llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp

192 ↗

(On Diff #391135)

Util helpers and matchers use Optional.

llvm/lib/Target/AMDGPU/AMDGPUCombine.td

def cvt_f32_ubyteN : GICombineRule<
   (apply [{ applyCvtF32UByteN(*${cvt_f32_ubyteN}, ${matchinfo}); }])>;
 
 def minmax_to_med3_matchdata : GIDefMatchData<"MinMaxToMed3MatchInfo">;
 def minmax_to_med3 : GICombineRule<
   (defs root:$min_or_max, minmax_to_med3_matchdata:$matchinfo),
   (match (wip_match_opcode G_SMAX,
                            G_SMIN,
                            G_UMAX,
-                           G_UMIN):$min_or_max,
+                           G_UMIN,
+                           G_FMINNUM,
+                           G_FMAXNUM):$min_or_max,
          [{ return matchMinMaxToMed3(*${min_or_max}, MRI, ${matchinfo}); }]),
   (apply [{ applyMinMaxToMed3(*${min_or_max}, ${matchinfo}); }])>;
 
 // Combines which should only apply on SI/VI
 def gfx6gfx7_combines : GICombineGroup<[fcmp_select_to_fmin_fmax_legacy]>;
 
 
 def AMDGPUPreLegalizerCombinerHelper: GICombinerHelper<

llvm/lib/Target/AMDGPU/AMDGPUGISel.td

 def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_XOR, SIbuffer_atomic_xor>;
 def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_INC, SIbuffer_atomic_inc>;
 def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_DEC, SIbuffer_atomic_dec>;
 def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_FADD, SIbuffer_atomic_fadd>;
 def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_CMPSWAP, SIbuffer_atomic_cmpswap>;
 def : GINodeEquiv<G_AMDGPU_S_BUFFER_LOAD, SIsbuffer_load>;
 def : GINodeEquiv<G_AMDGPU_SMED3, AMDGPUsmed3>;
 def : GINodeEquiv<G_AMDGPU_UMED3, AMDGPUumed3>;
+def : GINodeEquiv<G_AMDGPU_FMED3, AMDGPUfmed3_impl>;
 
 class GISelSop2Pat <
   SDPatternOperator node,
   Instruction inst,
   ValueType dst_vt,
   ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt>   : GCNPat <
 
   (dst_vt (node (src0_vt SReg_32:$src0), (src1_vt SReg_32:$src1))),

llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp

 #include "llvm/CodeGen/GlobalISel/CombinerInfo.h"
 #include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
 #include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
 #include "llvm/CodeGen/MachineDominators.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/TargetPassConfig.h"
 #include "llvm/Support/Debug.h"
 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
+#include "SIMachineFunctionInfo.h"
 
 #define DEBUG_TYPE "amdgpu-postlegalizer-combiner"
 
 using namespace llvm;
 using namespace MIPatternMatch;
 
 namespace {
 
 struct MinMaxMedOpc {
   unsigned Min, Max, Med;
 };
 
 using MIPtr = const MachineInstr *;
 /// Returns true and stores \p MI in \p Cst if it represents constant.
 bool isConst(MIPtr MI, MachineRegisterInfo &MRI, MIPtr &Cst) {
   unsigned Opc = MI->getOpcode();
-  if (Opc == AMDGPU::G_CONSTANT) {
+  if (Opc == AMDGPU::G_CONSTANT || Opc == AMDGPU::G_FCONSTANT) {
     Cst = MI;
     return true;
   }
   // TODO: Check for fp vector splat constants(consider ignoring undef in splat
   // check). Used for clamp in f16 packed instructions.
   return false;
 }
 
MinMaxMedOpc getMinMaxPair(unsigned Opc) {
   default:
     return {0, 0, 0};
   case AMDGPU::G_SMAX:
   case AMDGPU::G_SMIN:
     return {AMDGPU::G_SMIN, AMDGPU::G_SMAX, AMDGPU::G_AMDGPU_SMED3};
   case AMDGPU::G_UMAX:
   case AMDGPU::G_UMIN:
     return {AMDGPU::G_UMIN, AMDGPU::G_UMAX, AMDGPU::G_AMDGPU_UMED3};
+  case AMDGPU::G_FMINNUM:
+  case AMDGPU::G_FMAXNUM:
+    return {AMDGPU::G_FMINNUM, AMDGPU::G_FMAXNUM, AMDGPU::G_AMDGPU_FMED3};
   }
 }
 
 bool matchMed(MachineInstr &MI, MachineRegisterInfo &MRI, MinMaxMedOpc MMMOpc,
               MIPtr &Val, MIPtr &InnerInst, MIPtr &K0, MIPtr &K1) {
   // 4 operand commutes of: min(max(Val, K0), K1)
   if (MI.getOpcode() == MMMOpc.Min)
     // Find K1 from outer instruction: min(max(...), K1) or min(K1, max(...))
if (OpcodeTriple.Med == AMDGPU::G_AMDGPU_SMED3 ||
     if (OpcodeTriple.Med == AMDGPU::G_AMDGPU_SMED3 && KO_Imm.sge(K1_Imm))
       return false;
     if (OpcodeTriple.Med == AMDGPU::G_AMDGPU_UMED3 && KO_Imm.uge(K1_Imm))
       return false;
     MatchInfo = {OpcodeTriple.Med, ValDef, K0Def, K1Def};
     return true;
   }
 
+  if (OpcodeTriple.Med == AMDGPU::G_AMDGPU_FMED3) {
+    const APFloat &KO_FPImm = K0->getOperand(1).getFPImm()->getValue();
+    const APFloat &K1_FPImm = K1->getOperand(1).getFPImm()->getValue();
+    if (KO_FPImm >= K1_FPImm)
+      return false;
+
+    const MachineFunction *MF = MI.getMF();
+    const SIMachineFunctionInfo *Info = MF->getInfo<SIMachineFunctionInfo>();
+
+    // TODO: Add G_FMINNUM_IEEE (requires some additional checks for possible
+    // SNaN input).
+    if (OpcodeTriple.Min == AMDGPU::G_FMINNUM) {
+      assert(!Info->getMode().IEEE && "G_FMINNUM was supposed to be lowered to "
+                                      "G_FMINNUM_IEEE with IEEE=true");
+
+      const SIInstrInfo *TII = MF->getSubtarget<GCNSubtarget>().getInstrInfo();
+      APInt KObits = KO_FPImm.bitcastToAPInt();
+      APInt K1bits = K1_FPImm.bitcastToAPInt();
+      if ((!MRI.hasOneNonDBGUse(K0Def) || TII->isInlineConstant(KObits)) &&
+          (!MRI.hasOneNonDBGUse(K1Def) || TII->isInlineConstant(K1bits))) {
+        MatchInfo = {OpcodeTriple.Med, ValDef, K0Def, K1Def};
+        return true;
+      }
+    }
+  }
+
   return false;
 }
 
 static void applyMinMaxToMed3(MachineInstr &MI,
                               MinMaxToMed3MatchInfo &MatchInfo) {
   MachineIRBuilder B(MI);
   B.buildInstr(MatchInfo.Opc, {MI.getOperand(0)},
                {MatchInfo.Val0, MatchInfo.Val1, MatchInfo.Val2});

llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
   case AMDGPU::G_AMDGPU_FMAX_LEGACY:
   case AMDGPU::G_AMDGPU_RCP_IFLAG:
   case AMDGPU::G_AMDGPU_CVT_F32_UBYTE0:
   case AMDGPU::G_AMDGPU_CVT_F32_UBYTE1:
   case AMDGPU::G_AMDGPU_CVT_F32_UBYTE2:
   case AMDGPU::G_AMDGPU_CVT_F32_UBYTE3:
   case AMDGPU::G_AMDGPU_SMED3:
   case AMDGPU::G_AMDGPU_UMED3:
+  case AMDGPU::G_AMDGPU_FMED3:
     return getDefaultMappingVOP(MI);
   case AMDGPU::G_UMULH:
   case AMDGPU::G_SMULH: {
     if (Subtarget.hasScalarMulHiInsts() && isSALUMapping(MI))
       return getDefaultMappingSOP(MI);
     return getDefaultMappingVOP(MI);
   }
   case AMDGPU::G_IMPLICIT_DEF: {

llvm/lib/Target/AMDGPU/SIInstructions.td

def G_AMDGPU_SMED3 : AMDGPUGenericInstruction {
   let hasSideEffects = 0;
 }
 
 def G_AMDGPU_UMED3 : AMDGPUGenericInstruction {
   let OutOperandList = (outs type0:$dst);
   let InOperandList = (ins type0:$src0, type0:$src1, type0:$src2);
   let hasSideEffects = 0;
 }
+
+def G_AMDGPU_FMED3 : AMDGPUGenericInstruction {
+  let OutOperandList = (outs type0:$dst);
+  let InOperandList = (ins type0:$src0, type0:$src1, type0:$src2);
+  let hasSideEffects = 0;
+}

llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3.ll

; GFX9-NEXT:    s_endpgm
   store volatile float %tmp0, float addrspace(1)* undef
   %tmp1 = call float @llvm.maxnum.f32(float %a, float %b)
   %tmp2 = call float @llvm.minnum.f32(float %tmp1, float %c)
   %med3 = call float @llvm.maxnum.f32(float %tmp0, float %tmp2)
   store float %med3, float addrspace(1)* %outgep
   ret void
 }
 
+define amdgpu_ps float @test_min_max_ValK0_K1_u32(float %a) {
+; GCN-LABEL: test_min_max_ValK0_K1_u32:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    v_med3_f32 v0, v0, 2.0, 4.0
+; GCN-NEXT:    ; return to shader part epilog
+  %maxnum = call float @llvm.maxnum.f32(float %a, float 2.0)
+  %fmed = call float @llvm.minnum.f32(float %maxnum, float 4.0)
+  ret float %fmed
+}
+
+define amdgpu_ps float @test_non_inline_const(float %a) {
+; GCN-LABEL: test_non_inline_const:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    v_max_f32_e32 v0, 2.0, v0
+; GCN-NEXT:    v_min_f32_e32 v0, 0x41000000, v0
+; GCN-NEXT:    ; return to shader part epilog
+  %maxnum = call float @llvm.maxnum.f32(float %a, float 2.0)
+  %fmed = call float @llvm.minnum.f32(float %maxnum, float 8.0)
+  ret float %fmed
+}
+
+define amdgpu_ps float @min_max_ValK0_K1_float(float %a) {
+; GCN-LABEL: min_max_ValK0_K1_float:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    v_med3_f32 v0, v0, 2.0, 4.0
+; GCN-NEXT:    ; return to shader part epilog
+  %maxnum = call float @llvm.maxnum.f32(float 2.0, float %a)
+  %fmed = call float @llvm.minnum.f32(float %maxnum, float 4.0)
+  ret float %fmed
+}
+
+define amdgpu_ps float @test_min_K1max_ValK0__u32(float %a) {
+; GCN-LABEL: test_min_K1max_ValK0__u32:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    v_med3_f32 v0, v0, 2.0, 4.0
+; GCN-NEXT:    ; return to shader part epilog
+  %maxnum = call float @llvm.maxnum.f32(float %a, float 2.0)
+  %fmed = call float @llvm.minnum.f32(float 4.0, float %maxnum)
+  ret float %fmed
+}
+
+define amdgpu_ps float @test_min_K1max_K0Val__u32(float %a) {
+; GCN-LABEL: test_min_K1max_K0Val__u32:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    v_med3_f32 v0, v0, 2.0, 4.0
+; GCN-NEXT:    ; return to shader part epilog
+  %maxnum = call float @llvm.maxnum.f32(float 2.0, float %a)
+  %fmed = call float @llvm.minnum.f32(float 4.0, float %maxnum)
+  ret float %fmed
+}
+
+define amdgpu_ps float @test_max_min_ValK1_K0_u32(float %a) {
+; GCN-LABEL: test_max_min_ValK1_K0_u32:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    v_med3_f32 v0, v0, 2.0, 4.0
+; GCN-NEXT:    ; return to shader part epilog
+  %minnum = call float @llvm.minnum.f32(float %a, float 4.0)
+  %fmed = call float @llvm.maxnum.f32(float %minnum, float 2.0)
+  ret float %fmed
+}
+
+define amdgpu_ps float @test_max_min_K1Val_K0_u32(float %a) {
+; GCN-LABEL: test_max_min_K1Val_K0_u32:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    v_med3_f32 v0, v0, 2.0, 4.0
+; GCN-NEXT:    ; return to shader part epilog
+  %minnum = call float @llvm.minnum.f32(float 4.0, float %a)
+  %fmed = call float @llvm.maxnum.f32(float %minnum, float 2.0)
+  ret float %fmed
+}
+
+define amdgpu_ps float @test_max_K0min_ValK1__u32(float %a) {
+; GCN-LABEL: test_max_K0min_ValK1__u32:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    v_med3_f32 v0, v0, 2.0, 4.0
+; GCN-NEXT:    ; return to shader part epilog
+  %minnum = call float @llvm.minnum.f32(float %a, float 4.0)
+  %fmed = call float @llvm.maxnum.f32(float 2.0, float %minnum)
+  ret float %fmed
+}
+
+define amdgpu_ps float @test_max_K0min_K1Val__u32(float %a) {
+; GCN-LABEL: test_max_K0min_K1Val__u32:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    v_med3_f32 v0, v0, 2.0, 4.0
+; GCN-NEXT:    ; return to shader part epilog
+  %minnum = call float @llvm.minnum.f32(float 4.0, float %a)
+  %fmed = call float @llvm.maxnum.f32(float 2.0, float %minnum)
+  ret float %fmed
+}
+
 declare i32 @llvm.amdgcn.workitem.id.x() #0
 declare float @llvm.fabs.f32(float) #0
 declare float @llvm.minnum.f32(float, float) #0
 declare float @llvm.maxnum.f32(float, float) #0
 declare double @llvm.minnum.f64(double, double) #0
 declare double @llvm.maxnum.f64(double, double) #0
 declare half @llvm.fabs.f16(half) #0
 declare half @llvm.minnum.f16(half, half) #0
 declare half @llvm.maxnum.f16(half, half) #0
 
 attributes #0 = { nounwind readnone }
 attributes #1 = { nounwind "unsafe-fp-math"="false" "no-nans-fp-math"="false" }
 attributes #2 = { nounwind "unsafe-fp-math"="false" "no-nans-fp-math"="true" }

llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-fmed3.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: test_min_max_ValK0_K1_u32
+legalized: true
+tracksRegLiveness: true
+machineFunctionInfo:
+  mode:
+    ieee: false
+body: |
+  bb.1:
+    liveins: $vgpr0
+
+    ; CHECK-LABEL: name: test_min_max_ValK0_K1_u32
+    ; CHECK: liveins: $vgpr0
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 2.000000e+00
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 4.000000e+00
+    ; CHECK: [[AMDGPU_FMED3_:%[0-9]+]]:_(s32) = G_AMDGPU_FMED3 [[COPY]], [[C]], [[C1]]
+    ; CHECK: $vgpr0 = COPY [[AMDGPU_FMED3_]](s32)
+    ; CHECK: SI_RETURN_TO_EPILOG implicit $vgpr0
+    %0:_(s32) = COPY $vgpr0
+    %3:_(s32) = G_FCONSTANT float 2.000000e+00
+    %4:_(s32) = G_FMAXNUM %0, %3
+    %5:_(s32) = G_FCONSTANT float 4.000000e+00
+    %6:_(s32) = G_FMINNUM %4, %5
+    $vgpr0 = COPY %6(s32)
+    SI_RETURN_TO_EPILOG implicit $vgpr0
+...
+
+---
+name: test_non_inline_const
+legalized: true
+tracksRegLiveness: true
+machineFunctionInfo:
+  mode:
+    ieee: false
+body: |
+  bb.1:
+    liveins: $vgpr0
+
+    ; CHECK-LABEL: name: test_non_inline_const
+    ; CHECK: liveins: $vgpr0
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 2.000000e+00
+    ; CHECK: [[FMAXNUM:%[0-9]+]]:_(s32) = G_FMAXNUM [[COPY]], [[C]]
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 8.000000e+00
+    ; CHECK: [[FMINNUM:%[0-9]+]]:_(s32) = G_FMINNUM [[FMAXNUM]], [[C1]]
+    ; CHECK: $vgpr0 = COPY [[FMINNUM]](s32)
+    ; CHECK: SI_RETURN_TO_EPILOG implicit $vgpr0
+    %0:_(s32) = COPY $vgpr0
+    %3:_(s32) = G_FCONSTANT float 2.000000e+00
+    %4:_(s32) = G_FMAXNUM %0, %3
+    %5:_(s32) = G_FCONSTANT float 8.000000e+00
+    %6:_(s32) = G_FMINNUM %4, %5
+    $vgpr0 = COPY %6(s32)
+    SI_RETURN_TO_EPILOG implicit $vgpr0
+...
+
+---
+name: min_max_ValK0_K1_float
+legalized: true
+tracksRegLiveness: true
+machineFunctionInfo:
+  mode:
+    ieee: false
+body: |
+  bb.1:
+    liveins: $vgpr0
+
+    ; CHECK-LABEL: name: min_max_ValK0_K1_float
+    ; CHECK: liveins: $vgpr0
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 2.000000e+00
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 4.000000e+00
+    ; CHECK: [[AMDGPU_FMED3_:%[0-9]+]]:_(s32) = G_AMDGPU_FMED3 [[COPY]], [[C]], [[C1]]
+    ; CHECK: $vgpr0 = COPY [[AMDGPU_FMED3_]](s32)
+    ; CHECK: SI_RETURN_TO_EPILOG implicit $vgpr0
+    %0:_(s32) = COPY $vgpr0
+    %3:_(s32) = G_FCONSTANT float 2.000000e+00
+    %4:_(s32) = G_FMAXNUM %3, %0
+    %5:_(s32) = G_FCONSTANT float 4.000000e+00
+    %6:_(s32) = G_FMINNUM %4, %5
+    $vgpr0 = COPY %6(s32)
+    SI_RETURN_TO_EPILOG implicit $vgpr0
+...
+
+---
+name:            test_min_K1max_ValK0__u32
+legalized:       true
+tracksRegLiveness: true
+machineFunctionInfo:
+  mode:
+    ieee: false
+body: |
+  bb.1:
+    liveins: $vgpr0
+
+    ; CHECK-LABEL: name: test_min_K1max_ValK0__u32
+    ; CHECK: liveins: $vgpr0
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 2.000000e+00
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 4.000000e+00
+    ; CHECK: [[AMDGPU_FMED3_:%[0-9]+]]:_(s32) = G_AMDGPU_FMED3 [[COPY]], [[C]], [[C1]]
+    ; CHECK: $vgpr0 = COPY [[AMDGPU_FMED3_]](s32)
+    ; CHECK: SI_RETURN_TO_EPILOG implicit $vgpr0
+    %0:_(s32) = COPY $vgpr0
+    %3:_(s32) = G_FCONSTANT float 2.000000e+00
+    %4:_(s32) = G_FMAXNUM %0, %3
+    %5:_(s32) = G_FCONSTANT float 4.000000e+00
+    %6:_(s32) = G_FMINNUM %5, %4
+    $vgpr0 = COPY %6(s32)
+    SI_RETURN_TO_EPILOG implicit $vgpr0
+...
+
+---
+name: test_min_K1max_K0Val__u32
+legalized: true
+tracksRegLiveness: true
+machineFunctionInfo:
+  mode:
+    ieee: false
+body: |
+  bb.1:
+    liveins: $vgpr0
+
+    ; CHECK-LABEL: name: test_min_K1max_K0Val__u32
+    ; CHECK: liveins: $vgpr0
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 2.000000e+00
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 4.000000e+00
+    ; CHECK: [[AMDGPU_FMED3_:%[0-9]+]]:_(s32) = G_AMDGPU_FMED3 [[COPY]], [[C]], [[C1]]
+    ; CHECK: $vgpr0 = COPY [[AMDGPU_FMED3_]](s32)
+    ; CHECK: SI_RETURN_TO_EPILOG implicit $vgpr0
+    %0:_(s32) = COPY $vgpr0
+    %3:_(s32) = G_FCONSTANT float 2.000000e+00
+    %4:_(s32) = G_FMAXNUM %3, %0
+    %5:_(s32) = G_FCONSTANT float 4.000000e+00
+    %6:_(s32) = G_FMINNUM %5, %4
+    $vgpr0 = COPY %6(s32)
+    SI_RETURN_TO_EPILOG implicit $vgpr0
+...
+
+---
+name: test_max_min_ValK1_K0_u32
+legalized: true
+tracksRegLiveness: true
+machineFunctionInfo:
+  mode:
+    ieee: false
+body: |
+  bb.1:
+    liveins: $vgpr0
+
+    ; CHECK-LABEL: name: test_max_min_ValK1_K0_u32
+    ; CHECK: liveins: $vgpr0
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 4.000000e+00
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 2.000000e+00
+    ; CHECK: [[AMDGPU_FMED3_:%[0-9]+]]:_(s32) = G_AMDGPU_FMED3 [[COPY]], [[C1]], [[C]]
+    ; CHECK: $vgpr0 = COPY [[AMDGPU_FMED3_]](s32)
+    ; CHECK: SI_RETURN_TO_EPILOG implicit $vgpr0
+    %0:_(s32) = COPY $vgpr0
+    %3:_(s32) = G_FCONSTANT float 4.000000e+00
+    %4:_(s32) = G_FMINNUM %0, %3
+    %5:_(s32) = G_FCONSTANT float 2.000000e+00
+    %6:_(s32) = G_FMAXNUM %4, %5
+    $vgpr0 = COPY %6(s32)
+    SI_RETURN_TO_EPILOG implicit $vgpr0
+...
+
+---
+name: test_max_min_K1Val_K0_u32
+legalized: true
+tracksRegLiveness: true
+machineFunctionInfo:
+  mode:
+    ieee: false
+body: |
+  bb.1:
+    liveins: $vgpr0
+
+    ; CHECK-LABEL: name: test_max_min_K1Val_K0_u32
+    ; CHECK: liveins: $vgpr0
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 4.000000e+00
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 2.000000e+00
+    ; CHECK: [[AMDGPU_FMED3_:%[0-9]+]]:_(s32) = G_AMDGPU_FMED3 [[COPY]], [[C1]], [[C]]
+    ; CHECK: $vgpr0 = COPY [[AMDGPU_FMED3_]](s32)
+    ; CHECK: SI_RETURN_TO_EPILOG implicit $vgpr0
+    %0:_(s32) = COPY $vgpr0
+    %3:_(s32) = G_FCONSTANT float 4.000000e+00
+    %4:_(s32) = G_FMINNUM %3, %0
+    %5:_(s32) = G_FCONSTANT float 2.000000e+00
+    %6:_(s32) = G_FMAXNUM %4, %5
+    $vgpr0 = COPY %6(s32)
+    SI_RETURN_TO_EPILOG implicit $vgpr0
+...
+
+---
+name: test_max_K0min_ValK1__u32
+legalized: true
+tracksRegLiveness: true
+machineFunctionInfo:
+  mode:
+    ieee: false
+body: |
+  bb.1:
+    liveins: $vgpr0
+
+    ; CHECK-LABEL: name: test_max_K0min_ValK1__u32
+    ; CHECK: liveins: $vgpr0
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 4.000000e+00
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 2.000000e+00
+    ; CHECK: [[AMDGPU_FMED3_:%[0-9]+]]:_(s32) = G_AMDGPU_FMED3 [[COPY]], [[C1]], [[C]]
+    ; CHECK: $vgpr0 = COPY [[AMDGPU_FMED3_]](s32)
+    ; CHECK: SI_RETURN_TO_EPILOG implicit $vgpr0
+    %0:_(s32) = COPY $vgpr0
+    %3:_(s32) = G_FCONSTANT float 4.000000e+00
+    %4:_(s32) = G_FMINNUM %0, %3
+    %5:_(s32) = G_FCONSTANT float 2.000000e+00
+    %6:_(s32) = G_FMAXNUM %5, %4
+    $vgpr0 = COPY %6(s32)
+    SI_RETURN_TO_EPILOG implicit $vgpr0
+...
+
+---
+name: test_max_K0min_K1Val__u32
+legalized: true
+tracksRegLiveness: true
+machineFunctionInfo:
+  mode:
+    ieee: false
+body: |
+  bb.1:
+    liveins: $vgpr0
+
+    ; CHECK-LABEL: name: test_max_K0min_K1Val__u32
+    ; CHECK: liveins: $vgpr0
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 4.000000e+00
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 2.000000e+00
+    ; CHECK: [[AMDGPU_FMED3_:%[0-9]+]]:_(s32) = G_AMDGPU_FMED3 [[COPY]], [[C1]], [[C]]
+    ; CHECK: $vgpr0 = COPY [[AMDGPU_FMED3_]](s32)
+    ; CHECK: SI_RETURN_TO_EPILOG implicit $vgpr0
+    %0:_(s32) = COPY $vgpr0
+    %3:_(s32) = G_FCONSTANT float 4.000000e+00
+    %4:_(s32) = G_FMINNUM %3, %0
+    %5:_(s32) = G_FCONSTANT float 2.000000e+00
+    %6:_(s32) = G_FMAXNUM %5, %4
+    $vgpr0 = COPY %6(s32)
+    SI_RETURN_TO_EPILOG implicit $vgpr0
+...