AMDGPU/GlobalISel: Add integer med3 combines

[Petar.Avramovic]

Summary

Add signed and unsigned integer version of med3 combine.
Source pattern is min(max(Val, K0), K1) or max(min(Val, K1), K0)
where K0 and K1 are constants and K0 <= K1. Destination is med3
that corresponds to signedness of min/max in source.

[arsenm]

llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp

39–67

This feels like reinventing MIPatternMatch

83

Opcode checks first?

94

Technically 0 is a valid instruction opcode (PHI) but we ignore that most places

107

Braces

151–152

This will fail if the constant is a bitcasted G_FCONSTANT when the other patch extends isConst

166

Should not construct new MachineIRBuilder

[foad]

llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp

132–133

This should never fail.

141

I think it only has to be K0 <= K1.

[Petar.Avramovic]

Use MIPatternMatch to match source pattern. Use Optional instead of return 0. Separate from fp med3 function to avoid bitcasted G_FCONSTANT and explicitly match G_CONSTANT.

[foad]

Looks pretty good to me, just some questions inline.

Will we end up selecting v_med3 instructions even for uniform inputs? That would be bad.

llvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h

177

Why is the cast needed?

280

Might be simpler to make this a subclass of AnyBinaryOp_match?

llvm/lib/CodeGen/GlobalISel/Utils.cpp

349

Swap the operands: MI->getOpcode() != TargetOpcode::G_CONSTANT

llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp

267

I don't understand why you need to use Optional here. The default case could just be marked as unreachable.

281

Is this a template so that you can use it for floating point values in the future? Then shouldn't "CstRegMatch" be called "ICstRegMatch"?

310–313

I would remove these asserts.

[Petar.Avramovic]

Address review comments.

[Petar.Avramovic]

Should we move this combine after register bank select and skip min/max with sgpr bank?

llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp

281

Yes, fmed3 will match fconstant, and clamp fconstant or splat value

[foad]

In D90050#2405810, @Petar.Avramovic wrote:

Should we move this combine after register bank select and skip min/max with sgpr bank?

I'm not sure. @arsenm is that the usual way to handle this?

[arsenm]

In D90050#2405812, @foad wrote:

In D90050#2405810, @Petar.Avramovic wrote:

Should we move this combine after register bank select and skip min/max with sgpr bank?

I'm not sure. @arsenm is that the usual way to handle this?

This should probably be done after RegBankSelect, although post-regbankselect combines are a yet unsolved problem. The dummy pass is there for it, it just doesn't do anything yet

[Petar.Avramovic]

Move combines after register bank select. Check for register bank of the result register and only combine for vgpr bank. There is mir test for sgpr bank min/max input for completeness. However sgpr bank min/max are transformed to compare + select in regbankselect and we should not expect them in post regbank combiner.

[foad]

In D90050#2407767, @Petar.Avramovic wrote:

However sgpr bank min/max are transformed to compare + select in regbankselect

That seems wrong since we have S_MIN/MAX_I32/U32 instructions.

[arsenm]

In D90050#2407790, @foad wrote:

In D90050#2407767, @Petar.Avramovic wrote:

However sgpr bank min/max are transformed to compare + select in regbankselect

That seems wrong since we have S_MIN/MAX_I32/U32 instructions.

I thought I fixed this before

[arsenm]

The scalar min/max issue has been fixed, so this needs updating

[foad]

llvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h

266

Nit: drop the parens around (R.match(MRI, Op0) && L.match(MRI, Op1)).

llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp

115 ↗

(On Diff #306646)

Can we just assert the type is one of these, since we're running on legalized GMIR and these are the only types that we have integer min/max instructions for? (Or do we need to exclude v2s16?)

124 ↗

(On Diff #306646)

Nit: make this "K0_Imm" not "KO_Imm".

[Petar.Avramovic]

Rebased. Updated uniform test (Jay fixed reg-bank-select for uniform min and max) and added test for v2i16 which we don't combine.
Renamed G_AMDGPU_MED3 to G_AMDGPU_SMED3 since this patch also adds UMED3.

[arsenm]

llvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h

27–29

I'd rather just have to pass MRI consistently

251–262

Probably should split the new MIPatternMtach changes into a separate patch

[Petar.Avramovic]

Extracted MIPatternMtach changes.

[Petar.Avramovic]

Rebase and ping.

[foad]

Looks pretty good, just minor comments inline.

llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp

115 ↗

(On Diff #306646)

Ping? Maybe just if (Ty.isVector()) return false;?

97 ↗

(On Diff #340463)

I don't think you really need the form of m_CommutativeBinOp that does not check the opcode. This whole function could be written as:

return mi_match(MI, MRI, m_any_of(m_CommutativeBinOp(Max, m_CommutativeBinOp(Min, Val, K1), K0)),
                                  m_CommutativeBinOp(Min, m_CommutativeBinOp(Max, Val, K0), K1)));

[Petar.Avramovic]

Addressed review comments.

llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp

115 ↗

(On Diff #306646)

We need to exclude v2s16, there is a test that we don't combine in this case.
I did find it more informative this way since it is explicit about available types for med3.

[foad]

llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp

115 ↗

(On Diff #306646)

Fair enough.

llvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h

 namespace llvm {
 namespace MIPatternMatch {
 
 template <typename Reg, typename Pattern>
 bool mi_match(Reg R, const MachineRegisterInfo &MRI, Pattern &&P) {
   return P.match(MRI, R);
 }
 
+template <typename Pattern>
+bool mi_match(MachineInstr* MI, Pattern &&P) {
+  return P.match(MI->getMF()->getRegInfo(), MI);
+}
+
 // TODO: Extend for N use.
 template <typename SubPatternT> struct OneUse_match {
   SubPatternT SubPat;
   OneUse_match(const SubPatternT &SP) : SubPat(SP) {}
 
   bool match(const MachineRegisterInfo &MRI, Register Reg) {
     return MRI.hasOneUse(Reg) && SubPat.match(MRI, Reg);
   }

 ///{
 /// Convenience matchers for specific integer values.
 inline SpecificConstantMatch m_ZeroInt() { return SpecificConstantMatch(0); }
 inline SpecificConstantMatch m_AllOnesInt() {
   return SpecificConstantMatch(-1);
 }
 ///}
 
+struct ICstRegMatch {
+  Register &CR;
+  ICstRegMatch(Register &C) : CR(C) {}
+  bool match(const MachineRegisterInfo &MRI, Register Reg) {
+    if (auto MaybeCst = getConstantVRegValWithLookThrough(
+            Reg, MRI, /*LookThroughInstrs*/ true,
+            /*HandleFConstants*/ false)) {
+      CR = MaybeCst->VReg;
+      return true;
+    }
+    return false;
+  }
+};
+
+inline ICstRegMatch m_ICst(Register &Reg) { return ICstRegMatch(Reg); }
+
 // TODO: Rework this for different kinds of MachineOperand.
 // Currently assumes the Src for a match is a register.
 // We might want to support taking in some MachineOperands and call getReg on
 // that.
 
 struct operand_type_match {
   bool match(const MachineRegisterInfo &MRI, Register Reg) { return true; }
   bool match(const MachineRegisterInfo &MRI, MachineOperand *MO) {

 template <> struct bind_helper<MachineInstr *> {
   static bool bind(const MachineRegisterInfo &MRI, MachineInstr *&MI,
                    Register Reg) {
     MI = MRI.getVRegDef(Reg);
     if (MI)
       return true;
     return false;
   }
+  static bool bind(const MachineRegisterInfo &MRI, MachineInstr *&MI,
+                   MachineInstr *Inst) {
+    MI = Inst;
+    if (MI)
+      return true;
+    return false;
+  }
 };
 
 template <> struct bind_helper<LLT> {
   static bool bind(const MachineRegisterInfo &MRI, LLT Ty, Register Reg) {
     Ty = MRI.getType(Reg);
     if (Ty.isValid())
       return true;
     return false;
if (mi_match(Op, MRI, m_MInstr(TmpMI))) {
                (Commutable && (R.match(MRI, TmpMI->getOperand(1).getReg()) &&
                                L.match(MRI, TmpMI->getOperand(2).getReg())));
       }
     }
     return false;
   }
 };
 
+// Helper for (commutable) binary generic MI. Doesn't check opcode.
+template <typename LHS_P, typename RHS_P, bool Commutable = false>
+struct AnyBinaryOp_match {
+  LHS_P L;
+  RHS_P R;
+
+  AnyBinaryOp_match(const LHS_P &LHS, const RHS_P &RHS) : L(LHS), R(RHS) {}
+  template <typename OpTy>
+  bool match(const MachineRegisterInfo &MRI, OpTy &&Op) {
+    MachineInstr *TmpMI;
+    if (mi_match(Op, MRI, m_MInstr(TmpMI))) {
+      if (TmpMI->getNumOperands() == 3) {
+        return matchOperands(MRI, TmpMI->getOperand(1).getReg(),
+                             TmpMI->getOperand(2).getReg());
+      }
+    }
+    return false;
+  }
+  bool matchOperands(const MachineRegisterInfo &MRI, Register Op0,
+                     Register Op1) {
+    return (L.match(MRI, Op0) && R.match(MRI, Op1)) ||
+           (Commutable && (R.match(MRI, Op0) && L.match(MRI, Op1)));
+  }
+};
+
+template <typename LHS, typename RHS>
+inline AnyBinaryOp_match<LHS, RHS, false> m_BinOp(const LHS &L, const RHS &R) {
+  return AnyBinaryOp_match<LHS, RHS, false>(L, R);
+}
+
+template <typename LHS, typename RHS>
+inline AnyBinaryOp_match<LHS, RHS, true> m_CommutableBinOp(const LHS &L,
+                                                           const RHS &R) {
+  return AnyBinaryOp_match<LHS, RHS, true>(L, R);
+}
+
+// Helper for (commutable) binary generic MI that checks Opcode.
+template <typename LHS_P, typename RHS_P, bool Commutable = false>
+struct BinaryOpWithOpcode_match : AnyBinaryOp_match<LHS_P, RHS_P, Commutable> {
+  unsigned Opcode;
+
+  BinaryOpWithOpcode_match(unsigned Opcode, const LHS_P &LHS, const RHS_P &RHS)
+      : AnyBinaryOp_match<LHS_P, RHS_P, Commutable>(LHS, RHS), Opcode(Opcode) {}
+  template <typename OpTy>
+  bool match(const MachineRegisterInfo &MRI, OpTy &&Op) {
+    MachineInstr *TmpMI;
+    if (mi_match(Op, MRI, m_MInstr(TmpMI))) {
+      if (TmpMI->getOpcode() == Opcode && TmpMI->getNumOperands() == 3) {
+        return this->matchOperands(MRI, TmpMI->getOperand(1).getReg(),
+                                   TmpMI->getOperand(2).getReg());
+      }
+    }
+    return false;
+  }
+};
+
+template <typename LHS, typename RHS>
+inline BinaryOpWithOpcode_match<LHS, RHS, false>
+m_BinOp(unsigned Opcode, const LHS &L, const RHS &R) {
+  return BinaryOpWithOpcode_match<LHS, RHS, false>(Opcode, L, R);
+}
+
+template <typename LHS, typename RHS>
+inline BinaryOpWithOpcode_match<LHS, RHS, true>
+m_CommutableBinOp(unsigned Opcode, const LHS &L, const RHS &R) {
+  return BinaryOpWithOpcode_match<LHS, RHS, true>(Opcode, L, R);
+}
+
 template <typename LHS, typename RHS>
 inline BinaryOp_match<LHS, RHS, TargetOpcode::G_ADD, true>
 m_GAdd(const LHS &L, const RHS &R) {
   return BinaryOp_match<LHS, RHS, TargetOpcode::G_ADD, true>(L, R);
 }
 
 template <typename LHS, typename RHS>
 inline BinaryOp_match<LHS, RHS, TargetOpcode::G_SUB> m_GSub(const LHS &L,

llvm/include/llvm/CodeGen/GlobalISel/Utils.h

 class MachineRegisterInfo;
 class MCInstrDesc;
 class RegisterBankInfo;
 class TargetInstrInfo;
 class TargetLowering;
 class TargetPassConfig;
 class TargetRegisterInfo;
 class TargetRegisterClass;
+class ConstantInt;
 class ConstantFP;
 class APFloat;
 
 /// Try to constrain Reg to the specified register class. If this fails,
 /// create a new virtual register in the correct class.
 ///
 /// \return The virtual register constrained to the right register class.
 Register constrainRegToClass(MachineRegisterInfo &MRI,

 /// virtual register defined by this G_F/CONSTANT.
 /// When \p LookThroughInstrs == false this function behaves like
 /// getConstantVRegVal.
 /// When \p HandleFConstants == false the function bails on G_FCONSTANTs.
 Optional<ValueAndVReg>
 getConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI,
                                   bool LookThroughInstrs = true,
                                   bool HandleFConstants = true);
+const ConstantInt *getConstantIntVRegVal(Register VReg,
+                                         const MachineRegisterInfo &MRI);
 const ConstantFP* getConstantFPVRegVal(Register VReg,
                                        const MachineRegisterInfo &MRI);
 
 /// See if Reg is defined by an single def instruction that is
 /// Opcode. Also try to do trivial folding if it's a COPY with
 /// same types. Returns null otherwise.
 MachineInstr *getOpcodeDef(unsigned Opcode, Register Reg,
                            const MachineRegisterInfo &MRI);

llvm/lib/CodeGen/GlobalISel/Utils.cpp

Optional<ValueAndVReg> llvm::getConstantVRegValWithLookThrough(
   }
 
   if (Val.getBitWidth() > 64)
     return None;
 
   return ValueAndVReg{Val.getSExtValue(), VReg};
 }
 
+const ConstantInt *
+llvm::getConstantIntVRegVal(Register VReg, const MachineRegisterInfo &MRI) {
+  MachineInstr *MI = MRI.getVRegDef(VReg);
+  if (MI->getOpcode() != TargetOpcode::G_CONSTANT)
+    return nullptr;
+  return MI->getOperand(1).getCImm();
+}
+
 const ConstantFP *
 llvm::getConstantFPVRegVal(Register VReg, const MachineRegisterInfo &MRI) {
   MachineInstr *MI = MRI.getVRegDef(VReg);
   if (TargetOpcode::G_FCONSTANT != MI->getOpcode())
     return nullptr;
   return MI->getOperand(1).getFPImm();
 }
 

llvm/lib/Target/AMDGPU/AMDGPUCombine.td

def cvt_f32_ubyteN : GICombineRule<
   (defs root:$cvt_f32_ubyteN, cvt_f32_ubyteN_matchdata:$matchinfo),
   (match (wip_match_opcode G_AMDGPU_CVT_F32_UBYTE0,
                            G_AMDGPU_CVT_F32_UBYTE1,
                            G_AMDGPU_CVT_F32_UBYTE2,
                            G_AMDGPU_CVT_F32_UBYTE3):$cvt_f32_ubyteN,
          [{ return PostLegalizerHelper.matchCvtF32UByteN(*${cvt_f32_ubyteN}, ${matchinfo}); }]),
   (apply [{ PostLegalizerHelper.applyCvtF32UByteN(*${cvt_f32_ubyteN}, ${matchinfo}); }])>;
 
+def med3_matchdata : GIDefMatchData<"AMDGPUPostLegalizerCombinerHelper::Med3MatchInfo">;
+
+def int_minmax_to_med3 : GICombineRule<
+  (defs root:$min_or_max, med3_matchdata:$matchinfo),
+  (match (wip_match_opcode G_SMAX,
+                           G_SMIN,
+                           G_UMAX,
+                           G_UMIN):$min_or_max,
+         [{ return PostLegalizerHelper.matchIntMinMaxToMed3(*${min_or_max}, ${matchinfo}); }]),
+  (apply [{ PostLegalizerHelper.applyMed3(*${min_or_max}, ${matchinfo}); }])>;
+
+
 // Combines which should only apply on SI/VI
 def gfx6gfx7_combines : GICombineGroup<[fcmp_select_to_fmin_fmax_legacy]>;
 
 
 def AMDGPUPreLegalizerCombinerHelper: GICombinerHelper<
   "AMDGPUGenPreLegalizerCombinerHelper", [all_combines]> {
   let DisableRuleOption = "amdgpuprelegalizercombiner-disable-rule";
 }
 
 def AMDGPUPostLegalizerCombinerHelper: GICombinerHelper<
   "AMDGPUGenPostLegalizerCombinerHelper",
   [all_combines, gfx6gfx7_combines,
-   uchar_to_float, cvt_f32_ubyteN]> {
+   uchar_to_float, cvt_f32_ubyteN,
+   int_minmax_to_med3]> {
   let DisableRuleOption = "amdgpupostlegalizercombiner-disable-rule";
   let StateClass = "AMDGPUPostLegalizerCombinerHelperState";
   let AdditionalArguments = [];
 }
 
 def AMDGPURegBankCombinerHelper : GICombinerHelper<
   "AMDGPUGenRegBankCombinerHelper", []> {
   let DisableRuleOption = "amdgpuregbankcombiner-disable-rule";
 }

llvm/lib/Target/AMDGPU/AMDGPUGISel.td

 def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_AND, SIbuffer_atomic_and>;
 def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_OR, SIbuffer_atomic_or>;
 def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_XOR, SIbuffer_atomic_xor>;
 def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_INC, SIbuffer_atomic_inc>;
 def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_DEC, SIbuffer_atomic_dec>;
 def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_FADD, SIbuffer_atomic_fadd>;
 def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_CMPSWAP, SIbuffer_atomic_cmpswap>;
 def : GINodeEquiv<G_AMDGPU_S_BUFFER_LOAD, SIsbuffer_load>;
+def : GINodeEquiv<G_AMDGPU_SMED3, AMDGPUsmed3>;
+def : GINodeEquiv<G_AMDGPU_UMED3, AMDGPUumed3>;
 
 class GISelSop2Pat <
   SDPatternOperator node,
   Instruction inst,
   ValueType dst_vt,
   ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt>   : GCNPat <
 
   (dst_vt (node (src0_vt SReg_32:$src0), (src1_vt SReg_32:$src1))),

llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp

 
 class AMDGPUPostLegalizerCombinerHelper {
 protected:
   MachineIRBuilder &B;
   MachineFunction &MF;
   MachineRegisterInfo &MRI;
   CombinerHelper &Helper;
 
 public:
   AMDGPUPostLegalizerCombinerHelper(MachineIRBuilder &B, CombinerHelper &Helper)
       : B(B), MF(B.getMF()), MRI(*B.getMRI()), Helper(Helper){};
 
   struct FMinFMaxLegacyInfo {
     Register LHS;
     Register RHS;
     Register True;
     Register False;
     CmpInst::Predicate Pred;
   };
 
   // TODO: Make sure fmin_legacy/fmax_legacy don't canonicalize
   bool matchFMinFMaxLegacy(MachineInstr &MI, FMinFMaxLegacyInfo &Info);
   void applySelectFCmpToFMinToFMaxLegacy(MachineInstr &MI,
                                          const FMinFMaxLegacyInfo &Info);
 
   bool matchUCharToFloat(MachineInstr &MI);
   void applyUCharToFloat(MachineInstr &MI);
 
   // FIXME: Should be able to have 2 separate matchdatas rather than custom
   // struct boilerplate.
   struct CvtF32UByteMatchInfo {
     Register CvtVal;
     unsigned ShiftOffset;
   };
 
   bool matchCvtF32UByteN(MachineInstr &MI, CvtF32UByteMatchInfo &MatchInfo);
   void applyCvtF32UByteN(MachineInstr &MI,
                          const CvtF32UByteMatchInfo &MatchInfo);
+
+  struct MinMaxMedOpc {
+    unsigned Min, Max, Med;
+  };
+
+  struct Med3MatchInfo {
+    unsigned Opc;
+    Register Val0, Val1, Val2;
+  };
+
+  MinMaxMedOpc getMinMaxPair(unsigned Opc);
+
+  template <class m_Cst>
+  bool matchMed(MachineInstr &MI, MachineRegisterInfo &MRI, MinMaxMedOpc MMMOpc,
+                Register &Val, Register &K0, Register &K1);
+
+  bool matchIntMinMaxToMed3(MachineInstr &MI, Med3MatchInfo &MatchInfo);
+  void applyMed3(MachineInstr &MI, Med3MatchInfo &MatchInfo);
+
 };
 
 bool AMDGPUPostLegalizerCombinerHelper::matchFMinFMaxLegacy(
     MachineInstr &MI, FMinFMaxLegacyInfo &Info) {
   // FIXME: Combines should have subtarget predicates, and we shouldn't need
   // this here.
   if (!MF.getSubtarget<GCNSubtarget>().hasFminFmaxLegacy())
     return false;
 
   // FIXME: Type predicate on pattern
   if (MRI.getType(MI.getOperand(0).getReg()) != LLT::scalar(32))
     return false;
 
   Register Cond = MI.getOperand(1).getReg();
   if (!MRI.hasOneNonDBGUse(Cond) ||
       !mi_match(Cond, MRI,
                 m_GFCmp(m_Pred(Info.Pred), m_Reg(Info.LHS), m_Reg(Info.RHS))))
     return false;
 
   Info.True = MI.getOperand(2).getReg();
   Info.False = MI.getOperand(3).getReg();
 
   if (!(Info.LHS == Info.True && Info.RHS == Info.False) &&
       !(Info.LHS == Info.False && Info.RHS == Info.True))
     return false;
 
   switch (Info.Pred) {
   case CmpInst::FCMP_FALSE:
   case CmpInst::FCMP_OEQ:
   case CmpInst::FCMP_ONE:
   case CmpInst::FCMP_ORD:
   case CmpInst::FCMP_UNO:
   case CmpInst::FCMP_UEQ:
   case CmpInst::FCMP_UNE:
   case CmpInst::FCMP_TRUE:
     return false;
   default:
     return true;
   }
 }
 
 void AMDGPUPostLegalizerCombinerHelper::applySelectFCmpToFMinToFMaxLegacy(
     MachineInstr &MI, const FMinFMaxLegacyInfo &Info) {
   B.setInstrAndDebugLoc(MI);
   auto buildNewInst = [&MI, this](unsigned Opc, Register X, Register Y) {
     B.buildInstr(Opc, {MI.getOperand(0)}, {X, Y}, MI.getFlags());
   };
 
   switch (Info.Pred) {
   case CmpInst::FCMP_ULT:
   case CmpInst::FCMP_ULE:
     if (Info.LHS == Info.True)
       buildNewInst(AMDGPU::G_AMDGPU_FMIN_LEGACY, Info.RHS, Info.LHS);
     else
       buildNewInst(AMDGPU::G_AMDGPU_FMAX_LEGACY, Info.LHS, Info.RHS);
     break;
   case CmpInst::FCMP_OLE:
   case CmpInst::FCMP_OLT: {
     // We need to permute the operands to get the correct NaN behavior. The
     // selected operand is the second one based on the failing compare with NaN,
     // so permute it based on the compare type the hardware uses.
     if (Info.LHS == Info.True)
       buildNewInst(AMDGPU::G_AMDGPU_FMIN_LEGACY, Info.LHS, Info.RHS);
     else
       buildNewInst(AMDGPU::G_AMDGPU_FMAX_LEGACY, Info.RHS, Info.LHS);
     break;
   }
   case CmpInst::FCMP_UGE:
   case CmpInst::FCMP_UGT: {
     if (Info.LHS == Info.True)
       buildNewInst(AMDGPU::G_AMDGPU_FMAX_LEGACY, Info.RHS, Info.LHS);
     else
       buildNewInst(AMDGPU::G_AMDGPU_FMIN_LEGACY, Info.LHS, Info.RHS);
     break;
   }
   case CmpInst::FCMP_OGT:
   case CmpInst::FCMP_OGE: {
     if (Info.LHS == Info.True)
       buildNewInst(AMDGPU::G_AMDGPU_FMAX_LEGACY, Info.LHS, Info.RHS);
     else
       buildNewInst(AMDGPU::G_AMDGPU_FMIN_LEGACY, Info.RHS, Info.LHS);
     break;
   }
   default:
     llvm_unreachable("predicate should not have matched");
   }
 
if (SrcTy != S32) {
     CvtSrc = B.buildAnyExt(S32, CvtSrc).getReg(0);
   }
 
   assert(MI.getOpcode() != NewOpc);
   B.buildInstr(NewOpc, {MI.getOperand(0)}, {CvtSrc}, MI.getFlags());
   MI.eraseFromParent();
 }
 
+AMDGPUPostLegalizerCombinerHelper::MinMaxMedOpc
+AMDGPUPostLegalizerCombinerHelper::getMinMaxPair(unsigned Opc) {
+  switch (Opc) {
+  default:
+    llvm_unreachable("Unsupported opcode");
+  case AMDGPU::G_SMAX:
+  case AMDGPU::G_SMIN:
+    return {AMDGPU::G_SMIN, AMDGPU::G_SMAX, AMDGPU::G_AMDGPU_SMED3};
+  case AMDGPU::G_UMAX:
+  case AMDGPU::G_UMIN:
+    return {AMDGPU::G_UMIN, AMDGPU::G_UMAX, AMDGPU::G_AMDGPU_UMED3};
+  }
+}
+
+template <class m_Cst>
+bool AMDGPUPostLegalizerCombinerHelper::matchMed(MachineInstr &MI,
+                                                 MachineRegisterInfo &MRI,
+                                                 MinMaxMedOpc MMMOpc,
+                                                 Register &Val, Register &K0,
+                                                 Register &K1) {
+  // 4 operand commutes of: min(max(Val, K0), K1). Find K1 from outer instr:
+  // min(max(...), K1) or min(K1, max(...)). Find K0 and Val from inner instr:
+  // max(K0, Val) or max(Val, K0).
+  if (MI.getOpcode() == MMMOpc.Min)
+    return mi_match(
+        &MI,
+        m_CommutableBinOp(m_CommutableBinOp(MMMOpc.Max, m_Reg(Val), m_Cst(K0)),
+                          m_Cst(K1)));
+  // 4 operand commutes of: max(min(Val, K1), K0). Find K0 from outer instr:
+  // max(min(...), K0) or max(K0, min(...)). Find K1 and Val from inner instr:
+  // min(K1, Val) or min(Val, K1).
+  return mi_match(&MI, m_CommutableBinOp(
+                           m_CommutableBinOp(MMMOpc.Min, m_Reg(Val), m_Cst(K1)),
+                           m_Cst(K0)));
+}
+
+bool AMDGPUPostLegalizerCombinerHelper::matchIntMinMaxToMed3(
+    MachineInstr &MI, Med3MatchInfo &MatchInfo) {
+  LLT Ty = MRI.getType(MI.getOperand(0).getReg());
+  if (Ty != LLT::scalar(16) && Ty != LLT::scalar(32))
+    return false;
+
+  MinMaxMedOpc OpcodeTriple = getMinMaxPair(MI.getOpcode());
+  Register Val, K0, K1;
+  // Match min(max(Val, K0), K1) or max(min(Val, K1), K0). Then see if K0 <= K1.
+  if (!matchMed<ICstRegMatch>(MI, MRI, OpcodeTriple, Val, K0, K1))
+    return false;
+
+  const APInt &KO_Imm = getConstantIntVRegVal(K0, MRI)->getValue();
+  const APInt &K1_Imm = getConstantIntVRegVal(K1, MRI)->getValue();
+  if (OpcodeTriple.Med == AMDGPU::G_AMDGPU_SMED3 && KO_Imm.sgt(K1_Imm))
+    return false;
+  if (OpcodeTriple.Med == AMDGPU::G_AMDGPU_UMED3 && KO_Imm.ugt(K1_Imm))
+    return false;
+
+  MatchInfo = {OpcodeTriple.Med, Val, K0, K1};
+  return true;
+}
+
+void AMDGPUPostLegalizerCombinerHelper::applyMed3(MachineInstr &MI,
+                                                  Med3MatchInfo &MatchInfo) {
+  B.setInstrAndDebugLoc(MI);
+  B.buildInstr(MatchInfo.Opc, {MI.getOperand(0)},
+               {MatchInfo.Val0, MatchInfo.Val1, MatchInfo.Val2}, MI.getFlags());
+  MI.eraseFromParent();
+}
+
 class AMDGPUPostLegalizerCombinerHelperState {
 protected:
   CombinerHelper &Helper;
   AMDGPUPostLegalizerCombinerHelper &PostLegalizerHelper;
 
 public:
   AMDGPUPostLegalizerCombinerHelperState(
       CombinerHelper &Helper,

llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
   case AMDGPU::G_AMDGPU_FFBH_U32:
   case AMDGPU::G_AMDGPU_FMIN_LEGACY:
   case AMDGPU::G_AMDGPU_FMAX_LEGACY:
   case AMDGPU::G_AMDGPU_RCP_IFLAG:
   case AMDGPU::G_AMDGPU_CVT_F32_UBYTE0:
   case AMDGPU::G_AMDGPU_CVT_F32_UBYTE1:
   case AMDGPU::G_AMDGPU_CVT_F32_UBYTE2:
   case AMDGPU::G_AMDGPU_CVT_F32_UBYTE3:
+  case AMDGPU::G_AMDGPU_SMED3:
+  case AMDGPU::G_AMDGPU_UMED3:
     return getDefaultMappingVOP(MI);
   case AMDGPU::G_UMULH:
   case AMDGPU::G_SMULH: {
     if (Subtarget.hasScalarMulHiInsts() && isSALUMapping(MI))
       return getDefaultMappingSOP(MI);
     return getDefaultMappingVOP(MI);
   }
   case AMDGPU::G_IMPLICIT_DEF: {

llvm/lib/Target/AMDGPU/SIInstructions.td

 
 def G_AMDGPU_INTRIN_BVH_INTERSECT_RAY : AMDGPUGenericInstruction {
   let OutOperandList = (outs type0:$dst);
   let InOperandList = (ins unknown:$intrin, variable_ops);
   let hasSideEffects = 0;
   let mayLoad = 1;
   let mayStore = 0;
 }
+
+def G_AMDGPU_SMED3 : AMDGPUGenericInstruction {
+  let OutOperandList = (outs type0:$dst);
+  let InOperandList = (ins type0:$src0, type0:$src1, type0:$src2);
+  let hasSideEffects = 0;
+}
+
+def G_AMDGPU_UMED3 : AMDGPUGenericInstruction {
+  let OutOperandList = (outs type0:$dst);
+  let InOperandList = (ins type0:$src0, type0:$src1, type0:$src2);
+  let hasSideEffects = 0;
+}

llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-smed3.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: test_min_max_ValK0_K1_i32
+legalized: true
+tracksRegLiveness: true
+body: |
+  bb.1:
+    liveins: $vgpr0, $sgpr30_sgpr31
+
+    ; CHECK-LABEL: name: test_min_max_ValK0_K1_i32
+    ; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -12
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 17
+    ; CHECK: [[AMDGPU_SMED3_:%[0-9]+]]:_(s32) = G_AMDGPU_SMED3 [[COPY]], [[C]], [[C1]]
+    ; CHECK: $vgpr0 = COPY [[AMDGPU_SMED3_]](s32)
+    ; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
+    ; CHECK: S_SETPC_B64_return [[COPY2]], implicit $vgpr0
+    %0:_(s32) = COPY $vgpr0
+    %1:sgpr_64 = COPY $sgpr30_sgpr31
+    %2:_(s32) = G_CONSTANT i32 -12
+    %3:_(s32) = G_SMAX %0, %2
+    %4:_(s32) = G_CONSTANT i32 17
+    %5:_(s32) = G_SMIN %3, %4
+    $vgpr0 = COPY %5(s32)
+    %6:ccr_sgpr_64 = COPY %1
+    S_SETPC_B64_return %6, implicit $vgpr0
+...
+
+---
+name: min_max_ValK0_K1_i32
+legalized: true
+tracksRegLiveness: true
+body: |
+  bb.1:
+    liveins: $vgpr0, $sgpr30_sgpr31
+
+    ; CHECK-LABEL: name: min_max_ValK0_K1_i32
+    ; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -12
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 17
+    ; CHECK: [[AMDGPU_SMED3_:%[0-9]+]]:_(s32) = G_AMDGPU_SMED3 [[COPY]], [[C]], [[C1]]
+    ; CHECK: $vgpr0 = COPY [[AMDGPU_SMED3_]](s32)
+    ; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
+    ; CHECK: S_SETPC_B64_return [[COPY2]], implicit $vgpr0
+    %0:_(s32) = COPY $vgpr0
+    %1:sgpr_64 = COPY $sgpr30_sgpr31
+    %2:_(s32) = G_CONSTANT i32 -12
+    %3:_(s32) = G_SMAX %2, %0
+    %4:_(s32) = G_CONSTANT i32 17
+    %5:_(s32) = G_SMIN %3, %4
+    $vgpr0 = COPY %5(s32)
+    %6:ccr_sgpr_64 = COPY %1
+    S_SETPC_B64_return %6, implicit $vgpr0
+...
+
+---
+name: test_min_K1max_ValK0__i32
+legalized: true
+tracksRegLiveness: true
+body: |
+  bb.1:
+    liveins: $vgpr0, $sgpr30_sgpr31
+
+    ; CHECK-LABEL: name: test_min_K1max_ValK0__i32
+    ; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -12
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 17
+    ; CHECK: [[AMDGPU_SMED3_:%[0-9]+]]:_(s32) = G_AMDGPU_SMED3 [[COPY]], [[C]], [[C1]]
+    ; CHECK: $vgpr0 = COPY [[AMDGPU_SMED3_]](s32)
+    ; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
+    ; CHECK: S_SETPC_B64_return [[COPY2]], implicit $vgpr0
+    %0:_(s32) = COPY $vgpr0
+    %1:sgpr_64 = COPY $sgpr30_sgpr31
+    %2:_(s32) = G_CONSTANT i32 -12
+    %3:_(s32) = G_SMAX %0, %2
+    %4:_(s32) = G_CONSTANT i32 17
+    %5:_(s32) = G_SMIN %4, %3
+    $vgpr0 = COPY %5(s32)
+    %6:ccr_sgpr_64 = COPY %1
+    S_SETPC_B64_return %6, implicit $vgpr0
+...
+
+---
+name: test_min_K1max_K0Val__i32
+legalized: true
+tracksRegLiveness: true
+body: |
+  bb.1:
+    liveins: $vgpr0, $sgpr30_sgpr31
+
+    ; CHECK-LABEL: name: test_min_K1max_K0Val__i32
+    ; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -12
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 17
+    ; CHECK: [[AMDGPU_SMED3_:%[0-9]+]]:_(s32) = G_AMDGPU_SMED3 [[COPY]], [[C]], [[C1]]
+    ; CHECK: $vgpr0 = COPY [[AMDGPU_SMED3_]](s32)
+    ; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
+    ; CHECK: S_SETPC_B64_return [[COPY2]], implicit $vgpr0
+    %0:_(s32) = COPY $vgpr0
+    %1:sgpr_64 = COPY $sgpr30_sgpr31
+    %2:_(s32) = G_CONSTANT i32 -12
+    %3:_(s32) = G_SMAX %2, %0
+    %4:_(s32) = G_CONSTANT i32 17
+    %5:_(s32) = G_SMIN %4, %3
+    $vgpr0 = COPY %5(s32)
+    %6:ccr_sgpr_64 = COPY %1
+    S_SETPC_B64_return %6, implicit $vgpr0
+...
+
+---
+name: test_max_min_ValK1_K0_i32
+legalized: true
+tracksRegLiveness: true
+body: |
+  bb.1:
+    liveins: $vgpr0, $sgpr30_sgpr31
+
+    ; CHECK-LABEL: name: test_max_min_ValK1_K0_i32
+    ; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 17
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -12
+    ; CHECK: [[AMDGPU_SMED3_:%[0-9]+]]:_(s32) = G_AMDGPU_SMED3 [[COPY]], [[C1]], [[C]]
+    ; CHECK: $vgpr0 = COPY [[AMDGPU_SMED3_]](s32)
+    ; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
+    ; CHECK: S_SETPC_B64_return [[COPY2]], implicit $vgpr0
+    %0:_(s32) = COPY $vgpr0
+    %1:sgpr_64 = COPY $sgpr30_sgpr31
+    %2:_(s32) = G_CONSTANT i32 17
+    %3:_(s32) = G_SMIN %0, %2
+    %4:_(s32) = G_CONSTANT i32 -12
+    %5:_(s32) = G_SMAX %3, %4
+    $vgpr0 = COPY %5(s32)
+    %6:ccr_sgpr_64 = COPY %1
+    S_SETPC_B64_return %6, implicit $vgpr0
+...
+
+---
+name: test_max_min_K1Val_K0_i32
+legalized: true
+tracksRegLiveness: true
+body: |
+  bb.1:
+    liveins: $vgpr0, $sgpr30_sgpr31
+
+    ; CHECK-LABEL: name: test_max_min_K1Val_K0_i32
+    ; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 17
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -12
+    ; CHECK: [[AMDGPU_SMED3_:%[0-9]+]]:_(s32) = G_AMDGPU_SMED3 [[COPY]], [[C1]], [[C]]
+    ; CHECK: $vgpr0 = COPY [[AMDGPU_SMED3_]](s32)
+    ; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
+    ; CHECK: S_SETPC_B64_return [[COPY2]], implicit $vgpr0
+    %0:_(s32) = COPY $vgpr0
+    %1:sgpr_64 = COPY $sgpr30_sgpr31
+    %2:_(s32) = G_CONSTANT i32 17
+    %3:_(s32) = G_SMIN %2, %0
+    %4:_(s32) = G_CONSTANT i32 -12
+    %5:_(s32) = G_SMAX %3, %4
+    $vgpr0 = COPY %5(s32)
+    %6:ccr_sgpr_64 = COPY %1
+    S_SETPC_B64_return %6, implicit $vgpr0
+...
+
+---
+name: test_max_K0min_ValK1__i32
+legalized: true
+tracksRegLiveness: true
+body: |
+  bb.1:
+    liveins: $vgpr0, $sgpr30_sgpr31
+
+    ; CHECK-LABEL: name: test_max_K0min_ValK1__i32
+    ; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 17
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -12
+    ; CHECK: [[AMDGPU_SMED3_:%[0-9]+]]:_(s32) = G_AMDGPU_SMED3 [[COPY]], [[C1]], [[C]]
+    ; CHECK: $vgpr0 = COPY [[AMDGPU_SMED3_]](s32)
+    ; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
+    ; CHECK: S_SETPC_B64_return [[COPY2]], implicit $vgpr0
+    %0:_(s32) = COPY $vgpr0
+    %1:sgpr_64 = COPY $sgpr30_sgpr31
+    %2:_(s32) = G_CONSTANT i32 17
+    %3:_(s32) = G_SMIN %0, %2
+    %4:_(s32) = G_CONSTANT i32 -12
+    %5:_(s32) = G_SMAX %4, %3
+    $vgpr0 = COPY %5(s32)
+    %6:ccr_sgpr_64 = COPY %1
+    S_SETPC_B64_return %6, implicit $vgpr0
+...
+
+---
+name: test_max_K0min_K1Val__i32
+legalized: true
+tracksRegLiveness: true
+body: |
+  bb.1:
+    liveins: $vgpr0, $sgpr30_sgpr31
+
+    ; CHECK-LABEL: name: test_max_K0min_K1Val__i32
+    ; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 17
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -12
+    ; CHECK: [[AMDGPU_SMED3_:%[0-9]+]]:_(s32) = G_AMDGPU_SMED3 [[COPY]], [[C1]], [[C]]
+    ; CHECK: $vgpr0 = COPY [[AMDGPU_SMED3_]](s32)
+    ; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
+    ; CHECK: S_SETPC_B64_return [[COPY2]], implicit $vgpr0
+    %0:_(s32) = COPY $vgpr0
+    %1:sgpr_64 = COPY $sgpr30_sgpr31
+    %2:_(s32) = G_CONSTANT i32 17
+    %3:_(s32) = G_SMIN %2, %0
+    %4:_(s32) = G_CONSTANT i32 -12
+    %5:_(s32) = G_SMAX %4, %3
+    $vgpr0 = COPY %5(s32)
+    %6:ccr_sgpr_64 = COPY %1
+    S_SETPC_B64_return %6, implicit $vgpr0
+...

llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-umed3.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: test_min_max_ValK0_K1_u32
+legalized: true
+tracksRegLiveness: true
+body: |
+  bb.1:
+    liveins: $vgpr0, $sgpr30_sgpr31
+
+    ; CHECK-LABEL: name: test_min_max_ValK0_K1_u32
+    ; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 17
+    ; CHECK: [[AMDGPU_UMED3_:%[0-9]+]]:_(s32) = G_AMDGPU_UMED3 [[COPY]], [[C]], [[C1]]
+    ; CHECK: $vgpr0 = COPY [[AMDGPU_UMED3_]](s32)
+    ; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
+    ; CHECK: S_SETPC_B64_return [[COPY2]], implicit $vgpr0
+    %0:_(s32) = COPY $vgpr0
+    %1:sgpr_64 = COPY $sgpr30_sgpr31
+    %2:_(s32) = G_CONSTANT i32 12
+    %3:_(s32) = G_UMAX %0, %2
+    %4:_(s32) = G_CONSTANT i32 17
+    %5:_(s32) = G_UMIN %3, %4
+    $vgpr0 = COPY %5(s32)
+    %6:ccr_sgpr_64 = COPY %1
+    S_SETPC_B64_return %6, implicit $vgpr0
+...
+
+---
+name: min_max_ValK0_K1_i32
+legalized: true
+tracksRegLiveness: true
+body: |
+  bb.1:
+    liveins: $vgpr0, $sgpr30_sgpr31
+
+    ; CHECK-LABEL: name: min_max_ValK0_K1_i32
+    ; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 17
+    ; CHECK: [[AMDGPU_UMED3_:%[0-9]+]]:_(s32) = G_AMDGPU_UMED3 [[COPY]], [[C]], [[C1]]
+    ; CHECK: $vgpr0 = COPY [[AMDGPU_UMED3_]](s32)
+    ; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
+    ; CHECK: S_SETPC_B64_return [[COPY2]], implicit $vgpr0
+    %0:_(s32) = COPY $vgpr0
+    %1:sgpr_64 = COPY $sgpr30_sgpr31
+    %2:_(s32) = G_CONSTANT i32 12
+    %3:_(s32) = G_UMAX %2, %0
+    %4:_(s32) = G_CONSTANT i32 17
+    %5:_(s32) = G_UMIN %3, %4
+    $vgpr0 = COPY %5(s32)
+    %6:ccr_sgpr_64 = COPY %1
+    S_SETPC_B64_return %6, implicit $vgpr0
+...
+
+---
+name: test_min_K1max_ValK0__u32
+legalized: true
+tracksRegLiveness: true
+body: |
+  bb.1:
+    liveins: $vgpr0, $sgpr30_sgpr31
+
+    ; CHECK-LABEL: name: test_min_K1max_ValK0__u32
+    ; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 17
+    ; CHECK: [[AMDGPU_UMED3_:%[0-9]+]]:_(s32) = G_AMDGPU_UMED3 [[COPY]], [[C]], [[C1]]
+    ; CHECK: $vgpr0 = COPY [[AMDGPU_UMED3_]](s32)
+    ; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
+    ; CHECK: S_SETPC_B64_return [[COPY2]], implicit $vgpr0
+    %0:_(s32) = COPY $vgpr0
+    %1:sgpr_64 = COPY $sgpr30_sgpr31
+    %2:_(s32) = G_CONSTANT i32 12
+    %3:_(s32) = G_UMAX %0, %2
+    %4:_(s32) = G_CONSTANT i32 17
+    %5:_(s32) = G_UMIN %4, %3
+    $vgpr0 = COPY %5(s32)
+    %6:ccr_sgpr_64 = COPY %1
+    S_SETPC_B64_return %6, implicit $vgpr0
+...
+
+---
+name: test_min_K1max_K0Val__u32
+legalized: true
+tracksRegLiveness: true
+body: |
+  bb.1:
+    liveins: $vgpr0, $sgpr30_sgpr31
+
+    ; CHECK-LABEL: name: test_min_K1max_K0Val__u32
+    ; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 17
+    ; CHECK: [[AMDGPU_UMED3_:%[0-9]+]]:_(s32) = G_AMDGPU_UMED3 [[COPY]], [[C]], [[C1]]
+    ; CHECK: $vgpr0 = COPY [[AMDGPU_UMED3_]](s32)
+    ; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
+    ; CHECK: S_SETPC_B64_return [[COPY2]], implicit $vgpr0
+    %0:_(s32) = COPY $vgpr0
+    %1:sgpr_64 = COPY $sgpr30_sgpr31
+    %2:_(s32) = G_CONSTANT i32 12
+    %3:_(s32) = G_UMAX %2, %0
+    %4:_(s32) = G_CONSTANT i32 17
+    %5:_(s32) = G_UMIN %4, %3
+    $vgpr0 = COPY %5(s32)
+    %6:ccr_sgpr_64 = COPY %1
+    S_SETPC_B64_return %6, implicit $vgpr0
+...
+
+---
+name: test_max_min_ValK1_K0_u32
+legalized: true
+tracksRegLiveness: true
+body: |
+  bb.1:
+    liveins: $vgpr0, $sgpr30_sgpr31
+
+    ; CHECK-LABEL: name: test_max_min_ValK1_K0_u32
+    ; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 17
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
+    ; CHECK: [[AMDGPU_UMED3_:%[0-9]+]]:_(s32) = G_AMDGPU_UMED3 [[COPY]], [[C1]], [[C]]
+    ; CHECK: $vgpr0 = COPY [[AMDGPU_UMED3_]](s32)
+    ; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
+    ; CHECK: S_SETPC_B64_return [[COPY2]], implicit $vgpr0
+    %0:_(s32) = COPY $vgpr0
+    %1:sgpr_64 = COPY $sgpr30_sgpr31
+    %2:_(s32) = G_CONSTANT i32 17
+    %3:_(s32) = G_UMIN %0, %2
+    %4:_(s32) = G_CONSTANT i32 12
+    %5:_(s32) = G_UMAX %3, %4
+    $vgpr0 = COPY %5(s32)
+    %6:ccr_sgpr_64 = COPY %1
+    S_SETPC_B64_return %6, implicit $vgpr0
+...
+
+---
+name: test_max_min_K1Val_K0_u32
+legalized: true
+tracksRegLiveness: true
+body: |
+  bb.1:
+    liveins: $vgpr0, $sgpr30_sgpr31
+
+    ; CHECK-LABEL: name: test_max_min_K1Val_K0_u32
+    ; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 17
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
+    ; CHECK: [[AMDGPU_UMED3_:%[0-9]+]]:_(s32) = G_AMDGPU_UMED3 [[COPY]], [[C1]], [[C]]
+    ; CHECK: $vgpr0 = COPY [[AMDGPU_UMED3_]](s32)
+    ; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
+    ; CHECK: S_SETPC_B64_return [[COPY2]], implicit $vgpr0
+    %0:_(s32) = COPY $vgpr0
+    %1:sgpr_64 = COPY $sgpr30_sgpr31
+    %2:_(s32) = G_CONSTANT i32 17
+    %3:_(s32) = G_UMIN %2, %0
+    %4:_(s32) = G_CONSTANT i32 12
+    %5:_(s32) = G_UMAX %3, %4
+    $vgpr0 = COPY %5(s32)
+    %6:ccr_sgpr_64 = COPY %1
+    S_SETPC_B64_return %6, implicit $vgpr0
+...
+
+---
+name: test_max_K0min_ValK1__u32
+legalized: true
+tracksRegLiveness: true
+body: |
+  bb.1:
+    liveins: $vgpr0, $sgpr30_sgpr31
+
+    ; CHECK-LABEL: name: test_max_K0min_ValK1__u32
+    ; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 17
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
+    ; CHECK: [[AMDGPU_UMED3_:%[0-9]+]]:_(s32) = G_AMDGPU_UMED3 [[COPY]], [[C1]], [[C]]
+    ; CHECK: $vgpr0 = COPY [[AMDGPU_UMED3_]](s32)
+    ; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
+    ; CHECK: S_SETPC_B64_return [[COPY2]], implicit $vgpr0
+    %0:_(s32) = COPY $vgpr0
+    %1:sgpr_64 = COPY $sgpr30_sgpr31
+    %2:_(s32) = G_CONSTANT i32 17
+    %3:_(s32) = G_UMIN %0, %2
+    %4:_(s32) = G_CONSTANT i32 12
+    %5:_(s32) = G_UMAX %4, %3
+    $vgpr0 = COPY %5(s32)
+    %6:ccr_sgpr_64 = COPY %1
+    S_SETPC_B64_return %6, implicit $vgpr0
+...
+
+---
+name: test_max_K0min_K1Val__u32
+legalized: true
+tracksRegLiveness: true
+body: |
+  bb.1:
+    liveins: $vgpr0, $sgpr30_sgpr31
+
+    ; CHECK-LABEL: name: test_max_K0min_K1Val__u32
+    ; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 17
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
+    ; CHECK: [[AMDGPU_UMED3_:%[0-9]+]]:_(s32) = G_AMDGPU_UMED3 [[COPY]], [[C1]], [[C]]
+    ; CHECK: $vgpr0 = COPY [[AMDGPU_UMED3_]](s32)
+    ; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
+    ; CHECK: S_SETPC_B64_return [[COPY2]], implicit $vgpr0
+    %0:_(s32) = COPY $vgpr0
+    %1:sgpr_64 = COPY $sgpr30_sgpr31
+    %2:_(s32) = G_CONSTANT i32 17
+    %3:_(s32) = G_UMIN %2, %0
+    %4:_(s32) = G_CONSTANT i32 12
+    %5:_(s32) = G_UMAX %4, %3
+    $vgpr0 = COPY %5(s32)
+    %6:ccr_sgpr_64 = COPY %1
+    S_SETPC_B64_return %6, implicit $vgpr0
+...

llvm/test/CodeGen/AMDGPU/GlobalISel/smed3.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX10 %s
+
+define i32 @test_min_max_ValK0_K1_i32(i32 %a) {
+; GFX10-LABEL: test_min_max_ValK0_K1_i32:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_med3_i32 v0, v0, -12, 17
+; GFX10-NEXT:    ; implicit-def: $vcc_hi
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+  %smax = call i32 @llvm.smax.i32(i32 %a, i32 -12)
+  %smed = call i32 @llvm.smin.i32(i32 %smax, i32 17)
+  ret i32 %smed
+}
+
+define i32 @min_max_ValK0_K1_i32(i32 %a) {
+; GFX10-LABEL: min_max_ValK0_K1_i32:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_med3_i32 v0, v0, -12, 17
+; GFX10-NEXT:    ; implicit-def: $vcc_hi
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+  %smax = call i32 @llvm.smax.i32(i32 -12, i32 %a)
+  %smed = call i32 @llvm.smin.i32(i32 %smax, i32 17)
+  ret i32 %smed
+}
+
+define i32 @test_min_K1max_ValK0__i32(i32 %a) {
+; GFX10-LABEL: test_min_K1max_ValK0__i32:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_med3_i32 v0, v0, -12, 17
+; GFX10-NEXT:    ; implicit-def: $vcc_hi
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+  %smax = call i32 @llvm.smax.i32(i32 %a, i32 -12)
+  %smed = call i32 @llvm.smin.i32(i32 17, i32 %smax)
+  ret i32 %smed
+}
+
+define i32 @test_min_K1max_K0Val__i32(i32 %a) {
+; GFX10-LABEL: test_min_K1max_K0Val__i32:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_med3_i32 v0, v0, -12, 17
+; GFX10-NEXT:    ; implicit-def: $vcc_hi
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+  %smax = call i32 @llvm.smax.i32(i32 -12, i32 %a)
+  %smed = call i32 @llvm.smin.i32(i32 17, i32 %smax)
+  ret i32 %smed
+}
+
+define i32 @test_max_min_ValK1_K0_i32(i32 %a) {
+; GFX10-LABEL: test_max_min_ValK1_K0_i32:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_med3_i32 v0, v0, -12, 17
+; GFX10-NEXT:    ; implicit-def: $vcc_hi
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+  %smin = call i32 @llvm.smin.i32(i32 %a, i32 17)
+  %smed = call i32 @llvm.smax.i32(i32 %smin, i32 -12)
+  ret i32 %smed
+}
+
+define i32 @test_max_min_K1Val_K0_i32(i32 %a) {
+; GFX10-LABEL: test_max_min_K1Val_K0_i32:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_med3_i32 v0, v0, -12, 17
+; GFX10-NEXT:    ; implicit-def: $vcc_hi
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+  %smin = call i32 @llvm.smin.i32(i32 17, i32 %a)
+  %smed = call i32 @llvm.smax.i32(i32 %smin, i32 -12)
+  ret i32 %smed
+}
+
+define i32 @test_max_K0min_ValK1__i32(i32 %a) {
+; GFX10-LABEL: test_max_K0min_ValK1__i32:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_med3_i32 v0, v0, -12, 17
+; GFX10-NEXT:    ; implicit-def: $vcc_hi
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+  %smin = call i32 @llvm.smin.i32(i32 %a, i32 17)
+  %smed = call i32 @llvm.smax.i32(i32 -12, i32 %smin)
+  ret i32 %smed
+}
+
+define i32 @test_max_K0min_K1Val__i32(i32 %a) {
+; GFX10-LABEL: test_max_K0min_K1Val__i32:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_med3_i32 v0, v0, -12, 17
+; GFX10-NEXT:    ; implicit-def: $vcc_hi
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+  %smin = call i32 @llvm.smin.i32(i32 17, i32 %a)
+  %smed = call i32 @llvm.smax.i32(i32 -12, i32 %smin)
+  ret i32 %smed
+}
+
+declare i32 @llvm.smin.i32(i32, i32)
+declare i32 @llvm.smax.i32(i32, i32)

llvm/test/CodeGen/AMDGPU/GlobalISel/umed3.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX10 %s
+
+define i32 @test_min_max_ValK0_K1_u32(i32 %a) {
+; GFX10-LABEL: test_min_max_ValK0_K1_u32:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_med3_u32 v0, v0, 12, 17
+; GFX10-NEXT:    ; implicit-def: $vcc_hi
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+  %umax = call i32 @llvm.umax.i32(i32 %a, i32 12)
+  %umed = call i32 @llvm.umin.i32(i32 %umax, i32 17)
+  ret i32 %umed
+}
+
+define i32 @min_max_ValK0_K1_i32(i32 %a) {
+; GFX10-LABEL: min_max_ValK0_K1_i32:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_med3_u32 v0, v0, 12, 17
+; GFX10-NEXT:    ; implicit-def: $vcc_hi
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+  %umax = call i32 @llvm.umax.i32(i32 12, i32 %a)
+  %umed = call i32 @llvm.umin.i32(i32 %umax, i32 17)
+  ret i32 %umed
+}
+
+define i32 @test_min_K1max_ValK0__u32(i32 %a) {
+; GFX10-LABEL: test_min_K1max_ValK0__u32:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_med3_u32 v0, v0, 12, 17
+; GFX10-NEXT:    ; implicit-def: $vcc_hi
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+  %umax = call i32 @llvm.umax.i32(i32 %a, i32 12)
+  %umed = call i32 @llvm.umin.i32(i32 17, i32 %umax)
+  ret i32 %umed
+}
+
+define i32 @test_min_K1max_K0Val__u32(i32 %a) {
+; GFX10-LABEL: test_min_K1max_K0Val__u32:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_med3_u32 v0, v0, 12, 17
+; GFX10-NEXT:    ; implicit-def: $vcc_hi
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+  %umax = call i32 @llvm.umax.i32(i32 12, i32 %a)
+  %umed = call i32 @llvm.umin.i32(i32 17, i32 %umax)
+  ret i32 %umed
+}
+
+define i32 @test_max_min_ValK1_K0_u32(i32 %a) {
+; GFX10-LABEL: test_max_min_ValK1_K0_u32:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_med3_u32 v0, v0, 12, 17
+; GFX10-NEXT:    ; implicit-def: $vcc_hi
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+  %umin = call i32 @llvm.umin.i32(i32 %a, i32 17)
+  %umed = call i32 @llvm.umax.i32(i32 %umin, i32 12)
+  ret i32 %umed
+}
+
+define i32 @test_max_min_K1Val_K0_u32(i32 %a) {
+; GFX10-LABEL: test_max_min_K1Val_K0_u32:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_med3_u32 v0, v0, 12, 17
+; GFX10-NEXT:    ; implicit-def: $vcc_hi
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+  %umin = call i32 @llvm.umin.i32(i32 17, i32 %a)
+  %umed = call i32 @llvm.umax.i32(i32 %umin, i32 12)
+  ret i32 %umed
+}
+
+define i32 @test_max_K0min_ValK1__u32(i32 %a) {
+; GFX10-LABEL: test_max_K0min_ValK1__u32:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_med3_u32 v0, v0, 12, 17
+; GFX10-NEXT:    ; implicit-def: $vcc_hi
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+  %umin = call i32 @llvm.umin.i32(i32 %a, i32 17)
+  %umed = call i32 @llvm.umax.i32(i32 12, i32 %umin)
+  ret i32 %umed
+}
+
+define i32 @test_max_K0min_K1Val__u32(i32 %a) {
+; GFX10-LABEL: test_max_K0min_K1Val__u32:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_med3_u32 v0, v0, 12, 17
+; GFX10-NEXT:    ; implicit-def: $vcc_hi
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+  %umin = call i32 @llvm.umin.i32(i32 17, i32 %a)
+  %umed = call i32 @llvm.umax.i32(i32 12, i32 %umin)
+  ret i32 %umed
+}
+
+declare i32 @llvm.umin.i32(i32, i32)
+declare i32 @llvm.umax.i32(i32, i32)