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[AMDGPU] Cleanup AMDGPUUsage.rst
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Authored by t-tye on Oct 22 2020, 7:30 PM.

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rGbf6518a806ac: [AMDGPU] Cleanup AMDGPUUsage.rst
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  • Layout and typo improvements.
  • Add memory spaces section.
  • reStructure syntax fixes.

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---------- ----------
Use the ``clang -mcpu <Processor>`` option to specify the AMDGPU processor. The Use the ``clang -mcpu <Processor>`` option to specify the AMDGPU processor. The
names from both the *Processor* and *Alternative Processor* can be used. names from both the *Processor* and *Alternative Processor* can be used.
.. table:: AMDGPU Processors .. table:: AMDGPU Processors
:name: amdgpu-processor-table :name: amdgpu-processor-table
=========== =============== ============ ===== ================= ======= ====================== =========== =============== ============ ===== ============================= ======= ======================
Processor Alternative Target dGPU/ Target ROCm Example Processor Alternative Target dGPU/ Target ROCm Example
Processor Triple APU Features Support Products Processor Triple APU Features Support Products
Architecture Supported Architecture Supported
[Default] [Default]
=========== =============== ============ ===== ================= ======= ====================== =========== =============== ============ ===== ============================= ======= ======================
**Radeon HD 2000/3000 Series (R600)** [AMD-RADEON-HD-2000-3000]_ **Radeon HD 2000/3000 Series (R600)** [AMD-RADEON-HD-2000-3000]_
----------------------------------------------------------------------------------------------- -----------------------------------------------------------------------------------------------------------
``r600`` ``r600`` dGPU ``r600`` ``r600`` dGPU
``r630`` ``r600`` dGPU ``r630`` ``r600`` dGPU
``rs880`` ``r600`` dGPU ``rs880`` ``r600`` dGPU
``rv670`` ``r600`` dGPU ``rv670`` ``r600`` dGPU
**Radeon HD 4000 Series (R700)** [AMD-RADEON-HD-4000]_ **Radeon HD 4000 Series (R700)** [AMD-RADEON-HD-4000]_
----------------------------------------------------------------------------------------------- -----------------------------------------------------------------------------------------------------------
``rv710`` ``r600`` dGPU ``rv710`` ``r600`` dGPU
``rv730`` ``r600`` dGPU ``rv730`` ``r600`` dGPU
``rv770`` ``r600`` dGPU ``rv770`` ``r600`` dGPU
**Radeon HD 5000 Series (Evergreen)** [AMD-RADEON-HD-5000]_ **Radeon HD 5000 Series (Evergreen)** [AMD-RADEON-HD-5000]_
----------------------------------------------------------------------------------------------- -----------------------------------------------------------------------------------------------------------
``cedar`` ``r600`` dGPU ``cedar`` ``r600`` dGPU
``cypress`` ``r600`` dGPU ``cypress`` ``r600`` dGPU
``juniper`` ``r600`` dGPU ``juniper`` ``r600`` dGPU
``redwood`` ``r600`` dGPU ``redwood`` ``r600`` dGPU
``sumo`` ``r600`` dGPU ``sumo`` ``r600`` dGPU
**Radeon HD 6000 Series (Northern Islands)** [AMD-RADEON-HD-6000]_ **Radeon HD 6000 Series (Northern Islands)** [AMD-RADEON-HD-6000]_
----------------------------------------------------------------------------------------------- -----------------------------------------------------------------------------------------------------------
``barts`` ``r600`` dGPU ``barts`` ``r600`` dGPU
``caicos`` ``r600`` dGPU ``caicos`` ``r600`` dGPU
``cayman`` ``r600`` dGPU ``cayman`` ``r600`` dGPU
``turks`` ``r600`` dGPU ``turks`` ``r600`` dGPU
**GCN GFX6 (Southern Islands (SI))** [AMD-GCN-GFX6]_ **GCN GFX6 (Southern Islands (SI))** [AMD-GCN-GFX6]_
----------------------------------------------------------------------------------------------- -----------------------------------------------------------------------------------------------------------
``gfx600`` - ``tahiti`` ``amdgcn`` dGPU ``gfx600`` - ``tahiti`` ``amdgcn`` dGPU
``gfx601`` - ``pitcairn`` ``amdgcn`` dGPU ``gfx601`` - ``pitcairn`` ``amdgcn`` dGPU
- ``verde`` - ``verde``
``gfx602`` - ``hainan`` ``amdgcn`` dGPU ``gfx602`` - ``hainan`` ``amdgcn`` dGPU
- ``oland`` - ``oland``
**GCN GFX7 (Sea Islands (CI))** [AMD-GCN-GFX7]_ **GCN GFX7 (Sea Islands (CI))** [AMD-GCN-GFX7]_
----------------------------------------------------------------------------------------------- -----------------------------------------------------------------------------------------------------------
``gfx700`` - ``kaveri`` ``amdgcn`` APU - A6-7000 ``gfx700`` - ``kaveri`` ``amdgcn`` APU - A6-7000
- A6 Pro-7050B - A6 Pro-7050B
- A8-7100 - A8-7100
- A8 Pro-7150B - A8 Pro-7150B
- A10-7300 - A10-7300
- A10 Pro-7350B - A10 Pro-7350B
- FX-7500 - FX-7500
- A8-7200P - A8-7200P
- A10-7400P - A10-7400P
- FX-7600P - FX-7600P
``gfx701`` - ``hawaii`` ``amdgcn`` dGPU ROCm - FirePro W8100 ``gfx701`` - ``hawaii`` ``amdgcn`` dGPU ROCm - FirePro W8100
- FirePro W9100 - FirePro W9100
- FirePro S9150 - FirePro S9150
- FirePro S9170 - FirePro S9170
``gfx702`` ``amdgcn`` dGPU ROCm - Radeon R9 290 ``gfx702`` ``amdgcn`` dGPU ROCm - Radeon R9 290
- Radeon R9 290x - Radeon R9 290x
- Radeon R390 - Radeon R390
- Radeon R390x - Radeon R390x
``gfx703`` - ``kabini`` ``amdgcn`` APU - E1-2100 ``gfx703`` - ``kabini`` ``amdgcn`` APU - E1-2100
- ``mullins`` - E1-2200 - ``mullins`` - E1-2200
- E1-2500 - E1-2500
- E2-3000 - E2-3000
- E2-3800 - E2-3800
- A4-5000 - A4-5000
- A4-5100 - A4-5100
- A6-5200 - A6-5200
- A4 Pro-3340B - A4 Pro-3340B
``gfx704`` - ``bonaire`` ``amdgcn`` dGPU - Radeon HD 7790 ``gfx704`` - ``bonaire`` ``amdgcn`` dGPU - Radeon HD 7790
- Radeon HD 8770 - Radeon HD 8770
- R7 260 - R7 260
- R7 260X - R7 260X
``gfx705`` ``amdgcn`` APU ``gfx705`` ``amdgcn`` APU *TBA*
.. TODO::
Add product
names.
**GCN GFX8 (Volcanic Islands (VI))** [AMD-GCN-GFX8]_ **GCN GFX8 (Volcanic Islands (VI))** [AMD-GCN-GFX8]_
----------------------------------------------------------------------------------------------- -----------------------------------------------------------------------------------------------------------
``gfx801`` - ``carrizo`` ``amdgcn`` APU - xnack - A6-8500P ``gfx801`` - ``carrizo`` ``amdgcn`` APU - xnack - A6-8500P
[on] - Pro A6-8500B [on] - Pro A6-8500B
- A8-8600P - A8-8600P
- Pro A8-8600B - Pro A8-8600B
- FX-8800P - FX-8800P
- Pro A12-8800B - Pro A12-8800B
\ ``amdgcn`` APU - xnack ROCm - A10-8700P \ ``amdgcn`` APU - xnack ROCm - A10-8700P
[on] - Pro A10-8700B [on] - Pro A10-8700B
- A10-8780P - A10-8780P
\ ``amdgcn`` APU - xnack - A10-9600P \ ``amdgcn`` APU - xnack - A10-9600P
[on] - A10-9630P [on] - A10-9630P
- A12-9700P - A12-9700P
- A12-9730P - A12-9730P
- FX-9800P - FX-9800P
- FX-9830P - FX-9830P
\ ``amdgcn`` APU - xnack - E2-9010 \ ``amdgcn`` APU - xnack - E2-9010
[on] - A6-9210 [on] - A6-9210
- A9-9410 - A9-9410
``gfx802`` - ``iceland`` ``amdgcn`` dGPU - xnack ROCm - Radeon R285 ``gfx802`` - ``iceland`` ``amdgcn`` dGPU - xnack ROCm - Radeon R285
- ``tonga`` [off] - Radeon R9 380 - ``tonga`` [off] - Radeon R9 380
- Radeon R9 385 - Radeon R9 385
``gfx803`` - ``fiji`` ``amdgcn`` dGPU - xnack ROCm - Radeon R9 Nano ``gfx803`` - ``fiji`` ``amdgcn`` dGPU - xnack ROCm - Radeon R9 Nano
[off] - Radeon R9 Fury [off] - Radeon R9 Fury
- Radeon R9 FuryX - Radeon R9 FuryX
- Radeon Pro Duo - Radeon Pro Duo
- FirePro S9300x2 - FirePro S9300x2
- Radeon Instinct MI8 - Radeon Instinct MI8
\ - ``polaris10`` ``amdgcn`` dGPU - xnack ROCm - Radeon RX 470 \ - ``polaris10`` ``amdgcn`` dGPU - xnack ROCm - Radeon RX 470
[off] - Radeon RX 480 [off] - Radeon RX 480
- Radeon Instinct MI6 - Radeon Instinct MI6
\ - ``polaris11`` ``amdgcn`` dGPU - xnack ROCm - Radeon RX 460 \ - ``polaris11`` ``amdgcn`` dGPU - xnack ROCm - Radeon RX 460
[off] [off]
``gfx805`` - ``tongapro`` ``amdgcn`` dGPU - xnack ROCm - FirePro S7150 ``gfx805`` - ``tongapro`` ``amdgcn`` dGPU - xnack ROCm - FirePro S7150
[off] - FirePro S7100 [off] - FirePro S7100
- FirePro W7100 - FirePro W7100
- Mobile FirePro - Mobile FirePro
M7170 M7170
``gfx810`` - ``stoney`` ``amdgcn`` APU - xnack ``gfx810`` - ``stoney`` ``amdgcn`` APU - xnack *TBA*
[on] [on]
.. TODO::
Add product
names.
**GCN GFX9** [AMD-GCN-GFX9]_ **GCN GFX9** [AMD-GCN-GFX9]_
----------------------------------------------------------------------------------------------- -----------------------------------------------------------------------------------------------------------
``gfx900`` ``amdgcn`` dGPU - xnack ROCm - Radeon Vega ``gfx900`` ``amdgcn`` dGPU - xnack ROCm - Radeon Vega
[off] Frontier Edition [off] Frontier Edition
- Radeon RX Vega 56 - Radeon RX Vega 56
- Radeon RX Vega 64 - Radeon RX Vega 64
- Radeon RX Vega 64 - Radeon RX Vega 64
Liquid Liquid
- Radeon Instinct MI25 - Radeon Instinct MI25
``gfx902`` ``amdgcn`` APU - xnack - Ryzen 3 2200G ``gfx902`` ``amdgcn`` APU - xnack - Ryzen 3 2200G
[on] - Ryzen 5 2400G [on] - Ryzen 5 2400G
``gfx904`` ``amdgcn`` dGPU - xnack *TBA* ``gfx904`` ``amdgcn`` dGPU - xnack *TBA*
[off] [off]
.. TODO:: .. TODO::
Add product Add product
names. names.
``gfx906`` ``amdgcn`` dGPU - xnack - Radeon Instinct MI50 ``gfx906`` ``amdgcn`` dGPU - xnack - Radeon Instinct MI50
[off] - Radeon Instinct MI60 [off] - Radeon Instinct MI60
- sram-ecc - Radeon VII - sram-ecc - Radeon VII
[off] - Radeon Pro VII [off] - Radeon Pro VII
``gfx908`` ``amdgcn`` dGPU - xnack *TBA* ``gfx908`` ``amdgcn`` dGPU - xnack *TBA*
[off] [off]
- sram-ecc - sram-ecc
[on] [on]
.. TODO:: .. TODO::
Add product Add product
names. names.
``gfx909`` ``amdgcn`` APU - xnack *TBA* ``gfx909`` ``amdgcn`` APU - xnack *TBA*
[on] [off]
.. TODO:: .. TODO::
Add product Add product
names. names.
**GCN GFX10** [AMD-GCN-GFX10]_ **GCN GFX10** [AMD-GCN-GFX10]_
----------------------------------------------------------------------------------------------- -----------------------------------------------------------------------------------------------------------
``gfx1010`` ``amdgcn`` dGPU - xnack - Radeon RX 5700 ``gfx1010`` ``amdgcn`` dGPU - xnack - Radeon RX 5700
[off] - Radeon RX 5700 XT [off] - Radeon RX 5700 XT
- wavefrontsize64 - Radeon Pro 5600 XT - wavefrontsize64 - Radeon Pro 5600 XT
[off] - Radeon Pro 5600M [off] - Radeon Pro 5600M
- cumode - cumode
[off] [off]
``gfx1011`` ``amdgcn`` dGPU - xnack *TBA* ``gfx1011`` ``amdgcn`` dGPU - xnack *TBA*
[off] [off]
- wavefrontsize64 - wavefrontsize64
[off] [off]
- cumode - cumode
[off] [off]
.. TODO .. TODO::
Add product Add product
names. names.
``gfx1012`` ``amdgcn`` dGPU - xnack - Radeon RX 5500 ``gfx1012`` ``amdgcn`` dGPU - xnack - Radeon RX 5500
[off] - Radeon RX 5500 XT [off] - Radeon RX 5500 XT
- wavefrontsize64 - wavefrontsize64
[off] [off]
- cumode - cumode
[off] [off]
``gfx1030`` ``amdgcn`` dGPU - wavefrontsize64 *TBA* ``gfx1030`` ``amdgcn`` dGPU - wavefrontsize64 *TBA*
[off] [off]
- cumode - cumode
[off] [off]
.. TODO .. TODO::
Add product Add product
names. names.
``gfx1031`` ``amdgcn`` dGPU - wavefrontsize64 *TBA* ``gfx1031`` ``amdgcn`` dGPU - wavefrontsize64 *TBA*
[off] [off]
- cumode - cumode
[off] [off]
.. TODO .. TODO::
Add product Add product
names. names.
``gfx1032`` ``amdgcn`` dGPU - wavefrontsize64 *TBA* ``gfx1032`` ``amdgcn`` dGPU - wavefrontsize64 *TBA*
[off] [off]
- cumode - cumode
[off] [off]
.. TODO .. TODO::
Add product Add product
names. names.
=========== =============== ============ ===== ================= ======= ======================
=========== =============== ============ ===== ============================= ======= ======================
.. _amdgpu-target-features: .. _amdgpu-target-features:
Target Features Target Features
--------------- ---------------
Target features control how code is generated to support certain Target features control how code is generated to support certain
processor specific features. Not all target features are supported by processor specific features. Not all target features are supported by
▲ Show 20 Lines • Show All 481 Lines • ▼ Show 20 Lines ``EF_AMDGPU_SRAM_ECC`` 0x00000200 Indicates if the ``sram-ecc``
be 0. be 0.
See See
:ref:`amdgpu-target-features`. :ref:`amdgpu-target-features`.
================================= ========== ============================= ================================= ========== =============================
.. table:: AMDGPU ``EF_AMDGPU_MACH`` Values .. table:: AMDGPU ``EF_AMDGPU_MACH`` Values
:name: amdgpu-ef-amdgpu-mach-table :name: amdgpu-ef-amdgpu-mach-table
================================= ========== ============================= ==================================== ========== =============================
Name Value Description (see Name Value Description (see
:ref:`amdgpu-processor-table`) :ref:`amdgpu-processor-table`)
================================= ========== ============================= ==================================== ========== =============================
``EF_AMDGPU_MACH_NONE`` 0x000 *not specified* ``EF_AMDGPU_MACH_NONE`` 0x000 *not specified*
``EF_AMDGPU_MACH_R600_R600`` 0x001 ``r600`` ``EF_AMDGPU_MACH_R600_R600`` 0x001 ``r600``
``EF_AMDGPU_MACH_R600_R630`` 0x002 ``r630`` ``EF_AMDGPU_MACH_R600_R630`` 0x002 ``r630``
``EF_AMDGPU_MACH_R600_RS880`` 0x003 ``rs880`` ``EF_AMDGPU_MACH_R600_RS880`` 0x003 ``rs880``
``EF_AMDGPU_MACH_R600_RV670`` 0x004 ``rv670`` ``EF_AMDGPU_MACH_R600_RV670`` 0x004 ``rv670``
``EF_AMDGPU_MACH_R600_RV710`` 0x005 ``rv710`` ``EF_AMDGPU_MACH_R600_RV710`` 0x005 ``rv710``
``EF_AMDGPU_MACH_R600_RV730`` 0x006 ``rv730`` ``EF_AMDGPU_MACH_R600_RV730`` 0x006 ``rv730``
``EF_AMDGPU_MACH_R600_RV770`` 0x007 ``rv770`` ``EF_AMDGPU_MACH_R600_RV770`` 0x007 ``rv770``
``EF_AMDGPU_MACH_R600_CEDAR`` 0x008 ``cedar`` ``EF_AMDGPU_MACH_R600_CEDAR`` 0x008 ``cedar``
``EF_AMDGPU_MACH_R600_CYPRESS`` 0x009 ``cypress`` ``EF_AMDGPU_MACH_R600_CYPRESS`` 0x009 ``cypress``
``EF_AMDGPU_MACH_R600_JUNIPER`` 0x00a ``juniper`` ``EF_AMDGPU_MACH_R600_JUNIPER`` 0x00a ``juniper``
``EF_AMDGPU_MACH_R600_REDWOOD`` 0x00b ``redwood`` ``EF_AMDGPU_MACH_R600_REDWOOD`` 0x00b ``redwood``
``EF_AMDGPU_MACH_R600_SUMO`` 0x00c ``sumo`` ``EF_AMDGPU_MACH_R600_SUMO`` 0x00c ``sumo``
``EF_AMDGPU_MACH_R600_BARTS`` 0x00d ``barts`` ``EF_AMDGPU_MACH_R600_BARTS`` 0x00d ``barts``
``EF_AMDGPU_MACH_R600_CAICOS`` 0x00e ``caicos`` ``EF_AMDGPU_MACH_R600_CAICOS`` 0x00e ``caicos``
``EF_AMDGPU_MACH_R600_CAYMAN`` 0x00f ``cayman`` ``EF_AMDGPU_MACH_R600_CAYMAN`` 0x00f ``cayman``
``EF_AMDGPU_MACH_R600_TURKS`` 0x010 ``turks`` ``EF_AMDGPU_MACH_R600_TURKS`` 0x010 ``turks``
*reserved* 0x011 - Reserved for ``r600`` *reserved* 0x011 - Reserved for ``r600``
0x01f architecture processors. 0x01f architecture processors.
``EF_AMDGPU_MACH_AMDGCN_GFX600`` 0x020 ``gfx600`` ``EF_AMDGPU_MACH_AMDGCN_GFX600`` 0x020 ``gfx600``
``EF_AMDGPU_MACH_AMDGCN_GFX601`` 0x021 ``gfx601`` ``EF_AMDGPU_MACH_AMDGCN_GFX601`` 0x021 ``gfx601``
``EF_AMDGPU_MACH_AMDGCN_GFX700`` 0x022 ``gfx700`` ``EF_AMDGPU_MACH_AMDGCN_GFX700`` 0x022 ``gfx700``
``EF_AMDGPU_MACH_AMDGCN_GFX701`` 0x023 ``gfx701`` ``EF_AMDGPU_MACH_AMDGCN_GFX701`` 0x023 ``gfx701``
``EF_AMDGPU_MACH_AMDGCN_GFX702`` 0x024 ``gfx702`` ``EF_AMDGPU_MACH_AMDGCN_GFX702`` 0x024 ``gfx702``
``EF_AMDGPU_MACH_AMDGCN_GFX703`` 0x025 ``gfx703`` ``EF_AMDGPU_MACH_AMDGCN_GFX703`` 0x025 ``gfx703``
``EF_AMDGPU_MACH_AMDGCN_GFX704`` 0x026 ``gfx704`` ``EF_AMDGPU_MACH_AMDGCN_GFX704`` 0x026 ``gfx704``
*reserved* 0x027 Reserved. *reserved* 0x027 Reserved.
``EF_AMDGPU_MACH_AMDGCN_GFX801`` 0x028 ``gfx801`` ``EF_AMDGPU_MACH_AMDGCN_GFX801`` 0x028 ``gfx801``
``EF_AMDGPU_MACH_AMDGCN_GFX802`` 0x029 ``gfx802`` ``EF_AMDGPU_MACH_AMDGCN_GFX802`` 0x029 ``gfx802``
``EF_AMDGPU_MACH_AMDGCN_GFX803`` 0x02a ``gfx803`` ``EF_AMDGPU_MACH_AMDGCN_GFX803`` 0x02a ``gfx803``
``EF_AMDGPU_MACH_AMDGCN_GFX810`` 0x02b ``gfx810`` ``EF_AMDGPU_MACH_AMDGCN_GFX810`` 0x02b ``gfx810``
``EF_AMDGPU_MACH_AMDGCN_GFX900`` 0x02c ``gfx900`` ``EF_AMDGPU_MACH_AMDGCN_GFX900`` 0x02c ``gfx900``
``EF_AMDGPU_MACH_AMDGCN_GFX902`` 0x02d ``gfx902`` ``EF_AMDGPU_MACH_AMDGCN_GFX902`` 0x02d ``gfx902``
``EF_AMDGPU_MACH_AMDGCN_GFX904`` 0x02e ``gfx904`` ``EF_AMDGPU_MACH_AMDGCN_GFX904`` 0x02e ``gfx904``
``EF_AMDGPU_MACH_AMDGCN_GFX906`` 0x02f ``gfx906`` ``EF_AMDGPU_MACH_AMDGCN_GFX906`` 0x02f ``gfx906``
``EF_AMDGPU_MACH_AMDGCN_GFX908`` 0x030 ``gfx908`` ``EF_AMDGPU_MACH_AMDGCN_GFX908`` 0x030 ``gfx908``
``EF_AMDGPU_MACH_AMDGCN_GFX909`` 0x031 ``gfx909`` ``EF_AMDGPU_MACH_AMDGCN_GFX909`` 0x031 ``gfx909``
*reserved* 0x032 Reserved. *reserved* 0x032 Reserved.
``EF_AMDGPU_MACH_AMDGCN_GFX1010`` 0x033 ``gfx1010`` ``EF_AMDGPU_MACH_AMDGCN_GFX1010`` 0x033 ``gfx1010``
``EF_AMDGPU_MACH_AMDGCN_GFX1011`` 0x034 ``gfx1011`` ``EF_AMDGPU_MACH_AMDGCN_GFX1011`` 0x034 ``gfx1011``
``EF_AMDGPU_MACH_AMDGCN_GFX1012`` 0x035 ``gfx1012`` ``EF_AMDGPU_MACH_AMDGCN_GFX1012`` 0x035 ``gfx1012``
``EF_AMDGPU_MACH_AMDGCN_GFX1030`` 0x036 ``gfx1030`` ``EF_AMDGPU_MACH_AMDGCN_GFX1030`` 0x036 ``gfx1030``
``EF_AMDGPU_MACH_AMDGCN_GFX1031`` 0x037 ``gfx1031`` ``EF_AMDGPU_MACH_AMDGCN_GFX1031`` 0x037 ``gfx1031``
``EF_AMDGPU_MACH_AMDGCN_GFX1032`` 0x038 ``gfx1032`` ``EF_AMDGPU_MACH_AMDGCN_GFX1032`` 0x038 ``gfx1032``
*reserved* 0x039 Reserved. *reserved* 0x039 Reserved.
``EF_AMDGPU_MACH_AMDGCN_GFX602`` 0x03a ``gfx602`` ``EF_AMDGPU_MACH_AMDGCN_GFX602`` 0x03a ``gfx602``
``EF_AMDGPU_MACH_AMDGCN_GFX705`` 0x03b ``gfx705`` ``EF_AMDGPU_MACH_AMDGCN_GFX705`` 0x03b ``gfx705``
``EF_AMDGPU_MACH_AMDGCN_GFX805`` 0x03c ``gfx805`` ``EF_AMDGPU_MACH_AMDGCN_GFX805`` 0x03c ``gfx805``
================================= ========== ============================= ==================================== ========== =============================
Sections Sections
-------- --------
An AMDGPU target ELF code object has the standard ELF sections which include: An AMDGPU target ELF code object has the standard ELF sections which include:
.. table:: AMDGPU ELF Sections .. table:: AMDGPU ELF Sections
:name: amdgpu-elf-sections-table :name: amdgpu-elf-sections-table
▲ Show 20 Lines • Show All 71 Lines • ▼ Show 20 Lines
Code Object V2 Note Records (--amdhsa-code-object-version=2) Code Object V2 Note Records (--amdhsa-code-object-version=2)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
.. warning:: Code Object V2 is not the default code object version emitted by .. warning:: Code Object V2 is not the default code object version emitted by
this version of LLVM. For a description of the notes generated with the this version of LLVM. For a description of the notes generated with the
default configuration (Code Object V3) see :ref:`amdgpu-note-records-v3`. default configuration (Code Object V3) see :ref:`amdgpu-note-records-v3`.
The AMDGPU backend code object uses the following ELF note record in the The AMDGPU backend code object uses the following ELF note record in the
``.note`` section when compiling for Code Object ``.note`` section when compiling for Code Object V2
V2 (--amdhsa-code-object-version=2). (--amdhsa-code-object-version=2).
Additional note records may be present, but any which are not documented here Additional note records may be present, but any which are not documented here
are deprecated and should not be used. are deprecated and should not be used.
.. table:: AMDGPU Code Object V2 ELF Note Records .. table:: AMDGPU Code Object V2 ELF Note Records
:name: amdgpu-elf-note-records-table-v2 :name: amdgpu-elf-note-records-table-v2
===== ============================== ====================================== ===== ============================== ======================================
▲ Show 20 Lines • Show All 1,419 Lines • ▼ Show 20 Lines "AddrSpaceQual" string Kernel argument address space
- "Private" - "Private"
- "Global" - "Global"
- "Constant" - "Constant"
- "Local" - "Local"
- "Generic" - "Generic"
- "Region" - "Region"
.. TODO:: .. TODO::
Is GlobalBuffer only Global Is GlobalBuffer only Global
or Constant? Is or Constant? Is
DynamicSharedPointer always DynamicSharedPointer always
Local? Can HCC allow Generic? Local? Can HCC allow Generic?
How can Private or Region How can Private or Region
ever happen? ever happen?
"AccQual" string Kernel argument access "AccQual" string Kernel argument access
qualifier. Only present if qualifier. Only present if
"ValueKind" is "Image" or "ValueKind" is "Image" or
"Pipe". Values "Pipe". Values
are: are:
- "ReadOnly" - "ReadOnly"
- "WriteOnly" - "WriteOnly"
- "ReadWrite" - "ReadWrite"
.. TODO:: .. TODO::
Does this apply to Does this apply to
GlobalBuffer? GlobalBuffer?
"ActualAccQual" string The actual memory accesses "ActualAccQual" string The actual memory accesses
performed by the kernel on the performed by the kernel on the
kernel argument. Only present if kernel argument. Only present if
"ValueKind" is "GlobalBuffer", "ValueKind" is "GlobalBuffer",
"Image", or "Pipe". This may be "Image", or "Pipe". This may be
more restrictive than indicated more restrictive than indicated
by "AccQual" to reflect what the by "AccQual" to reflect what the
kernel actual does. If not kernel actual does. If not
Show All 21 Lines "IsVolatile" boolean Indicates if the kernel argument
present if "ValueKind" is present if "ValueKind" is
"GlobalBuffer". "GlobalBuffer".
"IsPipe" boolean Indicates if the kernel argument "IsPipe" boolean Indicates if the kernel argument
is pipe qualified. Only present is pipe qualified. Only present
if "ValueKind" is "Pipe". if "ValueKind" is "Pipe".
.. TODO:: .. TODO::
Can GlobalBuffer be pipe Can GlobalBuffer be pipe
qualified? qualified?
================= ============== ========= ================================ ================= ============== ========= ================================
.. ..
.. table:: AMDHSA Code Object V2 Kernel Code Properties Metadata Map .. table:: AMDHSA Code Object V2 Kernel Code Properties Metadata Map
:name: amdgpu-amdhsa-code-object-kernel-code-properties-metadata-map-table-v2 :name: amdgpu-amdhsa-code-object-kernel-code-properties-metadata-map-table-v2
============================ ============== ========= ===================== ============================ ============== ========= =====================
▲ Show 20 Lines • Show All 405 Lines • ▼ Show 20 Lines ".address_space" string Kernel argument address space
- "private" - "private"
- "global" - "global"
- "constant" - "constant"
- "local" - "local"
- "generic" - "generic"
- "region" - "region"
.. TODO:: .. TODO::
Is "global_buffer" only "global" Is "global_buffer" only "global"
or "constant"? Is or "constant"? Is
"dynamic_shared_pointer" always "dynamic_shared_pointer" always
"local"? Can HCC allow "generic"? "local"? Can HCC allow "generic"?
How can "private" or "region" How can "private" or "region"
ever happen? ever happen?
".access" string Kernel argument access ".access" string Kernel argument access
qualifier. Only present if qualifier. Only present if
".value_kind" is "image" or ".value_kind" is "image" or
"pipe". Values "pipe". Values
are: are:
- "read_only" - "read_only"
- "write_only" - "write_only"
- "read_write" - "read_write"
.. TODO:: .. TODO::
Does this apply to Does this apply to
"global_buffer"? "global_buffer"?
".actual_access" string The actual memory accesses ".actual_access" string The actual memory accesses
performed by the kernel on the performed by the kernel on the
kernel argument. Only present if kernel argument. Only present if
".value_kind" is "global_buffer", ".value_kind" is "global_buffer",
"image", or "pipe". This may be "image", or "pipe". This may be
more restrictive than indicated more restrictive than indicated
by ".access" to reflect what the by ".access" to reflect what the
kernel actual does. If not kernel actual does. If not
Show All 21 Lines ".is_volatile" boolean Indicates if the kernel argument
present if ".value_kind" is present if ".value_kind" is
"global_buffer". "global_buffer".
".is_pipe" boolean Indicates if the kernel argument ".is_pipe" boolean Indicates if the kernel argument
is pipe qualified. Only present is pipe qualified. Only present
if ".value_kind" is "pipe". if ".value_kind" is "pipe".
.. TODO:: .. TODO::
Can "global_buffer" be pipe Can "global_buffer" be pipe
qualified? qualified?
====================== ============== ========= ================================ ====================== ============== ========= ================================
.. ..
Kernel Dispatch Kernel Dispatch
~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~
The HSA architected queuing language (AQL) defines a user space memory The HSA architected queuing language (AQL) defines a user space memory interface
interface that can be used to control the dispatch of kernels, in an agent that can be used to control the dispatch of kernels, in an agent independent
independent way. An agent can have zero or more AQL queues created for it using way. An agent can have zero or more AQL queues created for it using the ROCm
the ROCm runtime, in which AQL packets (all of which are 64 bytes) can be runtime, in which AQL packets (all of which are 64 bytes) can be placed. See the
placed. See the *HSA Platform System Architecture Specification* [HSA]_ for the *HSA Platform System Architecture Specification* [HSA]_ for the AQL queue
AQL queue mechanics and packet layouts. mechanics and packet layouts.
The packet processor of a kernel agent is responsible for detecting and The packet processor of a kernel agent is responsible for detecting and
dispatching HSA kernels from the AQL queues associated with it. For AMD GPUs the dispatching HSA kernels from the AQL queues associated with it. For AMD GPUs the
packet processor is implemented by the hardware command processor (CP), packet processor is implemented by the hardware command processor (CP),
asynchronous dispatch controller (ADC) and shader processor input controller asynchronous dispatch controller (ADC) and shader processor input controller
(SPI). (SPI).
The ROCm runtime can be used to allocate an AQL queue object. It uses the kernel The ROCm runtime can be used to allocate an AQL queue object. It uses the kernel
Show All 40 Lines8. CP ensures that when the a wavefront starts executing the kernel machine
register state is defined in register state is defined in
:ref:`amdgpu-amdhsa-initial-kernel-execution-state`. :ref:`amdgpu-amdhsa-initial-kernel-execution-state`.
9. The prolog of the kernel machine code (see 9. The prolog of the kernel machine code (see
:ref:`amdgpu-amdhsa-kernel-prolog`) sets up the machine state as necessary :ref:`amdgpu-amdhsa-kernel-prolog`) sets up the machine state as necessary
before continuing executing the machine code that corresponds to the kernel. before continuing executing the machine code that corresponds to the kernel.
10. When the kernel dispatch has completed execution, CP signals the completion 10. When the kernel dispatch has completed execution, CP signals the completion
signal specified in the kernel dispatch packet if not 0. signal specified in the kernel dispatch packet if not 0.
.. _amdgpu-amdhsa-memory-spaces:
Memory Spaces
~~~~~~~~~~~~~
The memory space properties are:
.. table:: AMDHSA Memory Spaces
:name: amdgpu-amdhsa-memory-spaces-table
================= =========== ======== ======= ==================
Memory Space Name HSA Segment Hardware Address NULL Value
Name Name Size
================= =========== ======== ======= ==================
Private private scratch 32 0x00000000
Local group LDS 32 0xFFFFFFFF
Global global global 64 0x0000000000000000
Constant constant *same as 64 0x0000000000000000
global*
Generic flat flat 64 0x0000000000000000
Region N/A GDS 32 *not implemented
for AMDHSA*
================= =========== ======== ======= ==================
The global and constant memory spaces both use global virtual addresses, which
are the same virtual address space used by the CPU. However, some virtual
addresses may only be accessible to the CPU, some only accessible by the GPU,
and some by both.
Using the constant memory space indicates that the data will not change during
the execution of the kernel. This allows scalar read instructions to be
used. The vector and scalar L1 caches are invalidated of volatile data before
each kernel dispatch execution to allow constant memory to change values between
kernel dispatches.
The local memory space uses the hardware Local Data Store (LDS) which is
automatically allocated when the hardware creates work-groups of wavefronts, and
freed when all the wavefronts of a work-group have terminated. The data store
(DS) instructions can be used to access it.
The private memory space uses the hardware scratch memory support. If the kernel
uses scratch, then the hardware allocates memory that is accessed using
wavefront lane dword (4 byte) interleaving. The mapping used from private
address to physical address is:
``wavefront-scratch-base +
(private-address * wavefront-size * 4) +
(wavefront-lane-id * 4)``
There are different ways that the wavefront scratch base address is determined
by a wavefront (see :ref:`amdgpu-amdhsa-initial-kernel-execution-state`). This
memory can be accessed in an interleaved manner using buffer instruction with
the scratch buffer descriptor and per wavefront scratch offset, by the scratch
instructions, or by flat instructions. If each lane of a wavefront accesses the
same private address, the interleaving results in adjacent dwords being accessed
and hence requires fewer cache lines to be fetched. Multi-dword access is not
supported except by flat and scratch instructions in GFX9-GFX10.
The generic address space uses the hardware flat address support available in
GFX7-GFX10. This uses two fixed ranges of virtual addresses (the private and
local apertures), that are outside the range of addressible global memory, to
map from a flat address to a private or local address.
FLAT instructions can take a flat address and access global, private (scratch)
and group (LDS) memory depending in if the address is within one of the
aperture ranges. Flat access to scratch requires hardware aperture setup and
setup in the kernel prologue (see
:ref:`amdgpu-amdhsa-kernel-prolog-flat-scratch`). Flat access to LDS requires
hardware aperture setup and M0 (GFX7-GFX8) register setup (see
:ref:`amdgpu-amdhsa-kernel-prolog-m0`).
To convert between a segment address and a flat address the base address of the
apertures address can be used. For GFX7-GFX8 these are available in the
:ref:`amdgpu-amdhsa-hsa-aql-queue` the address of which can be obtained with
Queue Ptr SGPR (see :ref:`amdgpu-amdhsa-initial-kernel-execution-state`). For
GFX9-GFX10 the aperture base addresses are directly available as inline constant
registers ``SRC_SHARED_BASE/LIMIT`` and ``SRC_PRIVATE_BASE/LIMIT``. In 64 bit
address mode the aperture sizes are 2^32 bytes and the base is aligned to 2^32
which makes it easier to convert from flat to segment or segment to flat.
Image and Samplers Image and Samplers
~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~
Image and sample handles created by the ROCm runtime are 64-bit addresses of a Image and sample handles created by the ROCm runtime are 64-bit addresses of a
hardware 32-byte V# and 48 byte S# object respectively. In order to support the hardware 32-byte V# and 48 byte S# object respectively. In order to support the
HSA ``query_sampler`` operations two extra dwords are used to store the HSA BRIG HSA ``query_sampler`` operations two extra dwords are used to store the HSA BRIG
enumeration values for the queries that are not trivially deducible from the S# enumeration values for the queries that are not trivially deducible from the S#
representation. representation.
▲ Show 20 Lines • Show All 654 Lines • ▼ Show 20 Lines .. table:: SGPR Register Set Up Order
========== ========================== ====== ============================== ========== ========================== ====== ==============================
SGPR Order Name Number Description SGPR Order Name Number Description
(kernel descriptor enable of (kernel descriptor enable of
field) SGPRs field) SGPRs
========== ========================== ====== ============================== ========== ========================== ====== ==============================
First Private Segment Buffer 4 V# that can be used, together First Private Segment Buffer 4 V# that can be used, together
(enable_sgpr_private with Scratch Wavefront Offset (enable_sgpr_private with Scratch Wavefront Offset
_segment_buffer) as an offset, to access the _segment_buffer) as an offset, to access the
private address space using a private memory space using a
segment address. segment address.
CP uses the value provided by CP uses the value provided by
the runtime. the runtime.
then Dispatch Ptr 2 64-bit address of AQL dispatch then Dispatch Ptr 2 64-bit address of AQL dispatch
(enable_sgpr_dispatch_ptr) packet for kernel dispatch (enable_sgpr_dispatch_ptr) packet for kernel dispatch
actually executing. actually executing.
then Queue Ptr 2 64-bit address of amd_queue_t then Queue Ptr 2 64-bit address of amd_queue_t
▲ Show 20 Lines • Show All 183 Lines • ▼ Show 20 Lines:ref:`amdgpu-amdhsa-vgpr-register-set-up-order-table`.
.. table:: VGPR Register Set Up Order .. table:: VGPR Register Set Up Order
:name: amdgpu-amdhsa-vgpr-register-set-up-order-table :name: amdgpu-amdhsa-vgpr-register-set-up-order-table
========== ========================== ====== ============================== ========== ========================== ====== ==============================
VGPR Order Name Number Description VGPR Order Name Number Description
(kernel descriptor enable of (kernel descriptor enable of
field) VGPRs field) VGPRs
========== ========================== ====== ============================== ========== ========================== ====== ==============================
First Work-Item Id X 1 32-bit work item id in X First Work-Item Id X 1 32-bit work-item id in X
(Always initialized) dimension of work-group for (Always initialized) dimension of work-group for
wavefront lane. wavefront lane.
then Work-Item Id Y 1 32-bit work item id in Y then Work-Item Id Y 1 32-bit work-item id in Y
(enable_vgpr_workitem_id dimension of work-group for (enable_vgpr_workitem_id dimension of work-group for
> 0) wavefront lane. > 0) wavefront lane.
then Work-Item Id Z 1 32-bit work item id in Z then Work-Item Id Z 1 32-bit work-item id in Z
(enable_vgpr_workitem_id dimension of work-group for (enable_vgpr_workitem_id dimension of work-group for
> 1) wavefront lane. > 1) wavefront lane.
========== ========================== ====== ============================== ========== ========================== ====== ==============================
The setting of registers is done by GPU CP/ADC/SPI hardware as follows: The setting of registers is done by GPU CP/ADC/SPI hardware as follows:
1. SGPRs before the Work-Group Ids are set by CP using the 16 User Data 1. SGPRs before the Work-Group Ids are set by CP using the 16 User Data
registers. registers.
▲ Show 20 Lines • Show All 242 Lines • ▼ Show 20 Lines* The vector memory operations access a single vector L1 cache shared by all
SIMDs a CU. Therefore, no special action is required for coherence between the SIMDs a CU. Therefore, no special action is required for coherence between the
lanes of a single wavefront, or for coherence between wavefronts in the same lanes of a single wavefront, or for coherence between wavefronts in the same
work-group. A ``buffer_wbinvl1_vol`` is required for coherence between work-group. A ``buffer_wbinvl1_vol`` is required for coherence between
wavefronts executing in different work-groups as they may be executing on wavefronts executing in different work-groups as they may be executing on
different CUs. different CUs.
* The scalar memory operations access a scalar L1 cache shared by all wavefronts * The scalar memory operations access a scalar L1 cache shared by all wavefronts
on a group of CUs. The scalar and vector L1 caches are not coherent. However, on a group of CUs. The scalar and vector L1 caches are not coherent. However,
scalar operations are used in a restricted way so do not impact the memory scalar operations are used in a restricted way so do not impact the memory
model. See :ref:`amdgpu-address-spaces`. model. See :ref:`amdgpu-amdhsa-memory-spaces`.
* The vector and scalar memory operations use an L2 cache shared by all CUs on * The vector and scalar memory operations use an L2 cache shared by all CUs on
the same agent. the same agent.
* The L2 cache has independent channels to service disjoint ranges of virtual * The L2 cache has independent channels to service disjoint ranges of virtual
addresses. addresses.
* Each CU has a separate request queue per channel. Therefore, the vector and * Each CU has a separate request queue per channel. Therefore, the vector and
scalar memory operations performed by wavefronts executing in different scalar memory operations performed by wavefronts executing in different
work-groups (which may be executing on different CUs) of an agent can be work-groups (which may be executing on different CUs) of an agent can be
reordered relative to each other. A ``s_waitcnt vmcnt(0)`` is required to reordered relative to each other. A ``s_waitcnt vmcnt(0)`` is required to
Show All 38 Lines* The vector memory operations access a vector L0 cache. There is a single L0
wavefront. However, a ``BUFFER_GL0_INV`` is required for coherence between wavefront. However, a ``BUFFER_GL0_INV`` is required for coherence between
wavefronts executing in the same work-group as they may be executing on SIMDs wavefronts executing in the same work-group as they may be executing on SIMDs
of different CUs that access different L0s. A ``BUFFER_GL0_INV`` is also of different CUs that access different L0s. A ``BUFFER_GL0_INV`` is also
required for coherence between wavefronts executing in different work-groups required for coherence between wavefronts executing in different work-groups
as they may be executing on different WGPs. as they may be executing on different WGPs.
* The scalar memory operations access a scalar L0 cache shared by all wavefronts * The scalar memory operations access a scalar L0 cache shared by all wavefronts
on a WGP. The scalar and vector L0 caches are not coherent. However, scalar on a WGP. The scalar and vector L0 caches are not coherent. However, scalar
operations are used in a restricted way so do not impact the memory model. See operations are used in a restricted way so do not impact the memory model. See
:ref:`amdgpu-address-spaces`. :ref:`amdgpu-amdhsa-memory-spaces`.
* The vector and scalar memory L0 caches use an L1 cache shared by all WGPs on * The vector and scalar memory L0 caches use an L1 cache shared by all WGPs on
the same SA. Therefore, no special action is required for coherence between the same SA. Therefore, no special action is required for coherence between
the wavefronts of a single work-group. However, a ``BUFFER_GL1_INV`` is the wavefronts of a single work-group. However, a ``BUFFER_GL1_INV`` is
required for coherence between wavefronts executing in different work-groups required for coherence between wavefronts executing in different work-groups
as they may be executing on different SAs that access different L1s. as they may be executing on different SAs that access different L1s.
* The L1 caches have independent quadrants to service disjoint ranges of virtual * The L1 caches have independent quadrants to service disjoint ranges of virtual
addresses. addresses.
* Each L0 cache has a separate request queue per L1 quadrant. Therefore, the * Each L0 cache has a separate request queue per L1 quadrant. Therefore, the
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
AMDGPU backend only uses scalar memory operations to access memory that is AMDGPU backend only uses scalar memory operations to access memory that is
proven to not change during the execution of the kernel dispatch. This includes proven to not change during the execution of the kernel dispatch. This includes
constant address space and global address space for program scope const constant address space and global address space for program scope const
variables. Therefore, the kernel machine code does not have to maintain the variables. Therefore, the kernel machine code does not have to maintain the
scalar L1 cache to ensure it is coherent with the vector L1 cache. The scalar scalar L1 cache to ensure it is coherent with the vector L1 cache. The scalar
and vector L1 caches are invalidated between kernel dispatches by CP since and vector L1 caches are invalidated between kernel dispatches by CP since
constant address space data may change between kernel dispatch executions. See constant address space data may change between kernel dispatch executions. See
:ref:`amdgpu-address-spaces`. :ref:`amdgpu-amdhsa-memory-spaces`.
The one exception is if scalar writes are used to spill SGPR registers. In this The one exception is if scalar writes are used to spill SGPR registers. In this
case the AMDGPU backend ensures the memory location used to spill is never case the AMDGPU backend ensures the memory location used to spill is never
accessed by vector memory operations at the same time. If scalar writes are used accessed by vector memory operations at the same time. If scalar writes are used
then a ``s_dcache_wb`` is inserted before the ``s_endpgm`` and before a function then a ``s_dcache_wb`` is inserted before the ``s_endpgm`` and before a function
return since the locations may be used for vector memory instructions by a return since the locations may be used for vector memory instructions by a
future wavefront that uses the same scratch area, or a function call that future wavefront that uses the same scratch area, or a function call that
creates a frame at the same address, respectively. There is no need for a creates a frame at the same address, respectively. There is no need for a
▲ Show 20 Lines • Show All 3,608 Lines • Show Last 20 Lines