[AArch64][GlobalISel] Don't use explicit zero registers for compare results.

[aemerson]

Summary

These cause problems for later optimizations, just using an unused vreg like SelectionDAG generates better code in the end, and obviates the need for some GISel specific flag optimizations.

[paquette]

LGTM

llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp

case TargetOpcode::G_SELECT: {
     const Register CondReg = I.getOperand(1).getReg();
     const Register TReg = I.getOperand(2).getReg();
     const Register FReg = I.getOperand(3).getReg();
 
     if (tryOptSelect(I))
       return true;
 
     Register CSelOpc = selectSelectOpc(I, MRI, RBI);
+    // Make sure to use an unused vreg instead of wzr, so that the peephole
+    // optimizations will be able to optimize these.
+    Register DeadVReg = MRI.createVirtualRegister(&AArch64::GPR32RegClass);
     MachineInstr &TstMI =
         *BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::ANDSWri))
-             .addDef(AArch64::WZR)
+             .addDef(DeadVReg)
              .addUse(CondReg)
              .addImm(AArch64_AM::encodeLogicalImmediate(1, 32));
 
     MachineInstr &CSelMI = *BuildMI(MBB, I, I.getDebugLoc(), TII.get(CSelOpc))
                                 .addDef(I.getOperand(0).getReg())
                                 .addUse(TReg)
                                 .addUse(FReg)
                                 .addImm(AArch64CC::NE);
AArch64InstructionSelector::emitCMN(MachineOperand &LHS, MachineOperand &RHS,
   return emitADDS(Is32Bit ? AArch64::WZR : AArch64::XZR, LHS, RHS, MIRBuilder);
 }
 
 MachineInstr *
 AArch64InstructionSelector::emitTST(MachineOperand &LHS, MachineOperand &RHS,
                                     MachineIRBuilder &MIRBuilder) const {
   assert(LHS.isReg() && RHS.isReg() && "Expected register operands?");
   MachineRegisterInfo &MRI = MIRBuilder.getMF().getRegInfo();
-  unsigned RegSize = MRI.getType(LHS.getReg()).getSizeInBits();
+  LLT Ty = MRI.getType(LHS.getReg());
+  unsigned RegSize = Ty.getSizeInBits();
   bool Is32Bit = (RegSize == 32);
   const unsigned OpcTable[3][2] = {{AArch64::ANDSXri, AArch64::ANDSWri},
                                    {AArch64::ANDSXrs, AArch64::ANDSWrs},
                                    {AArch64::ANDSXrr, AArch64::ANDSWrr}};
-  Register ZReg = Is32Bit ? AArch64::WZR : AArch64::XZR;
   // ANDS needs a logical immediate for its immediate form. Check if we can
   // fold one in.
   if (auto ValAndVReg = getConstantVRegValWithLookThrough(RHS.getReg(), MRI)) {
     if (AArch64_AM::isLogicalImmediate(ValAndVReg->Value, RegSize)) {
-      auto TstMI = MIRBuilder.buildInstr(OpcTable[0][Is32Bit], {ZReg}, {LHS});
+      auto TstMI = MIRBuilder.buildInstr(OpcTable[0][Is32Bit], {Ty}, {LHS});
       TstMI.addImm(
           AArch64_AM::encodeLogicalImmediate(ValAndVReg->Value, RegSize));
       constrainSelectedInstRegOperands(*TstMI, TII, TRI, RBI);
       return &*TstMI;
     }
   }
 
   if (auto Fns = selectLogicalShiftedRegister(RHS))
-    return emitInstr(OpcTable[1][Is32Bit], {ZReg}, {LHS}, MIRBuilder, Fns);
-  return emitInstr(OpcTable[2][Is32Bit], {ZReg}, {LHS, RHS}, MIRBuilder);
+    return emitInstr(OpcTable[1][Is32Bit], {Ty}, {LHS}, MIRBuilder, Fns);
+  return emitInstr(OpcTable[2][Is32Bit], {Ty}, {LHS, RHS}, MIRBuilder);
 }
 
 std::pair<MachineInstr *, CmpInst::Predicate>
 AArch64InstructionSelector::emitIntegerCompare(
     MachineOperand &LHS, MachineOperand &RHS, MachineOperand &Predicate,
     MachineIRBuilder &MIRBuilder) const {
   assert(LHS.isReg() && RHS.isReg() && "Expected LHS and RHS to be registers!");
   assert(Predicate.isPredicate() && "Expected predicate?");
if (!ImmFns) {
     ImmFns = select12BitValueWithLeftShift(C);
     if (!ImmFns)
       return nullptr;
     P = NewP;
   }
 
   // At this point, we know we can select an immediate form. Go ahead and do
   // that.
-  Register ZReg;
   unsigned Opc;
   if (Size == 32) {
-    ZReg = AArch64::WZR;
     Opc = AArch64::SUBSWri;
   } else {
-    ZReg = AArch64::XZR;
     Opc = AArch64::SUBSXri;
   }
 
-  auto CmpMI = MIB.buildInstr(Opc, {ZReg}, {LHS.getReg()});
+  auto CmpMI = MIB.buildInstr(Opc, {Ty}, {LHS.getReg()});
   for (auto &RenderFn : *ImmFns)
     RenderFn(CmpMI);
   constrainSelectedInstRegOperands(*CmpMI, TII, TRI, RBI);
   return &*CmpMI;
 }
 
 MachineInstr *AArch64InstructionSelector::tryOptArithShiftedCompare(
     MachineOperand &LHS, MachineOperand &RHS, MachineIRBuilder &MIB) const {
   // We are looking for the following pattern:
   //
   // shift = G_SHL/ASHR/LHSR y, c
   // ...
   // cmp = G_ICMP pred, something, shift
   //
   // Since we will select the G_ICMP to a SUBS, we can potentially fold the
   // shift into the subtract.
   static const unsigned OpcTable[2] = {AArch64::SUBSWrs, AArch64::SUBSXrs};
-  static const Register ZRegTable[2] = {AArch64::WZR, AArch64::XZR};
   auto ImmFns = selectShiftedRegister(RHS);
   if (!ImmFns)
     return nullptr;
   MachineRegisterInfo &MRI = *MIB.getMRI();
   auto Ty = MRI.getType(LHS.getReg());
   assert(!Ty.isVector() && "Expected scalar or pointer only?");
   unsigned Size = Ty.getSizeInBits();
   bool Idx = (Size == 64);
-  Register ZReg = ZRegTable[Idx];
   unsigned Opc = OpcTable[Idx];
-  auto CmpMI = MIB.buildInstr(Opc, {ZReg}, {LHS.getReg()});
+  auto CmpMI = MIB.buildInstr(Opc, {Ty}, {LHS.getReg()});
   for (auto &RenderFn : *ImmFns)
     RenderFn(CmpMI);
   constrainSelectedInstRegOperands(*CmpMI, TII, TRI, RBI);
   return &*CmpMI;
 }
 
 bool AArch64InstructionSelector::tryOptShuffleDupLane(
     MachineInstr &I, LLT DstTy, LLT SrcTy, ArrayRef<int> Mask,

llvm/test/CodeGen/AArch64/GlobalISel/fold-fp-select.mir

bb.0:
     ; CHECK: liveins: $s0, $s1, $w1
     ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
     ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
     ; CHECK: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
     ; CHECK: FCMPSri [[COPY]], implicit-def $nzcv
     ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
     ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY [[CSINCWr]]
     ; CHECK: [[COPY3:%[0-9]+]]:gpr32 = COPY [[COPY2]]
-    ; CHECK: $wzr = ANDSWri [[COPY3]], 0, implicit-def $nzcv
+    ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY3]], 0, implicit-def $nzcv
     ; CHECK: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[FMOVS0_]], [[COPY1]], 1, implicit $nzcv
     ; CHECK: $w1 = COPY [[CSINCWr]]
     ; CHECK: $s0 = COPY [[FCSELSrrr]]
     ; CHECK: RET_ReallyLR implicit $s0
     %0:fpr(s32) = COPY $s0
     %1:fpr(s32) = COPY $s1
     %2:fpr(s32) = G_FCONSTANT float 0.000000e+00
     %5:gpr(s32) = G_FCMP floatpred(oeq), %0(s32), %2
body:             |
   bb.0:
     liveins: $s0, $w0
 
     ; CHECK-LABEL: name: using_icmp
     ; CHECK: liveins: $s0, $w0
     ; CHECK: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0
     ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0
     ; CHECK: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
-    ; CHECK: $wzr = SUBSWri [[COPY]], 0, 0, implicit-def $nzcv
+    ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 0, 0, implicit-def $nzcv
     ; CHECK: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[COPY1]], [[FMOVS0_]], 0, implicit $nzcv
     ; CHECK: $s0 = COPY [[FCSELSrrr]]
     ; CHECK: RET_ReallyLR implicit $s0
     %0:gpr(s32) = COPY $w0
     %1:fpr(s32) = COPY $s0
     %2:gpr(s32) = G_CONSTANT i32 0
     %5:fpr(s32) = G_FCONSTANT float 0.000000e+00
     %6:gpr(s32) = G_ICMP intpred(eq), %0(s32), %2
bb.0:
     ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
     ; CHECK: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
     ; CHECK: FCMPSri [[COPY]], implicit-def $nzcv
     ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
     ; CHECK: [[CSINCWr1:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
     ; CHECK: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr [[CSINCWr]], [[CSINCWr1]]
     ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY [[ORRWrr]]
     ; CHECK: [[COPY3:%[0-9]+]]:gpr32 = COPY [[COPY2]]
-    ; CHECK: $wzr = ANDSWri [[COPY3]], 0, implicit-def $nzcv
+    ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY3]], 0, implicit-def $nzcv
     ; CHECK: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[FMOVS0_]], [[COPY1]], 1, implicit $nzcv
     ; CHECK: $s0 = COPY [[FCSELSrrr]]
     ; CHECK: RET_ReallyLR implicit $s0
     %0:fpr(s32) = COPY $s0
     %1:fpr(s32) = COPY $s1
     %2:fpr(s32) = G_FCONSTANT float 0.000000e+00
     %5:gpr(s32) = G_FCMP floatpred(ueq), %0(s32), %2
     %3:gpr(s1) = G_TRUNC %5(s32)
bb.0:
     ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
     ; CHECK: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
     ; CHECK: FCMPSri [[COPY]], implicit-def $nzcv
     ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 5, implicit $nzcv
     ; CHECK: [[CSINCWr1:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv
     ; CHECK: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr [[CSINCWr]], [[CSINCWr1]]
     ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY [[ORRWrr]]
     ; CHECK: [[COPY3:%[0-9]+]]:gpr32 = COPY [[COPY2]]
-    ; CHECK: $wzr = ANDSWri [[COPY3]], 0, implicit-def $nzcv
+    ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY3]], 0, implicit-def $nzcv
     ; CHECK: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[COPY1]], [[FMOVS0_]], 1, implicit $nzcv
     ; CHECK: $s0 = COPY [[FCSELSrrr]]
     ; CHECK: RET_ReallyLR implicit $s0
     %0:fpr(s32) = COPY $s0
     %1:fpr(s32) = COPY $s1
     %2:fpr(s32) = G_FCONSTANT float 0.000000e+00
     %5:gpr(s32) = G_FCMP floatpred(one), %0(s32), %2
     %3:gpr(s1) = G_TRUNC %5(s32)
bb.0:
     ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
     ; CHECK: [[FMOVD0_:%[0-9]+]]:fpr64 = FMOVD0
     ; CHECK: FCMPDri [[COPY]], implicit-def $nzcv
     ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
     ; CHECK: [[CSINCWr1:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
     ; CHECK: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr [[CSINCWr]], [[CSINCWr1]]
     ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY [[ORRWrr]]
     ; CHECK: [[COPY3:%[0-9]+]]:gpr32 = COPY [[COPY2]]
-    ; CHECK: $wzr = ANDSWri [[COPY3]], 0, implicit-def $nzcv
+    ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY3]], 0, implicit-def $nzcv
     ; CHECK: [[FCSELDrrr:%[0-9]+]]:fpr64 = FCSELDrrr [[FMOVD0_]], [[COPY1]], 1, implicit $nzcv
     ; CHECK: $d0 = COPY [[FCSELDrrr]]
     ; CHECK: RET_ReallyLR implicit $d0
     %0:fpr(s64) = COPY $d0
     %1:fpr(s64) = COPY $d1
     %2:fpr(s64) = G_FCONSTANT double 0.000000e+00
     %5:gpr(s32) = G_FCMP floatpred(ueq), %0(s64), %2
     %3:gpr(s1) = G_TRUNC %5(s32)
bb.0:
     ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
     ; CHECK: [[FMOVD0_:%[0-9]+]]:fpr64 = FMOVD0
     ; CHECK: FCMPDri [[COPY]], implicit-def $nzcv
     ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 5, implicit $nzcv
     ; CHECK: [[CSINCWr1:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv
     ; CHECK: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr [[CSINCWr]], [[CSINCWr1]]
     ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY [[ORRWrr]]
     ; CHECK: [[COPY3:%[0-9]+]]:gpr32 = COPY [[COPY2]]
-    ; CHECK: $wzr = ANDSWri [[COPY3]], 0, implicit-def $nzcv
+    ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY3]], 0, implicit-def $nzcv
     ; CHECK: [[FCSELDrrr:%[0-9]+]]:fpr64 = FCSELDrrr [[COPY1]], [[FMOVD0_]], 1, implicit $nzcv
     ; CHECK: $d0 = COPY [[FCSELDrrr]]
     ; CHECK: RET_ReallyLR implicit $d0
     %0:fpr(s64) = COPY $d0
     %1:fpr(s64) = COPY $d1
     %2:fpr(s64) = G_FCONSTANT double 0.000000e+00
     %5:gpr(s32) = G_FCMP floatpred(one), %0(s64), %2
     %3:gpr(s1) = G_TRUNC %5(s32)
bb.0:
     liveins: $s0, $w0, $w1
 
     ; CHECK-LABEL: name: copy_from_physreg
     ; CHECK: liveins: $s0, $w0, $w1
     ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
     ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0
     ; CHECK: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
     ; CHECK: BL @copy_from_physreg, implicit-def $w0
-    ; CHECK: $wzr = ANDSWri [[COPY]], 0, implicit-def $nzcv
+    ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY]], 0, implicit-def $nzcv
     ; CHECK: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[COPY1]], [[FMOVS0_]], 1, implicit $nzcv
     ; CHECK: BL @copy_from_physreg, implicit-def $w0
     ; CHECK: $s0 = COPY [[FCSELSrrr]]
     ; CHECK: RET_ReallyLR implicit $s0
     %0:gpr(s32) = COPY $w0
     %1:fpr(s32) = COPY $s0
     %5:fpr(s32) = G_FCONSTANT float 0.000000e+00
     BL @copy_from_physreg, implicit-def $w0
     %3:gpr(s1) = G_TRUNC %0(s32)
     %4:fpr(s32) = G_SELECT %3(s1), %1, %5
     BL @copy_from_physreg, implicit-def $w0
     $s0 = COPY %4(s32)
     RET_ReallyLR implicit $s0
 
 ...

llvm/test/CodeGen/AArch64/GlobalISel/fold-select.mir

body:             |
   bb.0:
     liveins: $w0, $w1
 
     ; CHECK-LABEL: name: eq
     ; CHECK: liveins: $w0, $w1
     ; CHECK: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0
     ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
     ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr
-    ; CHECK: $wzr = SUBSWri [[COPY]], 0, 0, implicit-def $nzcv
+    ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 0, 0, implicit-def $nzcv
     ; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[COPY2]], [[COPY1]], 0, implicit $nzcv
     ; CHECK: $w0 = COPY [[CSELWr]]
     ; CHECK: RET_ReallyLR implicit $w0
     %0:gpr(s32) = COPY $w0
     %1:gpr(s32) = COPY $w1
     %2:gpr(s32) = G_CONSTANT i32 0
     %5:gpr(s32) = G_ICMP intpred(eq), %0(s32), %2
     %3:gpr(s1) = G_TRUNC %5(s32)
bb.0:
     ; constant. So, the CSELWr should use the predicate code 11, rather than
     ; 13.
 
     ; CHECK-LABEL: name: check_update_predicate
     ; CHECK: liveins: $w0, $w1
     ; CHECK: %copy1:gpr32sp = COPY $w0
     ; CHECK: %copy2:gpr32 = COPY $w1
     ; CHECK: %cst:gpr32 = MOVi32imm -1
-    ; CHECK: $wzr = SUBSWri %copy1, 0, 0, implicit-def $nzcv
+    ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri %copy1, 0, 0, implicit-def $nzcv
     ; CHECK: %select:gpr32 = CSELWr %cst, %copy2, 11, implicit $nzcv
     ; CHECK: $w0 = COPY %select
     ; CHECK: RET_ReallyLR implicit $w0
     %copy1:gpr(s32) = COPY $w0
     %copy2:gpr(s32) = COPY $w1
     %cst:gpr(s32) = G_CONSTANT i32 -1
     %cmp:gpr(s32) = G_ICMP intpred(sle), %copy1(s32), %cst
     %trunc:gpr(s1) = G_TRUNC %cmp(s32)
     %select:gpr(s32) = G_SELECT %trunc(s1), %cst, %copy2
     $w0 = COPY %select(s32)
     RET_ReallyLR implicit $w0
 ...

llvm/test/CodeGen/AArch64/GlobalISel/opt-and-tbnz-tbz.mir

 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   ; CHECK-LABEL: name: dont_fold_and_lt
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.0(0x40000000), %bb.1(0x40000000)
   ; CHECK:   liveins: $w0
   ; CHECK:   [[COPY:%[0-9]+]]:gpr32 = COPY $w0
-  ; CHECK:   $wzr = ANDSWri [[COPY]], 0, implicit-def $nzcv
+  ; CHECK:   [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY]], 0, implicit-def $nzcv
   ; CHECK:   [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv
   ; CHECK:   TBNZW [[CSINCWr]], 0, %bb.1
   ; CHECK:   B %bb.0
   ; CHECK: bb.1:
   ; CHECK:   RET_ReallyLR
   bb.0:
     successors: %bb.0, %bb.1
     liveins: $w0

 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   ; CHECK-LABEL: name: dont_fold_and_gt
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.0(0x40000000), %bb.1(0x40000000)
   ; CHECK:   liveins: $w0
   ; CHECK:   [[COPY:%[0-9]+]]:gpr32 = COPY $w0
-  ; CHECK:   $wzr = ANDSWri [[COPY]], 0, implicit-def $nzcv
+  ; CHECK:   [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY]], 0, implicit-def $nzcv
   ; CHECK:   [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv
   ; CHECK:   TBNZW [[CSINCWr]], 0, %bb.1
   ; CHECK:   B %bb.0
   ; CHECK: bb.1:
   ; CHECK:   RET_ReallyLR
   bb.0:
     successors: %bb.0, %bb.1
     liveins: $w0

 legalized:       true
 regBankSelected: true
 body:             |
   ; CHECK-LABEL: name: dont_fold_cmp_not_0
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.0(0x40000000), %bb.1(0x40000000)
   ; CHECK:   [[COPY:%[0-9]+]]:gpr64 = COPY $x0
   ; CHECK:   [[ANDXri:%[0-9]+]]:gpr64sp = ANDXri [[COPY]], 8064
-  ; CHECK:   $xzr = SUBSXri [[ANDXri]], 4, 0, implicit-def $nzcv
+  ; CHECK:   [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[ANDXri]], 4, 0, implicit-def $nzcv
   ; CHECK:   Bcc 1, %bb.1, implicit $nzcv
   ; CHECK:   B %bb.0
   ; CHECK: bb.1:
   ; CHECK:   RET_ReallyLR
   bb.0:
     successors: %bb.0, %bb.1
     liveins: $x0
     %0:gpr(s64) = COPY $x0

llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-compare.mir

 body:             |
   bb.0:
     liveins: $w0, $w1
     ; CHECK-LABEL: name: tst_s32
     ; CHECK: liveins: $w0, $w1
     ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
     ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $wzr
     ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
-    ; CHECK: $wzr = ANDSWrr [[COPY1]], [[COPY]], implicit-def $nzcv
+    ; CHECK: [[ANDSWrr:%[0-9]+]]:gpr32 = ANDSWrr [[COPY1]], [[COPY]], implicit-def $nzcv
     ; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm]], [[COPY1]], 0, implicit $nzcv
     ; CHECK: $w0 = COPY [[CSELWr]]
     ; CHECK: RET_ReallyLR implicit $w0
     %0:gpr(s32) = COPY $w0
     %1:gpr(s32) = COPY $w1
     %2:gpr(s32) = G_CONSTANT i32 0
     %6:gpr(s32) = G_CONSTANT i32 1
     %3:gpr(s32) = G_AND %2, %1
body:             |
   bb.0:
     liveins: $x0, $x1
     ; CHECK-LABEL: name: tst_s64
     ; CHECK: liveins: $x0, $x1
     ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x1
     ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $xzr
     ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
     ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
-    ; CHECK: $xzr = ANDSXrr [[COPY1]], [[COPY]], implicit-def $nzcv
+    ; CHECK: [[ANDSXrr:%[0-9]+]]:gpr64 = ANDSXrr [[COPY1]], [[COPY]], implicit-def $nzcv
     ; CHECK: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[SUBREG_TO_REG]], [[COPY1]], 0, implicit $nzcv
     ; CHECK: $x0 = COPY [[CSELXr]]
     ; CHECK: RET_ReallyLR implicit $x0
     %0:gpr(s64) = COPY $x0
     %1:gpr(s64) = COPY $x1
     %2:gpr(s64) = G_CONSTANT i64 0
     %6:gpr(s64) = G_CONSTANT i64 1
     %3:gpr(s64) = G_AND %2, %1
body:             |
   bb.0:
     liveins: $w0, $w1
     ; CHECK-LABEL: name: no_tst_unsigned_compare
     ; CHECK: liveins: $w0, $w1
     ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
     ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $wzr
     ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
     ; CHECK: [[ANDWrr:%[0-9]+]]:gpr32common = ANDWrr [[COPY1]], [[COPY]]
-    ; CHECK: $wzr = SUBSWri [[ANDWrr]], 0, 0, implicit-def $nzcv
+    ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[ANDWrr]], 0, 0, implicit-def $nzcv
     ; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm]], [[COPY1]], 8, implicit $nzcv
     ; CHECK: $w0 = COPY [[CSELWr]]
     ; CHECK: RET_ReallyLR implicit $w0
     %0:gpr(s32) = COPY $w0
     %1:gpr(s32) = COPY $w1
     %2:gpr(s32) = G_CONSTANT i32 0
     %6:gpr(s32) = G_CONSTANT i32 1
     %3:gpr(s32) = G_AND %2, %1
body:             |
   bb.0:
     liveins: $w0, $w1
     ; CHECK-LABEL: name: no_tst_nonzero
     ; CHECK: liveins: $w0, $w1
     ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
     ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $wzr
     ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
     ; CHECK: [[ANDWrr:%[0-9]+]]:gpr32common = ANDWrr [[COPY1]], [[COPY]]
-    ; CHECK: $wzr = SUBSWri [[ANDWrr]], 42, 0, implicit-def $nzcv
+    ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[ANDWrr]], 42, 0, implicit-def $nzcv
     ; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm]], [[COPY1]], 8, implicit $nzcv
     ; CHECK: $w0 = COPY [[CSELWr]]
     ; CHECK: RET_ReallyLR implicit $w0
     %0:gpr(s32) = COPY $w0
     %1:gpr(s32) = COPY $w1
     %2:gpr(s32) = G_CONSTANT i32 0
     %6:gpr(s32) = G_CONSTANT i32 1
     %3:gpr(s32) = G_AND %2, %1

 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $w0, $w1
     ; CHECK-LABEL: name: imm_tst
     ; CHECK: liveins: $w0, $w1
     ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
-    ; CHECK: $wzr = ANDSWri [[COPY]], 1, implicit-def $nzcv
+    ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY]], 1, implicit-def $nzcv
     ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
     ; CHECK: $w0 = COPY [[CSINCWr]]
     ; CHECK: RET_ReallyLR implicit $w0
     %0:gpr(s32) = COPY $w0
     %1:gpr(s32) = COPY $w1
     %2:gpr(s32) = G_CONSTANT i32 0
     %3:gpr(s32) = G_CONSTANT i32 1
 

 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $w0, $w1
     ; CHECK-LABEL: name: no_imm_tst_not_logical_imm
     ; CHECK: liveins: $w0, $w1
     ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
     ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm -1
-    ; CHECK: $wzr = ANDSWrr [[COPY]], [[MOVi32imm]], implicit-def $nzcv
+    ; CHECK: [[ANDSWrr:%[0-9]+]]:gpr32 = ANDSWrr [[COPY]], [[MOVi32imm]], implicit-def $nzcv
     ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
     ; CHECK: $w0 = COPY [[CSINCWr]]
     ; CHECK: RET_ReallyLR implicit $w0
     %0:gpr(s32) = COPY $w0
     %1:gpr(s32) = COPY $w1
     %2:gpr(s32) = G_CONSTANT i32 0
     %3:gpr(s32) = G_CONSTANT i32 1
 
bb.0:
     ; We should fold the G_SHL into the ANDS to get ANDSXrs.
     ;
     ; CHECK-LABEL: name: tst_fold_shift_s64
     ; CHECK: liveins: $x0, $x1
     ; CHECK: %copy:gpr64 = COPY $x1
     ; CHECK: %zero:gpr64 = COPY $xzr
     ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
     ; CHECK: %one:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
-    ; CHECK: $xzr = ANDSXrs %zero, %copy, 16, implicit-def $nzcv
+    ; CHECK: [[ANDSXrs:%[0-9]+]]:gpr64 = ANDSXrs %zero, %copy, 16, implicit-def $nzcv
     ; CHECK: %select:gpr64 = CSELXr %one, %zero, 0, implicit $nzcv
     ; CHECK: $x0 = COPY %select
     ; CHECK: RET_ReallyLR implicit $x0
     %copy:gpr(s64) = COPY $x1
     %zero:gpr(s64) = G_CONSTANT i64 0
     %one:gpr(s64) = G_CONSTANT i64 1
     %cst:gpr(s64) = G_CONSTANT i64 16
     %shift:gpr(s64) = G_SHL %copy(s64), %cst(s64)
bb.0:
     liveins: $w0, $w1
     ; We should fold the G_SHL into the ANDS to get ANDSWrs.
     ;
     ; CHECK-LABEL: name: tst_fold_shift_s32
     ; CHECK: liveins: $w0, $w1
     ; CHECK: %copy:gpr32 = COPY $w1
     ; CHECK: %zero:gpr32 = COPY $wzr
     ; CHECK: %one:gpr32 = MOVi32imm 1
-    ; CHECK: $wzr = ANDSWrs %zero, %copy, 16, implicit-def $nzcv
+    ; CHECK: [[ANDSWrs:%[0-9]+]]:gpr32 = ANDSWrs %zero, %copy, 16, implicit-def $nzcv
     ; CHECK: %select:gpr32 = CSELWr %one, %zero, 0, implicit $nzcv
     ; CHECK: $w0 = COPY %select
     ; CHECK: RET_ReallyLR implicit $w0
     %copy:gpr(s32) = COPY $w1
     %zero:gpr(s32) = G_CONSTANT i32 0
     %one:gpr(s32) = G_CONSTANT i32 1
     %cst:gpr(s32) = G_CONSTANT i32 16
     %shift:gpr(s32) = G_SHL %copy(s32), %cst(s32)
     %and:gpr(s32) = G_AND %zero, %shift
     %cmp:gpr(s32) = G_ICMP intpred(eq), %and(s32), %zero
     %cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
     %select:gpr(s32) = G_SELECT %cmp_trunc(s1), %one, %zero
     $w0 = COPY %select(s32)
     RET_ReallyLR implicit $w0

llvm/test/CodeGen/AArch64/GlobalISel/opt-shifted-reg-compare.mir

 body:             |
   bb.0:
     liveins: $w0, $w1
 
     ; CHECK-LABEL: name: eq_shl
     ; CHECK: liveins: $w0, $w1
     ; CHECK: %copy0:gpr32 = COPY $w0
     ; CHECK: %copy1:gpr32 = COPY $w1
-    ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 3, implicit-def $nzcv
+    ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 3, implicit-def $nzcv
     ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
     ; CHECK: $w0 = COPY %cmp
     ; CHECK: RET_ReallyLR implicit $w0
     %copy0:gpr(s32) = COPY $w0
     %copy1:gpr(s32) = COPY $w1
     %three:gpr(s32) = G_CONSTANT i32 3
     %shift:gpr(s32) = G_SHL %copy0, %three(s32)
     %cmp:gpr(s32) = G_ICMP intpred(eq), %copy1(s32), %shift

 body:             |
   bb.0:
     liveins: $w0, $w1
 
     ; CHECK-LABEL: name: eq_ashr
     ; CHECK: liveins: $w0, $w1
     ; CHECK: %copy0:gpr32 = COPY $w0
     ; CHECK: %copy1:gpr32 = COPY $w1
-    ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 131, implicit-def $nzcv
+    ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 131, implicit-def $nzcv
     ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
     ; CHECK: $w0 = COPY %cmp
     ; CHECK: RET_ReallyLR implicit $w0
     %copy0:gpr(s32) = COPY $w0
     %copy1:gpr(s32) = COPY $w1
     %three:gpr(s32) = G_CONSTANT i32 3
     %shift:gpr(s32) = G_ASHR %copy0, %three(s32)
     %cmp:gpr(s32) = G_ICMP intpred(eq), %copy1(s32), %shift

 body:             |
   bb.0:
     liveins: $w0, $w1
 
     ; CHECK-LABEL: name: eq_lshr
     ; CHECK: liveins: $w0, $w1
     ; CHECK: %copy0:gpr32 = COPY $w0
     ; CHECK: %copy1:gpr32 = COPY $w1
-    ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 67, implicit-def $nzcv
+    ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 67, implicit-def $nzcv
     ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
     ; CHECK: $w0 = COPY %cmp
     ; CHECK: RET_ReallyLR implicit $w0
     %copy0:gpr(s32) = COPY $w0
     %copy1:gpr(s32) = COPY $w1
     %three:gpr(s32) = G_CONSTANT i32 3
     %shift:gpr(s32) = G_LSHR %copy0, %three(s32)
     %cmp:gpr(s32) = G_ICMP intpred(eq), %copy1(s32), %shift

 body:             |
   bb.0:
     liveins: $w0, $w1
 
     ; CHECK-LABEL: name: ne_shl
     ; CHECK: liveins: $w0, $w1
     ; CHECK: %copy0:gpr32 = COPY $w0
     ; CHECK: %copy1:gpr32 = COPY $w1
-    ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 3, implicit-def $nzcv
+    ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 3, implicit-def $nzcv
     ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 0, implicit $nzcv
     ; CHECK: $w0 = COPY %cmp
     ; CHECK: RET_ReallyLR implicit $w0
     %copy0:gpr(s32) = COPY $w0
     %copy1:gpr(s32) = COPY $w1
     %three:gpr(s32) = G_CONSTANT i32 3
     %shift:gpr(s32) = G_SHL %copy0, %three(s32)
     %cmp:gpr(s32) = G_ICMP intpred(ne), %copy1(s32), %shift

 body:             |
   bb.0:
     liveins: $w0, $w1
 
     ; CHECK-LABEL: name: ne_ashr
     ; CHECK: liveins: $w0, $w1
     ; CHECK: %copy0:gpr32 = COPY $w0
     ; CHECK: %copy1:gpr32 = COPY $w1
-    ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 131, implicit-def $nzcv
+    ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 131, implicit-def $nzcv
     ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 0, implicit $nzcv
     ; CHECK: $w0 = COPY %cmp
     ; CHECK: RET_ReallyLR implicit $w0
     %copy0:gpr(s32) = COPY $w0
     %copy1:gpr(s32) = COPY $w1
     %three:gpr(s32) = G_CONSTANT i32 3
     %shift:gpr(s32) = G_ASHR %copy0, %three(s32)
     %cmp:gpr(s32) = G_ICMP intpred(ne), %copy1(s32), %shift

 body:             |
   bb.0:
     liveins: $w0, $w1
 
     ; CHECK-LABEL: name: ne_lshr
     ; CHECK: liveins: $w0, $w1
     ; CHECK: %copy0:gpr32 = COPY $w0
     ; CHECK: %copy1:gpr32 = COPY $w1
-    ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 67, implicit-def $nzcv
+    ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 67, implicit-def $nzcv
     ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 0, implicit $nzcv
     ; CHECK: $w0 = COPY %cmp
     ; CHECK: RET_ReallyLR implicit $w0
     %copy0:gpr(s32) = COPY $w0
     %copy1:gpr(s32) = COPY $w1
     %three:gpr(s32) = G_CONSTANT i32 3
     %shift:gpr(s32) = G_LSHR %copy0, %three(s32)
     %cmp:gpr(s32) = G_ICMP intpred(ne), %copy1(s32), %shift

 body:             |
   bb.0:
     liveins: $w0, $w1
 
     ; CHECK-LABEL: name: ult_shl
     ; CHECK: liveins: $w0, $w1
     ; CHECK: %copy0:gpr32 = COPY $w0
     ; CHECK: %copy1:gpr32 = COPY $w1
-    ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 3, implicit-def $nzcv
+    ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 3, implicit-def $nzcv
     ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 2, implicit $nzcv
     ; CHECK: $w0 = COPY %cmp
     ; CHECK: RET_ReallyLR implicit $w0
     %copy0:gpr(s32) = COPY $w0
     %copy1:gpr(s32) = COPY $w1
     %three:gpr(s32) = G_CONSTANT i32 3
     %shift:gpr(s32) = G_SHL %copy0, %three(s32)
     %cmp:gpr(s32) = G_ICMP intpred(ult), %copy1(s32), %shift
     $w0 = COPY %cmp(s32)
     RET_ReallyLR implicit $w0
 ...
 ---
 name:            ult_ashr
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $w0, $w1
 
     ; CHECK-LABEL: name: ult_ashr
     ; CHECK: liveins: $w0, $w1
     ; CHECK: %copy0:gpr32 = COPY $w0
     ; CHECK: %copy1:gpr32 = COPY $w1
-    ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 131, implicit-def $nzcv
+    ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 131, implicit-def $nzcv
     ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 2, implicit $nzcv
     ; CHECK: $w0 = COPY %cmp
     ; CHECK: RET_ReallyLR implicit $w0
     %copy0:gpr(s32) = COPY $w0
     %copy1:gpr(s32) = COPY $w1
     %three:gpr(s32) = G_CONSTANT i32 3
     %shift:gpr(s32) = G_ASHR %copy0, %three(s32)
     %cmp:gpr(s32) = G_ICMP intpred(ult), %copy1(s32), %shift
     $w0 = COPY %cmp(s32)
     RET_ReallyLR implicit $w0
 ...
 ---
 name:            ult_lshr
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $w0, $w1
 
     ; CHECK-LABEL: name: ult_lshr
     ; CHECK: liveins: $w0, $w1
     ; CHECK: %copy0:gpr32 = COPY $w0
     ; CHECK: %copy1:gpr32 = COPY $w1
-    ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 67, implicit-def $nzcv
+    ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 67, implicit-def $nzcv
     ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 2, implicit $nzcv
     ; CHECK: $w0 = COPY %cmp
     ; CHECK: RET_ReallyLR implicit $w0
     %copy0:gpr(s32) = COPY $w0
     %copy1:gpr(s32) = COPY $w1
     %three:gpr(s32) = G_CONSTANT i32 3
     %shift:gpr(s32) = G_LSHR %copy0, %three(s32)
     %cmp:gpr(s32) = G_ICMP intpred(ult), %copy1(s32), %shift
     $w0 = COPY %cmp(s32)
     RET_ReallyLR implicit $w0
 ...
 ---
 name:            ugt_shl
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $w0, $w1
 
     ; CHECK-LABEL: name: ugt_shl
     ; CHECK: liveins: $w0, $w1
     ; CHECK: %copy0:gpr32 = COPY $w0
     ; CHECK: %copy1:gpr32 = COPY $w1
-    ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 3, implicit-def $nzcv
+    ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 3, implicit-def $nzcv
     ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 9, implicit $nzcv
     ; CHECK: $w0 = COPY %cmp
     ; CHECK: RET_ReallyLR implicit $w0
     %copy0:gpr(s32) = COPY $w0
     %copy1:gpr(s32) = COPY $w1
     %three:gpr(s32) = G_CONSTANT i32 3
     %shift:gpr(s32) = G_SHL %copy0, %three(s32)
     %cmp:gpr(s32) = G_ICMP intpred(ugt), %copy1(s32), %shift
     $w0 = COPY %cmp(s32)
     RET_ReallyLR implicit $w0
 ...
 ---
 name:            ugt_ashr
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $w0, $w1
 
     ; CHECK-LABEL: name: ugt_ashr
     ; CHECK: liveins: $w0, $w1
     ; CHECK: %copy0:gpr32 = COPY $w0
     ; CHECK: %copy1:gpr32 = COPY $w1
-    ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 131, implicit-def $nzcv
+    ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 131, implicit-def $nzcv
     ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 9, implicit $nzcv
     ; CHECK: $w0 = COPY %cmp
     ; CHECK: RET_ReallyLR implicit $w0
     %copy0:gpr(s32) = COPY $w0
     %copy1:gpr(s32) = COPY $w1
     %three:gpr(s32) = G_CONSTANT i32 3
     %shift:gpr(s32) = G_ASHR %copy0, %three(s32)
     %cmp:gpr(s32) = G_ICMP intpred(ugt), %copy1(s32), %shift
     $w0 = COPY %cmp(s32)
     RET_ReallyLR implicit $w0
 ...
 ---
 name:            ugt_lshr
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $w0, $w1
 
     ; CHECK-LABEL: name: ugt_lshr
     ; CHECK: liveins: $w0, $w1
     ; CHECK: %copy0:gpr32 = COPY $w0
     ; CHECK: %copy1:gpr32 = COPY $w1
-    ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 67, implicit-def $nzcv
+    ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 67, implicit-def $nzcv
     ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 9, implicit $nzcv
     ; CHECK: $w0 = COPY %cmp
     ; CHECK: RET_ReallyLR implicit $w0
     %copy0:gpr(s32) = COPY $w0
     %copy1:gpr(s32) = COPY $w1
     %three:gpr(s32) = G_CONSTANT i32 3
     %shift:gpr(s32) = G_LSHR %copy0, %three(s32)
     %cmp:gpr(s32) = G_ICMP intpred(ugt), %copy1(s32), %shift

 body:             |
   bb.0:
     liveins: $w0, $w1
 
     ; CHECK-LABEL: name: uge_shl
     ; CHECK: liveins: $w0, $w1
     ; CHECK: %copy0:gpr32 = COPY $w0
     ; CHECK: %copy1:gpr32 = COPY $w1
-    ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 3, implicit-def $nzcv
+    ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 3, implicit-def $nzcv
     ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv
     ; CHECK: $w0 = COPY %cmp
     ; CHECK: RET_ReallyLR implicit $w0
     %copy0:gpr(s32) = COPY $w0
     %copy1:gpr(s32) = COPY $w1
     %three:gpr(s32) = G_CONSTANT i32 3
     %shift:gpr(s32) = G_SHL %copy0, %three(s32)
     %cmp:gpr(s32) = G_ICMP intpred(uge), %copy1(s32), %shift
     $w0 = COPY %cmp(s32)
     RET_ReallyLR implicit $w0
 ...
 ---
 name:            uge_ashr
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $w0, $w1
 
     ; CHECK-LABEL: name: uge_ashr
     ; CHECK: liveins: $w0, $w1
     ; CHECK: %copy0:gpr32 = COPY $w0
     ; CHECK: %copy1:gpr32 = COPY $w1
-    ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 131, implicit-def $nzcv
+    ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 131, implicit-def $nzcv
     ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv
     ; CHECK: $w0 = COPY %cmp
     ; CHECK: RET_ReallyLR implicit $w0
     %copy0:gpr(s32) = COPY $w0
     %copy1:gpr(s32) = COPY $w1
     %three:gpr(s32) = G_CONSTANT i32 3
     %shift:gpr(s32) = G_ASHR %copy0, %three(s32)
     %cmp:gpr(s32) = G_ICMP intpred(uge), %copy1(s32), %shift
     $w0 = COPY %cmp(s32)
     RET_ReallyLR implicit $w0
 ...
 ---
 name:            uge_lshr
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $w0, $w1
 
     ; CHECK-LABEL: name: uge_lshr
     ; CHECK: liveins: $w0, $w1
     ; CHECK: %copy0:gpr32 = COPY $w0
     ; CHECK: %copy1:gpr32 = COPY $w1
-    ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 67, implicit-def $nzcv
+    ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 67, implicit-def $nzcv
     ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv
     ; CHECK: $w0 = COPY %cmp
     ; CHECK: RET_ReallyLR implicit $w0
     %copy0:gpr(s32) = COPY $w0
     %copy1:gpr(s32) = COPY $w1
     %three:gpr(s32) = G_CONSTANT i32 3
     %shift:gpr(s32) = G_LSHR %copy0, %three(s32)
     %cmp:gpr(s32) = G_ICMP intpred(uge), %copy1(s32), %shift

 body:             |
   bb.0:
     liveins: $w0, $w1
 
     ; CHECK-LABEL: name: ule_shl
     ; CHECK: liveins: $w0, $w1
     ; CHECK: %copy0:gpr32 = COPY $w0
     ; CHECK: %copy1:gpr32 = COPY $w1
-    ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 3, implicit-def $nzcv
+    ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 3, implicit-def $nzcv
     ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 8, implicit $nzcv
     ; CHECK: $w0 = COPY %cmp
     ; CHECK: RET_ReallyLR implicit $w0
     %copy0:gpr(s32) = COPY $w0
     %copy1:gpr(s32) = COPY $w1
     %three:gpr(s32) = G_CONSTANT i32 3
     %shift:gpr(s32) = G_SHL %copy0, %three(s32)
     %cmp:gpr(s32) = G_ICMP intpred(ule), %copy1(s32), %shift
     $w0 = COPY %cmp(s32)
     RET_ReallyLR implicit $w0
 ...
 ---
 name:            ule_ashr
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $w0, $w1
 
     ; CHECK-LABEL: name: ule_ashr
     ; CHECK: liveins: $w0, $w1
     ; CHECK: %copy0:gpr32 = COPY $w0
     ; CHECK: %copy1:gpr32 = COPY $w1
-    ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 131, implicit-def $nzcv
+    ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 131, implicit-def $nzcv
     ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 8, implicit $nzcv
     ; CHECK: $w0 = COPY %cmp
     ; CHECK: RET_ReallyLR implicit $w0
     %copy0:gpr(s32) = COPY $w0
     %copy1:gpr(s32) = COPY $w1
     %three:gpr(s32) = G_CONSTANT i32 3
     %shift:gpr(s32) = G_ASHR %copy0, %three(s32)
     %cmp:gpr(s32) = G_ICMP intpred(ule), %copy1(s32), %shift
     $w0 = COPY %cmp(s32)
     RET_ReallyLR implicit $w0
 ...
 ---
 name:            ule_lshr
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $w0, $w1
 
     ; CHECK-LABEL: name: ule_lshr
     ; CHECK: liveins: $w0, $w1
     ; CHECK: %copy0:gpr32 = COPY $w0
     ; CHECK: %copy1:gpr32 = COPY $w1
-    ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 67, implicit-def $nzcv
+    ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 67, implicit-def $nzcv
     ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 8, implicit $nzcv
     ; CHECK: $w0 = COPY %cmp
     ; CHECK: RET_ReallyLR implicit $w0
     %copy0:gpr(s32) = COPY $w0
     %copy1:gpr(s32) = COPY $w1
     %three:gpr(s32) = G_CONSTANT i32 3
     %shift:gpr(s32) = G_LSHR %copy0, %three(s32)
     %cmp:gpr(s32) = G_ICMP intpred(ule), %copy1(s32), %shift

 body:             |
   bb.0:
     liveins: $w0, $w1
 
     ; CHECK-LABEL: name: slt_shl
     ; CHECK: liveins: $w0, $w1
     ; CHECK: %copy0:gpr32 = COPY $w0
     ; CHECK: %copy1:gpr32 = COPY $w1
-    ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 3, implicit-def $nzcv
+    ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 3, implicit-def $nzcv
     ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv
     ; CHECK: $w0 = COPY %cmp
     ; CHECK: RET_ReallyLR implicit $w0
     %copy0:gpr(s32) = COPY $w0
     %copy1:gpr(s32) = COPY $w1
     %three:gpr(s32) = G_CONSTANT i32 3
     %shift:gpr(s32) = G_SHL %copy0, %three(s32)
     %cmp:gpr(s32) = G_ICMP intpred(slt), %copy1(s32), %shift
     $w0 = COPY %cmp(s32)
     RET_ReallyLR implicit $w0
 ...
 ---
 name:            slt_ashr
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $w0, $w1
 
     ; CHECK-LABEL: name: slt_ashr
     ; CHECK: liveins: $w0, $w1
     ; CHECK: %copy0:gpr32 = COPY $w0
     ; CHECK: %copy1:gpr32 = COPY $w1
-    ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 131, implicit-def $nzcv
+    ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 131, implicit-def $nzcv
     ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv
     ; CHECK: $w0 = COPY %cmp
     ; CHECK: RET_ReallyLR implicit $w0
     %copy0:gpr(s32) = COPY $w0
     %copy1:gpr(s32) = COPY $w1
     %three:gpr(s32) = G_CONSTANT i32 3
     %shift:gpr(s32) = G_ASHR %copy0, %three(s32)
     %cmp:gpr(s32) = G_ICMP intpred(slt), %copy1(s32), %shift
     $w0 = COPY %cmp(s32)
     RET_ReallyLR implicit $w0
 ...
 ---
 name:            slt_lshr
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $w0, $w1
 
     ; CHECK-LABEL: name: slt_lshr
     ; CHECK: liveins: $w0, $w1
     ; CHECK: %copy0:gpr32 = COPY $w0
     ; CHECK: %copy1:gpr32 = COPY $w1
-    ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 67, implicit-def $nzcv
+    ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 67, implicit-def $nzcv
     ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv
     ; CHECK: $w0 = COPY %cmp
     ; CHECK: RET_ReallyLR implicit $w0
     %copy0:gpr(s32) = COPY $w0
     %copy1:gpr(s32) = COPY $w1
     %three:gpr(s32) = G_CONSTANT i32 3
     %shift:gpr(s32) = G_LSHR %copy0, %three(s32)
     %cmp:gpr(s32) = G_ICMP intpred(slt), %copy1(s32), %shift
     $w0 = COPY %cmp(s32)
     RET_ReallyLR implicit $w0
 ...
 ---
 name:            sgt_shl
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $w0, $w1
 
     ; CHECK-LABEL: name: sgt_shl
     ; CHECK: liveins: $w0, $w1
     ; CHECK: %copy0:gpr32 = COPY $w0
     ; CHECK: %copy1:gpr32 = COPY $w1
-    ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 3, implicit-def $nzcv
+    ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 3, implicit-def $nzcv
     ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv
     ; CHECK: $w0 = COPY %cmp
     ; CHECK: RET_ReallyLR implicit $w0
     %copy0:gpr(s32) = COPY $w0
     %copy1:gpr(s32) = COPY $w1
     %three:gpr(s32) = G_CONSTANT i32 3
     %shift:gpr(s32) = G_SHL %copy0, %three(s32)
     %cmp:gpr(s32) = G_ICMP intpred(sgt), %copy1(s32), %shift
     $w0 = COPY %cmp(s32)
     RET_ReallyLR implicit $w0
 ...
 ---
 name:            sgt_ashr
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $w0, $w1
 
     ; CHECK-LABEL: name: sgt_ashr
     ; CHECK: liveins: $w0, $w1
     ; CHECK: %copy0:gpr32 = COPY $w0
     ; CHECK: %copy1:gpr32 = COPY $w1
-    ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 131, implicit-def $nzcv
+    ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 131, implicit-def $nzcv
     ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv
     ; CHECK: $w0 = COPY %cmp
     ; CHECK: RET_ReallyLR implicit $w0
     %copy0:gpr(s32) = COPY $w0
     %copy1:gpr(s32) = COPY $w1
     %three:gpr(s32) = G_CONSTANT i32 3
     %shift:gpr(s32) = G_ASHR %copy0, %three(s32)
     %cmp:gpr(s32) = G_ICMP intpred(sgt), %copy1(s32), %shift
     $w0 = COPY %cmp(s32)
     RET_ReallyLR implicit $w0
 ...
 ---
 name:            sgt_lshr
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $w0, $w1
 
     ; CHECK-LABEL: name: sgt_lshr
     ; CHECK: liveins: $w0, $w1
     ; CHECK: %copy0:gpr32 = COPY $w0
     ; CHECK: %copy1:gpr32 = COPY $w1
-    ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 67, implicit-def $nzcv
+    ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 67, implicit-def $nzcv
     ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv
     ; CHECK: $w0 = COPY %cmp
     ; CHECK: RET_ReallyLR implicit $w0
     %copy0:gpr(s32) = COPY $w0
     %copy1:gpr(s32) = COPY $w1
     %three:gpr(s32) = G_CONSTANT i32 3
     %shift:gpr(s32) = G_LSHR %copy0, %three(s32)
     %cmp:gpr(s32) = G_ICMP intpred(sgt), %copy1(s32), %shift
     $w0 = COPY %cmp(s32)
     RET_ReallyLR implicit $w0
 ...
 ---
 name:            sge_shl
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $w0, $w1
 
     ; CHECK-LABEL: name: sge_shl
     ; CHECK: liveins: $w0, $w1
     ; CHECK: %copy0:gpr32 = COPY $w0
     ; CHECK: %copy1:gpr32 = COPY $w1
-    ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 3, implicit-def $nzcv
+    ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 3, implicit-def $nzcv
     ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 11, implicit $nzcv
     ; CHECK: $w0 = COPY %cmp
     ; CHECK: RET_ReallyLR implicit $w0
     %copy0:gpr(s32) = COPY $w0
     %copy1:gpr(s32) = COPY $w1
     %three:gpr(s32) = G_CONSTANT i32 3
     %shift:gpr(s32) = G_SHL %copy0, %three(s32)
     %cmp:gpr(s32) = G_ICMP intpred(sge), %copy1(s32), %shift
     $w0 = COPY %cmp(s32)
     RET_ReallyLR implicit $w0
 ...
 ---
 name:            sge_ashr
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $w0, $w1
 
     ; CHECK-LABEL: name: sge_ashr
     ; CHECK: liveins: $w0, $w1
     ; CHECK: %copy0:gpr32 = COPY $w0
     ; CHECK: %copy1:gpr32 = COPY $w1
-    ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 131, implicit-def $nzcv
+    ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 131, implicit-def $nzcv
     ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 11, implicit $nzcv
     ; CHECK: $w0 = COPY %cmp
     ; CHECK: RET_ReallyLR implicit $w0
     %copy0:gpr(s32) = COPY $w0
     %copy1:gpr(s32) = COPY $w1
     %three:gpr(s32) = G_CONSTANT i32 3
     %shift:gpr(s32) = G_ASHR %copy0, %three(s32)
     %cmp:gpr(s32) = G_ICMP intpred(sge), %copy1(s32), %shift
     $w0 = COPY %cmp(s32)
     RET_ReallyLR implicit $w0
 ...
 ---
 name:            sge_lshr
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $w0, $w1
 
     ; CHECK-LABEL: name: sge_lshr
     ; CHECK: liveins: $w0, $w1
     ; CHECK: %copy0:gpr32 = COPY $w0
     ; CHECK: %copy1:gpr32 = COPY $w1
-    ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 67, implicit-def $nzcv
+    ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 67, implicit-def $nzcv
     ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 11, implicit $nzcv
     ; CHECK: $w0 = COPY %cmp
     ; CHECK: RET_ReallyLR implicit $w0
     %copy0:gpr(s32) = COPY $w0
     %copy1:gpr(s32) = COPY $w1
     %three:gpr(s32) = G_CONSTANT i32 3
     %shift:gpr(s32) = G_LSHR %copy0, %three(s32)
     %cmp:gpr(s32) = G_ICMP intpred(sge), %copy1(s32), %shift

 body:             |
   bb.0:
     liveins: $w0, $w1
 
     ; CHECK-LABEL: name: sle_shl
     ; CHECK: liveins: $w0, $w1
     ; CHECK: %copy0:gpr32 = COPY $w0
     ; CHECK: %copy1:gpr32 = COPY $w1
-    ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 3, implicit-def $nzcv
+    ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 3, implicit-def $nzcv
     ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv
     ; CHECK: $w0 = COPY %cmp
     ; CHECK: RET_ReallyLR implicit $w0
     %copy0:gpr(s32) = COPY $w0
     %copy1:gpr(s32) = COPY $w1
     %three:gpr(s32) = G_CONSTANT i32 3
     %shift:gpr(s32) = G_SHL %copy0, %three(s32)
     %cmp:gpr(s32) = G_ICMP intpred(sle), %copy1(s32), %shift
     $w0 = COPY %cmp(s32)
     RET_ReallyLR implicit $w0
 ...
 ---
 name:            sle_ashr
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $w0, $w1
 
     ; CHECK-LABEL: name: sle_ashr
     ; CHECK: liveins: $w0, $w1
     ; CHECK: %copy0:gpr32 = COPY $w0
     ; CHECK: %copy1:gpr32 = COPY $w1
-    ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 131, implicit-def $nzcv
+    ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 131, implicit-def $nzcv
     ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv
     ; CHECK: $w0 = COPY %cmp
     ; CHECK: RET_ReallyLR implicit $w0
     %copy0:gpr(s32) = COPY $w0
     %copy1:gpr(s32) = COPY $w1
     %three:gpr(s32) = G_CONSTANT i32 3
     %shift:gpr(s32) = G_ASHR %copy0, %three(s32)
     %cmp:gpr(s32) = G_ICMP intpred(sle), %copy1(s32), %shift
     $w0 = COPY %cmp(s32)
     RET_ReallyLR implicit $w0
 ...
 ---
 name:            sle_lshr
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.0:
     liveins: $w0, $w1
 
     ; CHECK-LABEL: name: sle_lshr
     ; CHECK: liveins: $w0, $w1
     ; CHECK: %copy0:gpr32 = COPY $w0
     ; CHECK: %copy1:gpr32 = COPY $w1
-    ; CHECK: $wzr = SUBSWrs %copy1, %copy0, 67, implicit-def $nzcv
+    ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs %copy1, %copy0, 67, implicit-def $nzcv
     ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv
     ; CHECK: $w0 = COPY %cmp
     ; CHECK: RET_ReallyLR implicit $w0
     %copy0:gpr(s32) = COPY $w0
     %copy1:gpr(s32) = COPY $w1
     %three:gpr(s32) = G_CONSTANT i32 3
     %shift:gpr(s32) = G_LSHR %copy0, %three(s32)
     %cmp:gpr(s32) = G_ICMP intpred(sle), %copy1(s32), %shift
     $w0 = COPY %cmp(s32)
     RET_ReallyLR implicit $w0
 ...

llvm/test/CodeGen/AArch64/GlobalISel/preselect-process-phis.mir

body:             |
   ; CHECK:   successors: %bb.1(0x80000000)
   ; CHECK:   [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF
   ; CHECK:   [[DEF1:%[0-9]+]]:gpr64common = IMPLICIT_DEF
   ; CHECK:   [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 2143289344
   ; CHECK:   [[COPY:%[0-9]+]]:fpr32 = COPY [[MOVi32imm]]
   ; CHECK: bb.1:
   ; CHECK:   successors: %bb.2(0x80000000)
   ; CHECK:   [[DEF2:%[0-9]+]]:gpr32 = IMPLICIT_DEF
-  ; CHECK:   $wzr = ANDSWri [[DEF]], 0, implicit-def $nzcv
+  ; CHECK:   [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[DEF]], 0, implicit-def $nzcv
   ; CHECK:   [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[DEF2]], [[DEF2]], 1, implicit $nzcv
   ; CHECK: bb.2:
   ; CHECK:   successors: %bb.2(0x80000000)
   ; CHECK:   [[PHI:%[0-9]+]]:gpr32 = PHI [[CSELWr]], %bb.1, %8, %bb.2
   ; CHECK:   [[FCVTHSr:%[0-9]+]]:fpr16 = FCVTHSr [[COPY]]
   ; CHECK:   [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[FCVTHSr]], %subreg.hsub
   ; CHECK:   [[COPY1:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]]
   ; CHECK:   STRHHui [[PHI]], [[DEF1]], 0 :: (store 2 into `half* undef`)
body:             |
   ; CHECK:   successors: %bb.1(0x80000000)
   ; CHECK:   [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF
   ; CHECK:   [[DEF1:%[0-9]+]]:gpr64common = IMPLICIT_DEF
   ; CHECK:   [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 2143289344
   ; CHECK:   [[COPY:%[0-9]+]]:fpr32 = COPY [[MOVi32imm]]
   ; CHECK: bb.1:
   ; CHECK:   successors: %bb.2(0x80000000)
   ; CHECK:   [[DEF2:%[0-9]+]]:gpr32 = IMPLICIT_DEF
-  ; CHECK:   $wzr = ANDSWri [[DEF]], 0, implicit-def $nzcv
+  ; CHECK:   [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[DEF]], 0, implicit-def $nzcv
   ; CHECK:   [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[DEF2]], [[DEF2]], 1, implicit $nzcv
   ; CHECK:   [[COPY1:%[0-9]+]]:fpr32 = COPY [[CSELWr]]
   ; CHECK:   [[COPY2:%[0-9]+]]:fpr16 = COPY [[COPY1]].hsub
   ; CHECK: bb.2:
   ; CHECK:   successors: %bb.2(0x80000000)
   ; CHECK:   [[PHI:%[0-9]+]]:fpr16 = PHI %7, %bb.2, [[COPY2]], %bb.1
   ; CHECK:   [[FCVTHSr:%[0-9]+]]:fpr16 = FCVTHSr [[COPY]]
   ; CHECK:   STRHui [[PHI]], [[DEF1]], 0 :: (store 2 into `half* undef`)

llvm/test/CodeGen/AArch64/GlobalISel/select-arith-immed-compare.mir

bb.0:
     ; change the condition code.
     ;
     ; log_2(4096) == 12, so we can represent this as a 12 bit value with a
     ; left shift.
 
     ; CHECK-LABEL: name: slt_to_sle_s64
     ; CHECK: liveins: $x0
     ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
-    ; CHECK: $xzr = SUBSXri [[COPY]], 1, 12, implicit-def $nzcv
+    ; CHECK: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[COPY]], 1, 12, implicit-def $nzcv
     ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv
     ; CHECK: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF
     ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gpr64 = INSERT_SUBREG [[DEF]], [[CSINCWr]], %subreg.sub_32
     ; CHECK: [[ANDXri:%[0-9]+]]:gpr64sp = ANDXri [[INSERT_SUBREG]], 4096
     ; CHECK: $x0 = COPY [[ANDXri]]
     ; CHECK: RET_ReallyLR implicit $x0
     %0:gpr(s64) = COPY $x0
     %1:gpr(s64) = G_CONSTANT i64 4097
bb.0:
     ; change the condition code.
     ;
     ; log_2(4096) == 12, so we can represent this as a 12 bit value with a
     ; left shift.
 
     ; CHECK-LABEL: name: sge_to_sgt_s32
     ; CHECK: liveins: $w0
     ; CHECK: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0
-    ; CHECK: $wzr = SUBSWri [[COPY]], 1, 12, implicit-def $nzcv
+    ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 1, 12, implicit-def $nzcv
     ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv
     ; CHECK: [[ANDWri:%[0-9]+]]:gpr32sp = ANDWri [[CSINCWr]], 0
     ; CHECK: $w0 = COPY [[ANDWri]]
     ; CHECK: RET_ReallyLR implicit $w0
     %0:gpr(s32) = COPY $w0
     %1:gpr(s32) = G_CONSTANT i32 4097
     %4:gpr(s32) = G_ICMP intpred(sge), %0(s32), %1
     %5:gpr(s32) = G_CONSTANT i32 1
bb.0:
     ; change the condition code.
     ;
     ; log_2(4096) == 12, so we can represent this as a 12 bit value with a
     ; left shift.
 
     ; CHECK-LABEL: name: sge_to_sgt_s64
     ; CHECK: liveins: $x0
     ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
-    ; CHECK: $xzr = SUBSXri [[COPY]], 1, 12, implicit-def $nzcv
+    ; CHECK: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[COPY]], 1, 12, implicit-def $nzcv
     ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv
     ; CHECK: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF
     ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gpr64 = INSERT_SUBREG [[DEF]], [[CSINCWr]], %subreg.sub_32
     ; CHECK: [[ANDXri:%[0-9]+]]:gpr64sp = ANDXri [[INSERT_SUBREG]], 4096
     ; CHECK: $x0 = COPY [[ANDXri]]
     ; CHECK: RET_ReallyLR implicit $x0
     %0:gpr(s64) = COPY $x0
     %1:gpr(s64) = G_CONSTANT i64 4097
bb.0:
     ; change the condition code.
     ;
     ; log_2(4096) == 12, so we can represent this as a 12 bit value with a
     ; left shift.
 
     ; CHECK-LABEL: name: ult_to_ule_s32
     ; CHECK: liveins: $w0
     ; CHECK: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0
-    ; CHECK: $wzr = SUBSWri [[COPY]], 1, 12, implicit-def $nzcv
+    ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 1, 12, implicit-def $nzcv
     ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 8, implicit $nzcv
     ; CHECK: [[ANDWri:%[0-9]+]]:gpr32sp = ANDWri [[CSINCWr]], 0
     ; CHECK: $w0 = COPY [[ANDWri]]
     ; CHECK: RET_ReallyLR implicit $w0
     %0:gpr(s32) = COPY $w0
     %1:gpr(s32) = G_CONSTANT i32 4097
     %4:gpr(s32) = G_ICMP intpred(ult), %0(s32), %1
     %5:gpr(s32) = G_CONSTANT i32 1
bb.0:
     ; change the condition code.
     ;
     ; log_2(4096) == 12, so we can represent this as a 12 bit value with a
     ; left shift.
 
     ; CHECK-LABEL: name: ult_to_ule_s64
     ; CHECK: liveins: $x0
     ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
-    ; CHECK: $xzr = SUBSXri [[COPY]], 1, 12, implicit-def $nzcv
+    ; CHECK: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[COPY]], 1, 12, implicit-def $nzcv
     ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 8, implicit $nzcv
     ; CHECK: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF
     ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gpr64 = INSERT_SUBREG [[DEF]], [[CSINCWr]], %subreg.sub_32
     ; CHECK: [[ANDXri:%[0-9]+]]:gpr64sp = ANDXri [[INSERT_SUBREG]], 4096
     ; CHECK: $x0 = COPY [[ANDXri]]
     ; CHECK: RET_ReallyLR implicit $x0
     %0:gpr(s64) = COPY $x0
     %1:gpr(s64) = G_CONSTANT i64 4097
bb.0:
     ; change the condition code.
     ;
     ; log_2(4096) == 12, so we can represent this as a 12 bit value with a
     ; left shift.
 
     ; CHECK-LABEL: name: uge_to_ugt_s32
     ; CHECK: liveins: $w0
     ; CHECK: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0
-    ; CHECK: $wzr = SUBSWri [[COPY]], 1, 12, implicit-def $nzcv
+    ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 1, 12, implicit-def $nzcv
     ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 9, implicit $nzcv
     ; CHECK: [[ANDWri:%[0-9]+]]:gpr32sp = ANDWri [[CSINCWr]], 0
     ; CHECK: $w0 = COPY [[ANDWri]]
     ; CHECK: RET_ReallyLR implicit $w0
     %0:gpr(s32) = COPY $w0
     %1:gpr(s32) = G_CONSTANT i32 4097
     %4:gpr(s32) = G_ICMP intpred(uge), %0(s32), %1
     %5:gpr(s32) = G_CONSTANT i32 1
bb.0:
     ; change the condition code.
     ;
     ; log_2(4096) == 12, so we can represent this as a 12 bit value with a
     ; left shift.
 
     ; CHECK-LABEL: name: uge_to_ugt_s64
     ; CHECK: liveins: $x0
     ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
-    ; CHECK: $xzr = SUBSXri [[COPY]], 1, 12, implicit-def $nzcv
+    ; CHECK: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[COPY]], 1, 12, implicit-def $nzcv
     ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 9, implicit $nzcv
     ; CHECK: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF
     ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gpr64 = INSERT_SUBREG [[DEF]], [[CSINCWr]], %subreg.sub_32
     ; CHECK: [[ANDXri:%[0-9]+]]:gpr64sp = ANDXri [[INSERT_SUBREG]], 4096
     ; CHECK: $x0 = COPY [[ANDXri]]
     ; CHECK: RET_ReallyLR implicit $x0
     %0:gpr(s64) = COPY $x0
     %1:gpr(s64) = G_CONSTANT i64 4097
bb.0:
     ; log_2(8192) == 13, so we can represent this as a 12 bit value with a
     ; left shift.
     ;
     ; (We can't use 4095 here, because that's a legal arithmetic immediate.)
 
     ; CHECK-LABEL: name: sle_to_slt_s32
     ; CHECK: liveins: $w0
     ; CHECK: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0
-    ; CHECK: $wzr = SUBSWri [[COPY]], 2, 12, implicit-def $nzcv
+    ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 2, 12, implicit-def $nzcv
     ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv
     ; CHECK: [[ANDWri:%[0-9]+]]:gpr32sp = ANDWri [[CSINCWr]], 0
     ; CHECK: $w0 = COPY [[ANDWri]]
     ; CHECK: RET_ReallyLR implicit $w0
     %0:gpr(s32) = COPY $w0
     %1:gpr(s32) = G_CONSTANT i32 8191
     %4:gpr(s32) = G_ICMP intpred(sle), %0(s32), %1
     %5:gpr(s32) = G_CONSTANT i32 1
bb.0:
     ; the condition code.
     ;
     ; log_2(8192) == 13, so we can represent this as a 12 bit value with a
     ; left shift.
 
     ; CHECK-LABEL: name: sle_to_slt_s64
     ; CHECK: liveins: $x0
     ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
-    ; CHECK: $xzr = SUBSXri [[COPY]], 2, 12, implicit-def $nzcv
+    ; CHECK: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[COPY]], 2, 12, implicit-def $nzcv
     ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv
     ; CHECK: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF
     ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gpr64 = INSERT_SUBREG [[DEF]], [[CSINCWr]], %subreg.sub_32
     ; CHECK: [[ANDXri:%[0-9]+]]:gpr64sp = ANDXri [[INSERT_SUBREG]], 4096
     ; CHECK: $x0 = COPY [[ANDXri]]
     ; CHECK: RET_ReallyLR implicit $x0
     %0:gpr(s64) = COPY $x0
     %1:gpr(s64) = G_CONSTANT i64 8191
bb.0:
     ; the condition code.
     ;
     ; log_2(8192) == 13, so we can represent this as a 12 bit value with a
     ; left shift.
 
     ; CHECK-LABEL: name: sgt_to_sge_s32
     ; CHECK: liveins: $w0
     ; CHECK: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0
-    ; CHECK: $wzr = SUBSWri [[COPY]], 2, 12, implicit-def $nzcv
+    ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 2, 12, implicit-def $nzcv
     ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 11, implicit $nzcv
     ; CHECK: [[ANDWri:%[0-9]+]]:gpr32sp = ANDWri [[CSINCWr]], 0
     ; CHECK: $w0 = COPY [[ANDWri]]
     ; CHECK: RET_ReallyLR implicit $w0
     %0:gpr(s32) = COPY $w0
     %1:gpr(s32) = G_CONSTANT i32 8191
     %4:gpr(s32) = G_ICMP intpred(sgt), %0(s32), %1
     %5:gpr(s32) = G_CONSTANT i32 1
bb.0:
     ; the condition code.
     ;
     ; log_2(8192) == 13, so we can represent this as a 12 bit value with a
     ; left shift.
 
     ; CHECK-LABEL: name: sgt_to_sge_s64
     ; CHECK: liveins: $x0
     ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
-    ; CHECK: $xzr = SUBSXri [[COPY]], 2, 12, implicit-def $nzcv
+    ; CHECK: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[COPY]], 2, 12, implicit-def $nzcv
     ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 11, implicit $nzcv
     ; CHECK: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF
     ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gpr64 = INSERT_SUBREG [[DEF]], [[CSINCWr]], %subreg.sub_32
     ; CHECK: [[ANDXri:%[0-9]+]]:gpr64sp = ANDXri [[INSERT_SUBREG]], 4096
     ; CHECK: $x0 = COPY [[ANDXri]]
     ; CHECK: RET_ReallyLR implicit $x0
     %0:gpr(s64) = COPY $x0
     %1:gpr(s64) = G_CONSTANT i64 8191
bb.0:
     ; does not hold:
     ;
     ; x slt c => x sle c - 1
     ; x sge c => x sgt c - 1
 
     ; CHECK-LABEL: name: no_opt_zero
     ; CHECK: liveins: $x0
     ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
-    ; CHECK: $xzr = SUBSXri [[COPY]], 0, 0, implicit-def $nzcv
+    ; CHECK: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[COPY]], 0, 0, implicit-def $nzcv
     ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 2, implicit $nzcv
     ; CHECK: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF
     ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gpr64 = INSERT_SUBREG [[DEF]], [[CSINCWr]], %subreg.sub_32
     ; CHECK: [[ANDXri:%[0-9]+]]:gpr64sp = ANDXri [[INSERT_SUBREG]], 4096
     ; CHECK: $x0 = COPY [[ANDXri]]
     ; CHECK: RET_ReallyLR implicit $x0
     %0:gpr(s64) = COPY $x0
     %1:gpr(s64) = G_CONSTANT i64 0
bb.0:
     ; They should both be optimized in the same way, so the SUBS produced for
     ; each CSEL should be the same.
 
     ; CHECK-LABEL: name: more_than_one_use_select
     ; CHECK: liveins: $x0, $x1, $x2
     ; CHECK: %a:gpr64common = COPY $x0
     ; CHECK: %b:gpr64 = COPY $x1
     ; CHECK: %c:gpr64 = COPY $x2
-    ; CHECK: $xzr = SUBSXri %a, 0, 0, implicit-def $nzcv
+    ; CHECK: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri %a, 0, 0, implicit-def $nzcv
     ; CHECK: %select1:gpr64 = CSELXr %a, %b, 11, implicit $nzcv
-    ; CHECK: $xzr = SUBSXri %a, 0, 0, implicit-def $nzcv
+    ; CHECK: [[SUBSXri1:%[0-9]+]]:gpr64 = SUBSXri %a, 0, 0, implicit-def $nzcv
     ; CHECK: %select2:gpr64 = CSELXr %b, %c, 11, implicit $nzcv
     ; CHECK: %add:gpr64 = ADDXrr %select1, %select2
     ; CHECK: $x0 = COPY %add
     ; CHECK: RET_ReallyLR implicit $x0
     %a:gpr(s64) = COPY $x0
     %b:gpr(s64) = COPY $x1
     %c:gpr(s64) = COPY $x2
     %cst:gpr(s64) = G_CONSTANT i64 -1

llvm/test/CodeGen/AArch64/GlobalISel/select-cbz.mir

 tracksRegLiveness: true
 body:             |
   ; CHECK-LABEL: name: test_rhs_unknown
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; CHECK:   liveins: $x0
   ; CHECK:   [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
   ; CHECK:   [[LDRXui:%[0-9]+]]:gpr64common = LDRXui [[COPY]], 0 :: (load 8)
-  ; CHECK:   $xzr = SUBSXri [[LDRXui]], 42, 0, implicit-def $nzcv
+  ; CHECK:   [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[LDRXui]], 42, 0, implicit-def $nzcv
   ; CHECK:   Bcc 0, %bb.2, implicit $nzcv
   ; CHECK: bb.1:
   ; CHECK:   successors: %bb.2(0x80000000)
   ; CHECK:   STRXui $xzr, [[COPY]], 0 :: (store 8)
   ; CHECK: bb.2:
   ; CHECK:   RET_ReallyLR
   bb.1:
     successors: %bb.2, %bb.3

 
 ...
 ---
 name:            update_pred_minus_one
 legalized:       true
 regBankSelected: true
 
 body:             |
-  ; The G_ICMP here will be optimized into a slt against 0.
-  ; The branch should inherit this change, so we should have Bcc 11 rather than
-  ; Bcc 13.
-
   ; CHECK-LABEL: name: update_pred_minus_one
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.0(0x40000000), %bb.1(0x40000000)
   ; CHECK:   [[COPY:%[0-9]+]]:gpr32sp = COPY $w0
-  ; CHECK:   $wzr = SUBSWri [[COPY]], 0, 0, implicit-def $nzcv
+  ; CHECK:   [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 0, 0, implicit-def $nzcv
   ; CHECK:   Bcc 11, %bb.1, implicit $nzcv
   ; CHECK:   B %bb.0
   ; CHECK: bb.1:
+  ; The G_ICMP here will be optimized into a slt against 0.
+  ; The branch should inherit this change, so we should have Bcc 11 rather than
+  ; Bcc 13.
+
   bb.0:
     liveins: $w0
     successors: %bb.0, %bb.1
 
     %0:gpr(s32) = COPY $w0
     %1:gpr(s32) = G_CONSTANT i32 -1
     %2:gpr(s32) = G_ICMP intpred(sle), %0, %1
     %3:gpr(s1) = G_TRUNC %2(s32)
     G_BRCOND %3(s1), %bb.1
     G_BR %bb.0
 
   bb.1:
 ...

llvm/test/CodeGen/AArch64/GlobalISel/select-cmp.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
 ---
 name:            cmp_imm_32
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.1:
     liveins: $w0
 
     ; CHECK-LABEL: name: cmp_imm_32
     ; CHECK: liveins: $w0
     ; CHECK: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0
-    ; CHECK: $wzr = SUBSWri [[COPY]], 42, 0, implicit-def $nzcv
+    ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 42, 0, implicit-def $nzcv
     ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
     ; CHECK: $w0 = COPY [[CSINCWr]]
     ; CHECK: RET_ReallyLR implicit $w0
     %0:gpr(s32) = COPY $w0
     %1:gpr(s32) = G_CONSTANT i32 42
     %5:gpr(s32) = G_ICMP intpred(eq), %0(s32), %1
     $w0 = COPY %5(s32)
     RET_ReallyLR implicit $w0
 
 ...
 ---
 name:            cmp_imm_64
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.1:
     liveins: $x0
 
     ; CHECK-LABEL: name: cmp_imm_64
     ; CHECK: liveins: $x0
     ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
-    ; CHECK: $xzr = SUBSXri [[COPY]], 42, 0, implicit-def $nzcv
+    ; CHECK: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[COPY]], 42, 0, implicit-def $nzcv
     ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
     ; CHECK: $w0 = COPY [[CSINCWr]]
     ; CHECK: RET_ReallyLR implicit $w0
     %0:gpr(s64) = COPY $x0
     %1:gpr(s64) = G_CONSTANT i64 42
     %5:gpr(s32) = G_ICMP intpred(eq), %0(s64), %1
     $w0 = COPY %5(s32)
     RET_ReallyLR implicit $w0

 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.1:
     liveins: $w0
     ; CHECK-LABEL: name: cmp_imm_lookthrough
     ; CHECK: liveins: $w0
     ; CHECK: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0
-    ; CHECK: $wzr = SUBSWri [[COPY]], 42, 0, implicit-def $nzcv
+    ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 42, 0, implicit-def $nzcv
     ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
     ; CHECK: $w0 = COPY [[CSINCWr]]
     ; CHECK: RET_ReallyLR implicit $w0
     %0:gpr(s32) = COPY $w0
     %1:gpr(s64) = G_CONSTANT i64 42
     %2:gpr(s32) = G_TRUNC %1(s64)
     %5:gpr(s32) = G_ICMP intpred(eq), %0(s32), %2
     $w0 = COPY %5(s32)
     RET_ReallyLR implicit $w0
 
 ...
 ---
 name:            cmp_imm_lookthrough_bad_trunc
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.1:
     liveins: $w0
     ; CHECK-LABEL: name: cmp_imm_lookthrough_bad_trunc
     ; CHECK: liveins: $w0
     ; CHECK: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0
-    ; CHECK: $wzr = SUBSWri [[COPY]], 0, 0, implicit-def $nzcv
+    ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 0, 0, implicit-def $nzcv
     ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
     ; CHECK: $w0 = COPY [[CSINCWr]]
     ; CHECK: RET_ReallyLR implicit $w0
     %0:gpr(s32) = COPY $w0
     %1:gpr(s64) = G_CONSTANT i64 68719476736 ; 0x1000000000
     %2:gpr(s32) = G_TRUNC %1(s64) ; Value truncates to 0
     %5:gpr(s32) = G_ICMP intpred(eq), %0(s32), %2
     $w0 = COPY %5(s32)
     RET_ReallyLR implicit $w0

llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt-constrain.mir

- id:              0
       blocks:          [ '%bb.4' ]
 body:             |
   ; CHECK-LABEL: name: check_constrain
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; CHECK:   [[DEF:%[0-9]+]]:gpr64common = IMPLICIT_DEF
   ; CHECK:   [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[DEF]], 0 :: (load 1)
   ; CHECK:   [[SUBREG_TO_REG:%[0-9]+]]:gpr64common = SUBREG_TO_REG 0, [[LDRBBui]], %subreg.sub_32
-  ; CHECK:   $xzr = SUBSXri [[SUBREG_TO_REG]], 8, 0, implicit-def $nzcv
+  ; CHECK:   [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[SUBREG_TO_REG]], 8, 0, implicit-def $nzcv
   ; CHECK:   Bcc 8, %bb.3, implicit $nzcv
   ; CHECK: bb.1:
   ; CHECK:   successors: %bb.2(0x40000000), %bb.3(0x40000000)
   ; CHECK:   [[MOVaddrJT:%[0-9]+]]:gpr64 = MOVaddrJT target-flags(aarch64-page) %jump-table.0, target-flags(aarch64-pageoff, aarch64-nc) %jump-table.0
   ; CHECK:   early-clobber %6:gpr64, early-clobber %7:gpr64sp = JumpTableDest32 [[MOVaddrJT]], [[SUBREG_TO_REG]], %jump-table.0
   ; CHECK:   BR %6
   ; CHECK: bb.2:
   ; CHECK:   successors: %bb.3(0x80000000)
+  ; CHECK:   B %bb.3
   ; CHECK: bb.3:
   ; CHECK:   RET_ReallyLR
   bb.1:
     %1:gpr(p0) = G_IMPLICIT_DEF
     %5:gpr(s64) = G_ZEXTLOAD %1(p0) :: (load 1)
     %7:gpr(s64) = G_CONSTANT i64 8
     %16:gpr(s32) = G_ICMP intpred(ugt), %5(s64), %7
     %8:gpr(s1) = G_TRUNC %16(s32)

llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir

body:             |
   ; CHECK-LABEL: name: jt_test
   ; CHECK: bb.0.entry:
   ; CHECK:   successors: %bb.4(0x40000000), %bb.1(0x40000000)
   ; CHECK:   liveins: $w0
   ; CHECK:   [[COPY:%[0-9]+]]:gpr32common = COPY $w0
   ; CHECK:   [[COPY1:%[0-9]+]]:gpr32 = COPY $wzr
   ; CHECK:   [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 4, 0, implicit-def $nzcv
   ; CHECK:   [[SUBREG_TO_REG:%[0-9]+]]:gpr64common = SUBREG_TO_REG 0, [[SUBSWri]], %subreg.sub_32
-  ; CHECK:   $xzr = SUBSXri [[SUBREG_TO_REG]], 71, 0, implicit-def $nzcv
+  ; CHECK:   [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[SUBREG_TO_REG]], 71, 0, implicit-def $nzcv
   ; CHECK:   Bcc 8, %bb.4, implicit $nzcv
   ; CHECK: bb.1.entry:
   ; CHECK:   successors: %bb.3(0x2aaaaaab), %bb.4(0x2aaaaaab), %bb.2(0x2aaaaaab)
   ; CHECK:   [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr
   ; CHECK:   [[MOVaddrJT:%[0-9]+]]:gpr64 = MOVaddrJT target-flags(aarch64-page) %jump-table.0, target-flags(aarch64-pageoff, aarch64-nc) %jump-table.0
   ; CHECK:   early-clobber %18:gpr64, early-clobber %19:gpr64sp = JumpTableDest32 [[MOVaddrJT]], [[SUBREG_TO_REG]], %jump-table.0
   ; CHECK:   BR %18
   ; CHECK: bb.2.sw.bb:

llvm/test/CodeGen/AArch64/GlobalISel/select-select.mir

bb.0:
 
     ; CHECK-LABEL: name: select_f32
     ; CHECK: liveins: $s0, $s1, $w0
     ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
     ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0
     ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s1
     ; CHECK: [[COPY3:%[0-9]+]]:fpr32 = COPY [[COPY]]
     ; CHECK: [[COPY4:%[0-9]+]]:gpr32 = COPY [[COPY3]]
-    ; CHECK: $wzr = ANDSWri [[COPY4]], 0, implicit-def $nzcv
+    ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY4]], 0, implicit-def $nzcv
     ; CHECK: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[COPY1]], [[COPY2]], 1, implicit $nzcv
     ; CHECK: $s0 = COPY [[FCSELSrrr]]
     ; CHECK: RET_ReallyLR implicit $s0
     %3:gpr(s32) = COPY $w0
     %0:gpr(s1) = G_TRUNC %3(s32)
     %1:fpr(s32) = COPY $s0
     %2:fpr(s32) = COPY $s1
     %5:fpr(s1) = COPY %0(s1)
bb.0:
 
     ; CHECK-LABEL: name: select_f64
     ; CHECK: liveins: $d0, $d1, $w0
     ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
     ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
     ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d1
     ; CHECK: [[COPY3:%[0-9]+]]:fpr32 = COPY [[COPY]]
     ; CHECK: [[COPY4:%[0-9]+]]:gpr32 = COPY [[COPY3]]
-    ; CHECK: $wzr = ANDSWri [[COPY4]], 0, implicit-def $nzcv
+    ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY4]], 0, implicit-def $nzcv
     ; CHECK: [[FCSELDrrr:%[0-9]+]]:fpr64 = FCSELDrrr [[COPY1]], [[COPY2]], 1, implicit $nzcv
     ; CHECK: $d0 = COPY [[FCSELDrrr]]
     ; CHECK: RET_ReallyLR implicit $d0
     %3:gpr(s32) = COPY $w0
     %0:gpr(s1) = G_TRUNC %3(s32)
     %1:fpr(s64) = COPY $d0
     %2:fpr(s64) = COPY $d1
     %5:fpr(s1) = COPY %0(s1)
     %4:fpr(s64) = G_SELECT %5(s1), %1, %2
     $d0 = COPY %4(s64)
     RET_ReallyLR implicit $d0

llvm/test/CodeGen/AArch64/GlobalISel/select.mir

registers:
   - { id: 4, class: gpr }
   - { id: 5, class: gpr }
   - { id: 6, class: gpr }
   - { id: 7, class: gpr }
   - { id: 8, class: gpr }
   - { id: 9, class: gpr }
 
 # CHECK:  body:
-# CHECK:      $wzr = ANDSWri %10, 0, implicit-def $nzcv
+# CHECK:      ANDSWri %10, 0, implicit-def $nzcv
 # CHECK:      %3:gpr32 = CSELWr %1, %2, 1, implicit $nzcv
-# CHECK:      $wzr = ANDSWri %10, 0, implicit-def $nzcv
+# CHECK:      ANDSWri %10, 0, implicit-def $nzcv
 # CHECK:      %6:gpr64 = CSELXr %4, %5, 1, implicit $nzcv
-# CHECK:      $wzr = ANDSWri %10, 0, implicit-def $nzcv
+# CHECK:      ANDSWri %10, 0, implicit-def $nzcv
 # CHECK:      %9:gpr64 = CSELXr %7, %8, 1, implicit $nzcv
 body:             |
   bb.0:
     liveins: $w0, $w1, $w2
     %10:gpr(s32) = COPY $w0
     %0(s1) = G_TRUNC %10
 
     %1(s32) = COPY $w1

llvm/test/CodeGen/AArch64/GlobalISel/tbnz-slt.mir

 alignment:       4
 legalized:       true
 regBankSelected: true
 body:             |
   ; CHECK-LABEL: name: no_tbnz_not_zero
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.0(0x40000000), %bb.1(0x40000000)
   ; CHECK:   %copy:gpr32sp = COPY $w0
-  ; CHECK:   $wzr = SUBSWri %copy, 1, 0, implicit-def $nzcv
+  ; CHECK:   [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri %copy, 1, 0, implicit-def $nzcv
   ; CHECK:   Bcc 11, %bb.1, implicit $nzcv
   ; CHECK:   B %bb.0
   ; CHECK: bb.1:
   ; CHECK:   RET_ReallyLR
   bb.0:
     successors: %bb.0, %bb.1
     liveins: $x0
     %copy:gpr(s32) = COPY $w0

 alignment:       4
 legalized:       true
 regBankSelected: true
 body:             |
   ; CHECK-LABEL: name: dont_fold_and
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.0(0x40000000), %bb.1(0x40000000)
   ; CHECK:   %copy:gpr64 = COPY $x0
-  ; CHECK:   $xzr = ANDSXri %copy, 8000, implicit-def $nzcv
+  ; CHECK:   [[ANDSXri:%[0-9]+]]:gpr64 = ANDSXri %copy, 8000, implicit-def $nzcv
   ; CHECK:   %cmp:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv
   ; CHECK:   TBNZW %cmp, 0, %bb.1
   ; CHECK:   B %bb.0
   ; CHECK: bb.1:
   ; CHECK:   RET_ReallyLR
   bb.0:
     successors: %bb.0, %bb.1
     liveins: $x0

llvm/test/CodeGen/AArch64/GlobalISel/tbz-sgt.mir

 alignment:       4
 legalized:       true
 regBankSelected: true
 body:             |
   ; CHECK-LABEL: name: no_tbz_not_negative_one
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.0(0x40000000), %bb.1(0x40000000)
   ; CHECK:   %copy:gpr32sp = COPY $w0
-  ; CHECK:   $wzr = SUBSWri %copy, 1, 0, implicit-def $nzcv
+  ; CHECK:   [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri %copy, 1, 0, implicit-def $nzcv
   ; CHECK:   Bcc 12, %bb.1, implicit $nzcv
   ; CHECK:   B %bb.0
   ; CHECK: bb.1:
   ; CHECK:   RET_ReallyLR
   bb.0:
     successors: %bb.0, %bb.1
     liveins: $x0
     %copy:gpr(s32) = COPY $w0

 legalized:       true
 regBankSelected: true
 body:             |
   ; CHECK-LABEL: name: dont_fold_and
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.0(0x40000000), %bb.1(0x40000000)
   ; CHECK:   %copy:gpr64 = COPY $x0
   ; CHECK:   %and:gpr64sp = ANDXri %copy, 8000
-  ; CHECK:   $xzr = SUBSXri %and, 0, 0, implicit-def $nzcv
+  ; CHECK:   [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri %and, 0, 0, implicit-def $nzcv
   ; CHECK:   Bcc 10, %bb.1, implicit $nzcv
   ; CHECK:   B %bb.0
   ; CHECK: bb.1:
   ; CHECK:   RET_ReallyLR
   bb.0:
     successors: %bb.0, %bb.1
     liveins: $x0
     %copy:gpr(s64) = COPY $x0