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Differential D89405

[CodeGen][X86] Emit fshl/fshr ir intrinsics for shiftleft128/shiftright128 ms intrinsics
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Authored by RKSimon on Oct 14 2020, 9:59 AM.

Details

Reviewers
craig.topper
spatel
rnk
thakis
Commits
rGd7fa9030d47f: [CodeGen][X86] Emit fshl/fshr ir intrinsics for shiftleft128/shiftright128 ms…
Summary

Now that funnel shift handling is pretty good, we can use the intrinsics directly and avoid a lot of zext/trunc issues.

https://godbolt.org/z/YqhnnM

Diff Detail

Event Timeline

RKSimon created this revision.Oct 14 2020, 9:59 AM
Herald added a project: Restricted Project. · View Herald TranscriptOct 14 2020, 9:59 AM
Herald added a subscriber: pengfei. · View Herald Transcript
RKSimon requested review of this revision.Oct 14 2020, 9:59 AM
Harbormaster completed remote builds in B75085: Diff 298172.Oct 14 2020, 11:01 AM
craig.topper accepted this revision.Oct 14 2020, 11:58 PM

LGTM

This revision is now accepted and ready to land.Oct 14 2020, 11:58 PM
Closed by commit rGd7fa9030d47f: [CodeGen][X86] Emit fshl/fshr ir intrinsics for shiftleft128/shiftright128 ms… (authored by RKSimon). · Explain WhyOct 15 2020, 2:23 AM
This revision was automatically updated to reflect the committed changes.
RKSimon added a commit: rGd7fa9030d47f: [CodeGen][X86] Emit fshl/fshr ir intrinsics for shiftleft128/shiftright128 ms….

Revision Contents

PathSize
clang/
lib/
CodeGen/
28 lines
test/
CodeGen/
X86/
19 lines

Diff 298172

clang/lib/CodeGen/CGBuiltin.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
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} }
case X86::BI__faststorefence: { case X86::BI__faststorefence: {
return Builder.CreateFence(llvm::AtomicOrdering::SequentiallyConsistent, return Builder.CreateFence(llvm::AtomicOrdering::SequentiallyConsistent,
llvm::SyncScope::System); llvm::SyncScope::System);
} }
case X86::BI__shiftleft128: case X86::BI__shiftleft128:
case X86::BI__shiftright128: { case X86::BI__shiftright128: {
// FIXME: Once fshl/fshr no longer add an unneeded and and cmov, do this: llvm::Function *F = CGM.getIntrinsic(
// llvm::Function *F = CGM.getIntrinsic( BuiltinID == X86::BI__shiftleft128 ? Intrinsic::fshl : Intrinsic::fshr,
// BuiltinID == X86::BI__shiftleft128 ? Intrinsic::fshl : Intrinsic::fshr, Int64Ty);
// Int64Ty); // Flip low/high ops and zero-extend amount to matching type.
// Ops[2] = Builder.CreateZExt(Ops[2], Int64Ty); // shiftleft128(Low, High, Amt) -> fshl(High, Low, Amt)
// return Builder.CreateCall(F, Ops); // shiftright128(Low, High, Amt) -> fshr(High, Low, Amt)
llvm::Type *Int128Ty = Builder.getInt128Ty(); std::swap(Ops[0], Ops[1]);
Value *HighPart128 = Ops[2] = Builder.CreateZExt(Ops[2], Int64Ty);
Builder.CreateShl(Builder.CreateZExt(Ops[1], Int128Ty), 64); return Builder.CreateCall(F, Ops);
Value *LowPart128 = Builder.CreateZExt(Ops[0], Int128Ty);
Value *Val = Builder.CreateOr(HighPart128, LowPart128);
Value *Amt = Builder.CreateAnd(Builder.CreateZExt(Ops[2], Int128Ty),
llvm::ConstantInt::get(Int128Ty, 0x3f));
Value *Res;
if (BuiltinID == X86::BI__shiftleft128)
Res = Builder.CreateLShr(Builder.CreateShl(Val, Amt), 64);
else
Res = Builder.CreateLShr(Val, Amt);
return Builder.CreateTrunc(Res, Int64Ty);
} }
case X86::BI_ReadWriteBarrier: case X86::BI_ReadWriteBarrier:
case X86::BI_ReadBarrier: case X86::BI_ReadBarrier:
case X86::BI_WriteBarrier: { case X86::BI_WriteBarrier: {
return Builder.CreateFence(llvm::AtomicOrdering::SequentiallyConsistent, return Builder.CreateFence(llvm::AtomicOrdering::SequentiallyConsistent,
llvm::SyncScope::SingleThread); llvm::SyncScope::SingleThread);
} }
case X86::BI_BitScanForward: case X86::BI_BitScanForward:
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clang/test/CodeGen/X86/ms-x86-intrinsics.c

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// CHECK-X64: store i64 % // CHECK-X64: store i64 %
// CHECK-X64: ret i64 % // CHECK-X64: ret i64 %
unsigned __int64 test__shiftleft128(unsigned __int64 l, unsigned __int64 h, unsigned __int64 test__shiftleft128(unsigned __int64 l, unsigned __int64 h,
unsigned char d) { unsigned char d) {
return __shiftleft128(l, h, d); return __shiftleft128(l, h, d);
} }
// CHECK-X64-LABEL: define dso_local i64 @test__shiftleft128(i64 %l, i64 %h, i8 %d) // CHECK-X64-LABEL: define dso_local i64 @test__shiftleft128(i64 %l, i64 %h, i8 %d)
// CHECK-X64: = zext i64 %{{.*}} to i128 // CHECK-X64: = zext i8 %{{.*}} to i64
// CHECK-X64: = shl nuw i128 %{{.*}}, 64 // CHECK-X64: = tail call i64 @llvm.fshl.i64(i64 %h, i64 %l, i64 %{{.*}})
// CHECK-X64: = zext i64 %{{.*}} to i128
// CHECK-X64: = or i128 %
// CHECK-X64: = and i8 %{{.*}}, 63
// CHECK-X64: = shl i128 %
// CHECK-X64: = lshr i128 %
// CHECK-X64: = trunc i128 %
// CHECK-X64: ret i64 % // CHECK-X64: ret i64 %
unsigned __int64 test__shiftright128(unsigned __int64 l, unsigned __int64 h, unsigned __int64 test__shiftright128(unsigned __int64 l, unsigned __int64 h,
unsigned char d) { unsigned char d) {
return __shiftright128(l, h, d); return __shiftright128(l, h, d);
} }
// CHECK-X64-LABEL: define dso_local i64 @test__shiftright128(i64 %l, i64 %h, i8 %d) // CHECK-X64-LABEL: define dso_local i64 @test__shiftright128(i64 %l, i64 %h, i8 %d)
// CHECK-X64: = zext i64 %{{.*}} to i128 // CHECK-X64: = zext i8 %{{.*}} to i64
// CHECK-X64: = shl nuw i128 %{{.*}}, 64 // CHECK-X64: = tail call i64 @llvm.fshr.i64(i64 %h, i64 %l, i64 %{{.*}})
// CHECK-X64: = zext i64 %{{.*}} to i128
// CHECK-X64: = or i128 %
// CHECK-X64: = and i8 %{{.*}}, 63
// CHECK-X64: = lshr i128 %
// CHECK-X64: = trunc i128 %
// CHECK-X64: ret i64 % // CHECK-X64: ret i64 %
#endif // defined(__x86_64__) #endif // defined(__x86_64__)