[ARM] Fix pointer offset when splitting stores from VMOVDRR

[dmgreen]

Summary

We were not accounting for the pointer offset when splitting a load from a VMOVDRR node, which could lead to incorrect aliasing info. In this case it is the fneg via integer arithmetic that gives us a store->load pair that we started getting wrong.

[efriedma]

llvm/lib/Target/ARM/ARMISelLowering.cpp

14556–14557

While you're here, fix this to use St->getOriginalAlign() instead of trying to mess with the computed alignment?

[dmgreen]

Now using getOriginalAlignment

[efriedma]

LGTM

llvm/lib/Target/ARM/ARMISelLowering.cpp

static SDValue PerformSTORECombine(SDNode *N,
   if (StVal.getNode()->getOpcode() == ARMISD::VMOVDRR &&
       StVal.getNode()->hasOneUse()) {
     SelectionDAG  &DAG = DCI.DAG;
     bool isBigEndian = DAG.getDataLayout().isBigEndian();
     SDLoc DL(St);
     SDValue BasePtr = St->getBasePtr();
     SDValue NewST1 = DAG.getStore(
         St->getChain(), DL, StVal.getNode()->getOperand(isBigEndian ? 1 : 0),
-        BasePtr, St->getPointerInfo(), St->getAlignment(),
+        BasePtr, St->getPointerInfo(), St->getOriginalAlign(),
         St->getMemOperand()->getFlags());
 
     SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
                                     DAG.getConstant(4, DL, MVT::i32));
     return DAG.getStore(NewST1.getValue(0), DL,
                         StVal.getNode()->getOperand(isBigEndian ? 0 : 1),
-                        OffsetPtr, St->getPointerInfo(),
-                        std::min(4U, St->getAlignment() / 2),
+                        OffsetPtr, St->getPointerInfo().getWithOffset(4),
+                        St->getOriginalAlign(),
                         St->getMemOperand()->getFlags());
   }
 
   if (StVal.getValueType() == MVT::i64 &&
       StVal.getNode()->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
 
     // Bitcast an i64 store extracted from a vector to f64.
     // Otherwise, the i64 value will be legalized to a pair of i32 values.

llvm/test/CodeGen/Thumb2/vmovdrroffset.ll

 ; CHECK-NEXT:    vmov.f32 s16, s2
 ; CHECK-NEXT:    vmov.f32 s18, s0
 ; CHECK-NEXT:    vmov.f32 s17, s3
 ; CHECK-NEXT:    vmov.f32 s19, s1
 ; CHECK-NEXT:    bl sqrt
 ; CHECK-NEXT:    vmov r2, r3, d8
 ; CHECK-NEXT:    vmov r0, r1, d0
 ; CHECK-NEXT:    bl __aeabi_dadd
+; CHECK-NEXT:    str r1, [sp, #4]
 ; CHECK-NEXT:    mov r4, r0
 ; CHECK-NEXT:    ldrb.w r0, [sp, #7]
-; CHECK-NEXT:    str r1, [sp, #4]
 ; CHECK-NEXT:    eor r0, r0, #128
 ; CHECK-NEXT:    strb.w r0, [sp, #7]
 ; CHECK-NEXT:    vmov r0, r1, d9
 ; CHECK-NEXT:    mov r2, r0
 ; CHECK-NEXT:    mov r3, r1
 ; CHECK-NEXT:    bl __aeabi_dadd
 ; CHECK-NEXT:    mov r3, r1
 ; CHECK-NEXT:    ldr r1, [sp, #4]