[InstCombine] Fix pr47668

[aqjune]

Summary

This patch fixes pr47668 (https://llvm.org/pr47668) by checking whether the shift amount is smaller than the bitwidth of variables.

This is done by checking whether Z is a constant and it is smaller than the bitwidth.

When the shift amount is undef, it is unsafe in theory because 1 << undef is poison, causing the miscompilation happen again.
To prevent this, I made the undef simply fold into zero, since shl 0 can be optimized later.

Proof to the first and second changes:
https://alive2.llvm.org/ce/z/CVBwu9 , https://alive2.llvm.org/ce/z/h2ZWoW

The changes in f_var2* and f_var3* are checking whether src and tgt are identical, so proof not needed

[lebedev.ri]

This is missing alive link.
I think the fix is wrong, based solely on the fact that it is huge.
I would think the fix should be:

• if the shift amount is a variable, check that it is not undef
• if it is a constant, sanitize undef elts to 0

Am i wrong?

[aqjune]

Hi, I'm back!

The complexity comes from dealing with the case when the input is a vector.
It iterates over the elements of a vector and puts the undef-eliminated result into ZWithoutUndef.

[lebedev.ri]

In D88432#2304707, @aqjune wrote:

Hi, I'm back!

The complexity comes from dealing with the case when the input is a vector.
It iterates over the elements of a vector and puts the undef-eliminated result into ZWithoutUndef.

Please do reply to the question i asked, not re-explain the code.

[aqjune]

Soothe clang-format warning

[aqjune]

In D88432#2298717, @lebedev.ri wrote:

• if the shift amount is a variable, check that it is not undef
• if it is a constant, sanitize undef elts to 0

In the first case, the variable should be checked to be less than the bitwidth as well, which is slightly expensive so not contained in this patch.

The second case is what this change contains. Additionally, it had to check whether the value was less than the bitwidth, which made the code slightly longer.

[aqjune]

Did my explanation make sense?
The message was that it was needed to check the shift bitwidth as well, which slightly made the code longer.

[aqjune]

Just found that this old patch is still open - I'd like to revisit this later since freeze can be used to resurrect this transformation. This will require investigation into the impact of freeze.

llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp

 //===- InstCombineSelect.cpp ----------------------------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
if (!(Cmp->hasOneUse() && Cmp->getOperand(0)->hasOneUse() &&
     return nullptr;
 
   // The TrueVal has general form of:  and %B, 1
   Value *B;
   if (!match(TVal, m_OneUse(m_And(m_Value(B), m_One()))))
     return nullptr;
 
   // Where %B may be optionally shifted:  lshr %X, %Z.
-  Value *X, *Z;
-  const bool HasShift = match(B, m_OneUse(m_LShr(m_Value(X), m_Value(Z))));
+  Value *X;
+  Constant *Z;
+  bool HasShift = match(B, m_OneUse(m_LShr(m_Value(X), m_Constant(Z))));
+
+  // Check that Z is smaller than bitwidth.
+  // If it isn't, set HasShift to false.
+  if (HasShift) {
+    if (auto *CI = dyn_cast<ConstantInt>(Z)) {
+      HasShift &= CI->getValue().ult(X->getType()->getIntegerBitWidth());
+    } else if (isa<UndefValue>(Z)) {
+      // Simply fold Z to zero.
+      // Otherwise, MaskB (which is 1 << Z) becomes poison because Z is undef.
+      Z = ConstantInt::getNullValue(Z->getType());
+    } else if (auto *VTy = dyn_cast<FixedVectorType>(Z->getType())) {
+      unsigned BW = VTy->getElementType()->getIntegerBitWidth();
+      SmallVector<Constant *, 4> ZWithoutUndef;
+
+      for (unsigned i = 0; i < VTy->getNumElements(); ++i) {
+        Constant *Elem = Z->getAggregateElement(i);
+        if (isa<UndefValue>(Elem)) {
+          ZWithoutUndef.push_back(ConstantInt::get(Elem->getType(), 0));
+          continue;
+        }
+
+        auto *CI = dyn_cast<ConstantInt>(Elem);
+        if (!CI) {
+          HasShift = false;
+          break;
+        }
+        if (CI->getValue().uge(BW)) {
+          HasShift = false;
+          break;
+        }
+        ZWithoutUndef.push_back(CI);
+      }
+      if (HasShift)
+        Z = ConstantVector::get(ZWithoutUndef);
+
+    } else {
+      HasShift = false;
+    }
+  }
   if (!HasShift)
     X = B;
 
   Value *Y;
   if (!match(Cmp->getOperand(0), m_c_And(m_Specific(X), m_Value(Y))))
     return nullptr;
 
   // ((X & Y) == 0) ? ((X >> Z) & 1) : 1 --> (X & (Y | (1 << Z))) != 0

llvm/test/Transforms/InstCombine/select-of-bittest.ll

;
   %tmp2 = lshr <2 x i32> %arg, <i32 2, i32 1> ; shift is not splat
   %tmp3 = and <2 x i32> %tmp2, <i32 1, i32 1>
   %tmp4 = select <2 x i1> %tmp1, <2 x i32> %tmp3, <2 x i32> <i32 1, i32 1>
   ret <2 x i32> %tmp4
 }
 
 define <3 x i32> @and_lshr_and_vec_undef(<3 x i32> %arg) {
 ; CHECK-LABEL: @and_lshr_and_vec_undef(
-; CHECK-NEXT:    [[TMP1:%.*]] = and <3 x i32> [[ARG:%.*]], <i32 3, i32 undef, i32 3>
+; CHECK-NEXT:    [[TMP1:%.*]] = and <3 x i32> [[ARG:%.*]], <i32 3, i32 -1, i32 3>
 ; CHECK-NEXT:    [[TMP2:%.*]] = icmp ne <3 x i32> [[TMP1]], zeroinitializer
 ; CHECK-NEXT:    [[TMP4:%.*]] = zext <3 x i1> [[TMP2]] to <3 x i32>
 ; CHECK-NEXT:    ret <3 x i32> [[TMP4]]
 ;
   %tmp = and <3 x i32> %arg, <i32 1, i32 undef, i32 1>
   %tmp1 = icmp eq <3 x i32> %tmp, <i32 0, i32 undef, i32 0>
   %tmp2 = lshr <3 x i32> %arg, <i32 1, i32 undef, i32 1>
   %tmp3 = and <3 x i32> %tmp2, <i32 1, i32 undef, i32 1>
;
   %tmp3 = lshr <2 x i32> %arg, <i32 1, i32 2> ; shift is not splat
   %tmp4 = and <2 x i32> %tmp3, <i32 1, i32 1>
   %tmp5 = select <2 x i1> %tmp2, <2 x i32> %tmp4, <2 x i32> <i32 1, i32 1>
   ret <2 x i32> %tmp5
 }
 
 define <3 x i32> @f_var0_vec_undef(<3 x i32> %arg, <3 x i32> %arg1) {
 ; CHECK-LABEL: @f_var0_vec_undef(
-; CHECK-NEXT:    [[TMP1:%.*]] = or <3 x i32> [[ARG1:%.*]], <i32 2, i32 undef, i32 2>
+; CHECK-NEXT:    [[TMP1:%.*]] = or <3 x i32> [[ARG1:%.*]], <i32 2, i32 1, i32 2>
 ; CHECK-NEXT:    [[TMP2:%.*]] = and <3 x i32> [[TMP1]], [[ARG:%.*]]
 ; CHECK-NEXT:    [[TMP3:%.*]] = icmp ne <3 x i32> [[TMP2]], zeroinitializer
 ; CHECK-NEXT:    [[TMP5:%.*]] = zext <3 x i1> [[TMP3]] to <3 x i32>
 ; CHECK-NEXT:    ret <3 x i32> [[TMP5]]
 ;
   %tmp = and <3 x i32> %arg, %arg1
   %tmp2 = icmp eq <3 x i32> %tmp, <i32 0, i32 undef, i32 0>
   %tmp3 = lshr <3 x i32> %arg, <i32 1, i32 undef, i32 1>
;
   %tmp = and <3 x i32> %arg, %arg1
   %tmp2 = icmp eq <3 x i32> %tmp, <i32 0, i32 undef, i32 0>
   %tmp3 = and <3 x i32> %arg, <i32 1, i32 undef, i32 1>
   %tmp4 = select <3 x i1> %tmp2, <3 x i32> %tmp3, <3 x i32> <i32 1, i32 undef, i32 1>
   ret <3 x i32> %tmp4
 }
 
 ; ============================================================================ ;
-; Shift can be a variable, too.
+; Shift can't be a variable in general
 ; ============================================================================ ;
 
 define i32 @f_var2(i32 %arg, i32 %arg1) {
 ; CHECK-LABEL: @f_var2(
-; CHECK-NEXT:    [[TMP1:%.*]] = shl i32 1, [[ARG1:%.*]]
-; CHECK-NEXT:    [[TMP2:%.*]] = or i32 [[TMP1]], 1
-; CHECK-NEXT:    [[TMP3:%.*]] = and i32 [[TMP2]], [[ARG:%.*]]
-; CHECK-NEXT:    [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
-; CHECK-NEXT:    [[TMP5:%.*]] = zext i1 [[TMP4]] to i32
+; CHECK-NEXT:    [[TMP:%.*]] = and i32 [[ARG:%.*]], 1
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i32 [[TMP]], 0
+; CHECK-NEXT:    [[TMP3:%.*]] = lshr i32 [[ARG]], [[ARG1:%.*]]
+; CHECK-NEXT:    [[TMP4:%.*]] = and i32 [[TMP3]], 1
+; CHECK-NEXT:    [[TMP5:%.*]] = select i1 [[TMP2]], i32 [[TMP4]], i32 1
 ; CHECK-NEXT:    ret i32 [[TMP5]]
 ;
   %tmp = and i32 %arg, 1
   %tmp2 = icmp eq i32 %tmp, 0
   %tmp3 = lshr i32 %arg, %arg1
   %tmp4 = and i32 %tmp3, 1
   %tmp5 = select i1 %tmp2, i32 %tmp4, i32 1
   ret i32 %tmp5
 }
 
 define <2 x i32> @f_var2_splatvec(<2 x i32> %arg, <2 x i32> %arg1) {
 ; CHECK-LABEL: @f_var2_splatvec(
-; CHECK-NEXT:    [[TMP1:%.*]] = shl <2 x i32> <i32 1, i32 1>, [[ARG1:%.*]]
-; CHECK-NEXT:    [[TMP2:%.*]] = or <2 x i32> [[TMP1]], <i32 1, i32 1>
-; CHECK-NEXT:    [[TMP3:%.*]] = and <2 x i32> [[TMP2]], [[ARG:%.*]]
-; CHECK-NEXT:    [[TMP4:%.*]] = icmp ne <2 x i32> [[TMP3]], zeroinitializer
-; CHECK-NEXT:    [[TMP5:%.*]] = zext <2 x i1> [[TMP4]] to <2 x i32>
+; CHECK-NEXT:    [[TMP:%.*]] = and <2 x i32> [[ARG:%.*]], <i32 1, i32 1>
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq <2 x i32> [[TMP]], zeroinitializer
+; CHECK-NEXT:    [[TMP3:%.*]] = lshr <2 x i32> [[ARG]], [[ARG1:%.*]]
+; CHECK-NEXT:    [[TMP4:%.*]] = and <2 x i32> [[TMP3]], <i32 1, i32 1>
+; CHECK-NEXT:    [[TMP5:%.*]] = select <2 x i1> [[TMP2]], <2 x i32> [[TMP4]], <2 x i32> <i32 1, i32 1>
 ; CHECK-NEXT:    ret <2 x i32> [[TMP5]]
 ;
   %tmp = and <2 x i32> %arg, <i32 1, i32 1>
   %tmp2 = icmp eq <2 x i32> %tmp, zeroinitializer
   %tmp3 = lshr <2 x i32> %arg, %arg1
   %tmp4 = and <2 x i32> %tmp3, <i32 1, i32 1>
   %tmp5 = select <2 x i1> %tmp2, <2 x i32> %tmp4, <2 x i32> <i32 1, i32 1>
   ret <2 x i32> %tmp5
 }
 
 define <2 x i32> @f_var2_vec(<2 x i32> %arg, <2 x i32> %arg1) {
 ; CHECK-LABEL: @f_var2_vec(
-; CHECK-NEXT:    [[TMP1:%.*]] = shl <2 x i32> <i32 1, i32 1>, [[ARG1:%.*]]
-; CHECK-NEXT:    [[TMP2:%.*]] = or <2 x i32> [[TMP1]], <i32 2, i32 1>
-; CHECK-NEXT:    [[TMP3:%.*]] = and <2 x i32> [[TMP2]], [[ARG:%.*]]
-; CHECK-NEXT:    [[TMP4:%.*]] = icmp ne <2 x i32> [[TMP3]], zeroinitializer
-; CHECK-NEXT:    [[TMP5:%.*]] = zext <2 x i1> [[TMP4]] to <2 x i32>
+; CHECK-NEXT:    [[TMP:%.*]] = and <2 x i32> [[ARG:%.*]], <i32 2, i32 1>
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq <2 x i32> [[TMP]], zeroinitializer
+; CHECK-NEXT:    [[TMP3:%.*]] = lshr <2 x i32> [[ARG]], [[ARG1:%.*]]
+; CHECK-NEXT:    [[TMP4:%.*]] = and <2 x i32> [[TMP3]], <i32 1, i32 1>
+; CHECK-NEXT:    [[TMP5:%.*]] = select <2 x i1> [[TMP2]], <2 x i32> [[TMP4]], <2 x i32> <i32 1, i32 1>
 ; CHECK-NEXT:    ret <2 x i32> [[TMP5]]
 ;
   %tmp = and <2 x i32> %arg, <i32 2, i32 1>; mask is not splat
   %tmp2 = icmp eq <2 x i32> %tmp, zeroinitializer
   %tmp3 = lshr <2 x i32> %arg, %arg1
   %tmp4 = and <2 x i32> %tmp3, <i32 1, i32 1>
   %tmp5 = select <2 x i1> %tmp2, <2 x i32> %tmp4, <2 x i32> <i32 1, i32 1>
   ret <2 x i32> %tmp5
 }
 
 define <3 x i32> @f_var2_vec_undef(<3 x i32> %arg, <3 x i32> %arg1) {
 ; CHECK-LABEL: @f_var2_vec_undef(
-; CHECK-NEXT:    [[TMP1:%.*]] = shl <3 x i32> <i32 1, i32 1, i32 1>, [[ARG1:%.*]]
-; CHECK-NEXT:    [[TMP2:%.*]] = or <3 x i32> [[TMP1]], <i32 1, i32 undef, i32 1>
-; CHECK-NEXT:    [[TMP3:%.*]] = and <3 x i32> [[TMP2]], [[ARG:%.*]]
-; CHECK-NEXT:    [[TMP4:%.*]] = icmp ne <3 x i32> [[TMP3]], zeroinitializer
-; CHECK-NEXT:    [[TMP5:%.*]] = zext <3 x i1> [[TMP4]] to <3 x i32>
+; CHECK-NEXT:    [[TMP:%.*]] = and <3 x i32> [[ARG:%.*]], <i32 1, i32 undef, i32 1>
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq <3 x i32> [[TMP]], <i32 0, i32 undef, i32 0>
+; CHECK-NEXT:    [[TMP3:%.*]] = lshr <3 x i32> [[ARG]], [[ARG1:%.*]]
+; CHECK-NEXT:    [[TMP4:%.*]] = and <3 x i32> [[TMP3]], <i32 1, i32 undef, i32 1>
+; CHECK-NEXT:    [[TMP5:%.*]] = select <3 x i1> [[TMP2]], <3 x i32> [[TMP4]], <3 x i32> <i32 1, i32 undef, i32 1>
 ; CHECK-NEXT:    ret <3 x i32> [[TMP5]]
 ;
   %tmp = and <3 x i32> %arg, <i32 1, i32 undef, i32 1>
   %tmp2 = icmp eq <3 x i32> %tmp, <i32 0, i32 undef, i32 0>
   %tmp3 = lshr <3 x i32> %arg, %arg1
   %tmp4 = and <3 x i32> %tmp3, <i32 1, i32 undef, i32 1>
   %tmp5 = select <3 x i1> %tmp2, <3 x i32> %tmp4, <3 x i32> <i32 1, i32 undef, i32 1>
   ret <3 x i32> %tmp5
 }
 
 ; ============================================================================ ;
 ; The worst case: both Mask and Shift are variables
 ; ============================================================================ ;
 
 define i32 @f_var3(i32 %arg, i32 %arg1, i32 %arg2) {
 ; CHECK-LABEL: @f_var3(
-; CHECK-NEXT:    [[TMP1:%.*]] = shl i32 1, [[ARG2:%.*]]
-; CHECK-NEXT:    [[TMP2:%.*]] = or i32 [[TMP1]], [[ARG1:%.*]]
-; CHECK-NEXT:    [[TMP3:%.*]] = and i32 [[TMP2]], [[ARG:%.*]]
-; CHECK-NEXT:    [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
-; CHECK-NEXT:    [[TMP6:%.*]] = zext i1 [[TMP4]] to i32
+; CHECK-NEXT:    [[TMP:%.*]] = and i32 [[ARG:%.*]], [[ARG1:%.*]]
+; CHECK-NEXT:    [[TMP3:%.*]] = icmp eq i32 [[TMP]], 0
+; CHECK-NEXT:    [[TMP4:%.*]] = lshr i32 [[ARG]], [[ARG2:%.*]]
+; CHECK-NEXT:    [[TMP5:%.*]] = and i32 [[TMP4]], 1
+; CHECK-NEXT:    [[TMP6:%.*]] = select i1 [[TMP3]], i32 [[TMP5]], i32 1
 ; CHECK-NEXT:    ret i32 [[TMP6]]
 ;
   %tmp = and i32 %arg, %arg1
   %tmp3 = icmp eq i32 %tmp, 0
   %tmp4 = lshr i32 %arg, %arg2
   %tmp5 = and i32 %tmp4, 1
   %tmp6 = select i1 %tmp3, i32 %tmp5, i32 1
   ret i32 %tmp6
 }
 
 ; Should be exactly as the previous one
 define i32 @f_var3_commutative_and(i32 %arg, i32 %arg1, i32 %arg2) {
 ; CHECK-LABEL: @f_var3_commutative_and(
-; CHECK-NEXT:    [[TMP1:%.*]] = shl i32 1, [[ARG2:%.*]]
-; CHECK-NEXT:    [[TMP2:%.*]] = or i32 [[TMP1]], [[ARG1:%.*]]
-; CHECK-NEXT:    [[TMP3:%.*]] = and i32 [[TMP2]], [[ARG:%.*]]
-; CHECK-NEXT:    [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
-; CHECK-NEXT:    [[TMP6:%.*]] = zext i1 [[TMP4]] to i32
+; CHECK-NEXT:    [[TMP:%.*]] = and i32 [[ARG1:%.*]], [[ARG:%.*]]
+; CHECK-NEXT:    [[TMP3:%.*]] = icmp eq i32 [[TMP]], 0
+; CHECK-NEXT:    [[TMP4:%.*]] = lshr i32 [[ARG]], [[ARG2:%.*]]
+; CHECK-NEXT:    [[TMP5:%.*]] = and i32 [[TMP4]], 1
+; CHECK-NEXT:    [[TMP6:%.*]] = select i1 [[TMP3]], i32 [[TMP5]], i32 1
 ; CHECK-NEXT:    ret i32 [[TMP6]]
 ;
   %tmp = and i32 %arg1, %arg ; in different order
   %tmp3 = icmp eq i32 %tmp, 0
   %tmp4 = lshr i32 %arg, %arg2
   %tmp5 = and i32 %tmp4, 1
   %tmp6 = select i1 %tmp3, i32 %tmp5, i32 1
   ret i32 %tmp6
 }
 
 define <2 x i32> @f_var3_splatvec(<2 x i32> %arg, <2 x i32> %arg1, <2 x i32> %arg2) {
 ; CHECK-LABEL: @f_var3_splatvec(
-; CHECK-NEXT:    [[TMP1:%.*]] = shl <2 x i32> <i32 1, i32 1>, [[ARG2:%.*]]
-; CHECK-NEXT:    [[TMP2:%.*]] = or <2 x i32> [[TMP1]], [[ARG1:%.*]]
-; CHECK-NEXT:    [[TMP3:%.*]] = and <2 x i32> [[TMP2]], [[ARG:%.*]]
-; CHECK-NEXT:    [[TMP4:%.*]] = icmp ne <2 x i32> [[TMP3]], zeroinitializer
-; CHECK-NEXT:    [[TMP6:%.*]] = zext <2 x i1> [[TMP4]] to <2 x i32>
+; CHECK-NEXT:    [[TMP:%.*]] = and <2 x i32> [[ARG:%.*]], [[ARG1:%.*]]
+; CHECK-NEXT:    [[TMP3:%.*]] = icmp eq <2 x i32> [[TMP]], zeroinitializer
+; CHECK-NEXT:    [[TMP4:%.*]] = lshr <2 x i32> [[ARG]], [[ARG2:%.*]]
+; CHECK-NEXT:    [[TMP5:%.*]] = and <2 x i32> [[TMP4]], <i32 1, i32 1>
+; CHECK-NEXT:    [[TMP6:%.*]] = select <2 x i1> [[TMP3]], <2 x i32> [[TMP5]], <2 x i32> <i32 1, i32 1>
 ; CHECK-NEXT:    ret <2 x i32> [[TMP6]]
 ;
   %tmp = and <2 x i32> %arg, %arg1
   %tmp3 = icmp eq <2 x i32> %tmp, zeroinitializer
   %tmp4 = lshr <2 x i32> %arg, %arg2
   %tmp5 = and <2 x i32> %tmp4, <i32 1, i32 1>
   %tmp6 = select <2 x i1> %tmp3, <2 x i32> %tmp5, <2 x i32> <i32 1, i32 1>
   ret <2 x i32> %tmp6
 }
 
 define <3 x i32> @f_var3_vec_undef(<3 x i32> %arg, <3 x i32> %arg1, <3 x i32> %arg2) {
 ; CHECK-LABEL: @f_var3_vec_undef(
-; CHECK-NEXT:    [[TMP1:%.*]] = shl <3 x i32> <i32 1, i32 1, i32 1>, [[ARG2:%.*]]
-; CHECK-NEXT:    [[TMP2:%.*]] = or <3 x i32> [[TMP1]], [[ARG1:%.*]]
-; CHECK-NEXT:    [[TMP3:%.*]] = and <3 x i32> [[TMP2]], [[ARG:%.*]]
-; CHECK-NEXT:    [[TMP4:%.*]] = icmp ne <3 x i32> [[TMP3]], zeroinitializer
-; CHECK-NEXT:    [[TMP6:%.*]] = zext <3 x i1> [[TMP4]] to <3 x i32>
+; CHECK-NEXT:    [[TMP:%.*]] = and <3 x i32> [[ARG:%.*]], [[ARG1:%.*]]
+; CHECK-NEXT:    [[TMP3:%.*]] = icmp eq <3 x i32> [[TMP]], <i32 0, i32 undef, i32 0>
+; CHECK-NEXT:    [[TMP4:%.*]] = lshr <3 x i32> [[ARG]], [[ARG2:%.*]]
+; CHECK-NEXT:    [[TMP5:%.*]] = and <3 x i32> [[TMP4]], <i32 1, i32 undef, i32 1>
+; CHECK-NEXT:    [[TMP6:%.*]] = select <3 x i1> [[TMP3]], <3 x i32> [[TMP5]], <3 x i32> <i32 1, i32 undef, i32 1>
 ; CHECK-NEXT:    ret <3 x i32> [[TMP6]]
 ;
   %tmp = and <3 x i32> %arg, %arg1
   %tmp3 = icmp eq <3 x i32> %tmp, <i32 0, i32 undef, i32 0>
   %tmp4 = lshr <3 x i32> %arg, %arg2
   %tmp5 = and <3 x i32> %tmp4, <i32 1, i32 undef, i32 1>
   %tmp6 = select <3 x i1> %tmp3, <3 x i32> %tmp5, <3 x i32> <i32 1, i32 undef, i32 1>
   ret <3 x i32> %tmp6
;
   ret i32 %tmp3
 }
 
 ; Wrong icmp pred
 
 define i32 @n6(i32 %arg) {
 ; CHECK-LABEL: @n6(
 ; CHECK-NEXT:    [[TMP:%.*]] = and i32 [[ARG:%.*]], 1
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq i32 [[TMP]], 0
+; CHECK-NEXT:    [[TMP1_NOT:%.*]] = icmp eq i32 [[TMP]], 0
 ; CHECK-NEXT:    [[TMP2:%.*]] = lshr i32 [[ARG]], 2
 ; CHECK-NEXT:    [[TMP3:%.*]] = and i32 [[TMP2]], 1
-; CHECK-NEXT:    [[TMP4:%.*]] = select i1 [[TMP1]], i32 1, i32 [[TMP3]]
+; CHECK-NEXT:    [[TMP4:%.*]] = select i1 [[TMP1_NOT]], i32 1, i32 [[TMP3]]
 ; CHECK-NEXT:    ret i32 [[TMP4]]
 ;
   %tmp = and i32 %arg, 1
   %tmp1 = icmp ne i32 %tmp, 0 ; ne, not eq
   %tmp2 = lshr i32 %arg, 2
   %tmp3 = and i32 %tmp2, 1
   %tmp4 = select i1 %tmp1, i32 %tmp3, i32 1
   ret i32 %tmp4
 }
 
 define i32 @n7(i32 %arg) {
 ; CHECK-LABEL: @n7(
 ; CHECK-NEXT:    [[TMP:%.*]] = and i32 [[ARG:%.*]], 2
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq i32 [[TMP]], 0
+; CHECK-NEXT:    [[TMP1_NOT:%.*]] = icmp eq i32 [[TMP]], 0
 ; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[ARG]], 1
-; CHECK-NEXT:    [[TMP3:%.*]] = select i1 [[TMP1]], i32 1, i32 [[TMP2]]
+; CHECK-NEXT:    [[TMP3:%.*]] = select i1 [[TMP1_NOT]], i32 1, i32 [[TMP2]]
 ; CHECK-NEXT:    ret i32 [[TMP3]]
 ;
   %tmp = and i32 %arg, 2
   %tmp1 = icmp ne i32 %tmp, 0 ; ne, not eq
   %tmp2 = and i32 %arg, 1
   %tmp3 = select i1 %tmp1, i32 %tmp2, i32 1
   ret i32 %tmp3
 }
 
 ; icmp second operand is not zero
 
 define i32 @n8(i32 %arg) {
 ; CHECK-LABEL: @n8(
 ; CHECK-NEXT:    [[TMP:%.*]] = and i32 [[ARG:%.*]], 1
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq i32 [[TMP]], 0
+; CHECK-NEXT:    [[TMP1_NOT:%.*]] = icmp eq i32 [[TMP]], 0
 ; CHECK-NEXT:    [[TMP2:%.*]] = lshr i32 [[ARG]], 2
 ; CHECK-NEXT:    [[TMP3:%.*]] = and i32 [[TMP2]], 1
-; CHECK-NEXT:    [[TMP4:%.*]] = select i1 [[TMP1]], i32 1, i32 [[TMP3]]
+; CHECK-NEXT:    [[TMP4:%.*]] = select i1 [[TMP1_NOT]], i32 1, i32 [[TMP3]]
 ; CHECK-NEXT:    ret i32 [[TMP4]]
 ;
   %tmp = and i32 %arg, 1
   %tmp1 = icmp eq i32 %tmp, 1
   %tmp2 = lshr i32 %arg, 2
   %tmp3 = and i32 %tmp2, 1
   %tmp4 = select i1 %tmp1, i32 %tmp3, i32 1
   ret i32 %tmp4
 }