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Differential D88419

[RDA] Switch isSafeToMove iterators
ClosedPublic

Authored by samparker on Sep 28 2020, 7:50 AM.

Details

Reviewers
SjoerdMeijer
samtebbs
nikic
dmgreen
Commits
rG700f93e92b6d: [RDA] Switch isSafeToMove iterators
Summary

So that forwards is forwards and backwards is reverse. Also add a check so that we know the instructions are in the expected order. We'll need a follow-up patch to two to be able to successfully move instructions around for ARMLowOverheadLoops.

Diff Detail

Event Timeline

samparker created this revision.Sep 28 2020, 7:50 AM
Herald added a project: Restricted Project. · View Herald TranscriptSep 28 2020, 7:50 AM
Herald added subscribers: hiraditya, kristof.beyls. · View Herald Transcript
samparker requested review of this revision.Sep 28 2020, 7:50 AM
Harbormaster completed remote builds in B73170: Diff 294704.Sep 28 2020, 8:02 AM
samtebbs added inline comments.Sep 28 2020, 8:54 AM
llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-operand.ll
31

I may be misunderstanding this but won't this overwrite the subtraction to r3 that is done each iteration? So I think this should be outside the loop like it was before.

samparker added inline comments.Sep 29 2020, 12:21 AM
llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-operand.ll
31

The DLS doesn't actually signal the beginning on the loop, and the mov is still in the preheader. The loop body begins with the vctp.32.

SjoerdMeijer accepted this revision.Sep 29 2020, 1:07 AM

If Sam has no further questions, this looks good to me.

llvm/lib/CodeGen/ReachingDefAnalysis.cpp
582–587

This code is an exact copy of the previous one, except one iterator. This can probably be refactored into one IsSafeToMove function that gets passed in this iterator. But it's a nit, up to you if it is worth doing this.

This revision is now accepted and ready to land.Sep 29 2020, 1:07 AM
samparker added inline comments.Sep 29 2020, 1:18 AM
llvm/lib/CodeGen/ReachingDefAnalysis.cpp
582–587

I thought the same, but each loop uses different sentinels: begin/rbegin and end/rend and I didn't see a way to handle that.

SjoerdMeijer added inline comments.Sep 29 2020, 1:19 AM
llvm/lib/CodeGen/ReachingDefAnalysis.cpp
582–587

ok, fair enough

Closed by commit rG700f93e92b6d: [RDA] Switch isSafeToMove iterators (authored by samparker). · Explain WhySep 30 2020, 12:11 AM
This revision was automatically updated to reflect the committed changes.
samparker added a commit: rG700f93e92b6d: [RDA] Switch isSafeToMove iterators.

Revision Contents

PathSize
llvm/
lib/
CodeGen/
16 lines
test/
CodeGen/
Thumb2/
LowOverheadLoops/
2 lines
2 lines
2 lines
25 lines
21 lines

Diff 295185

llvm/lib/CodeGen/ReachingDefAnalysis.cpp

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} }
// Can we safely move 'From' to just before 'To'? To satisfy this, 'From' must // Can we safely move 'From' to just before 'To'? To satisfy this, 'From' must
// not define a register that is used by any instructions, after and including, // not define a register that is used by any instructions, after and including,
// 'To'. These instructions also must not redefine any of Froms operands. // 'To'. These instructions also must not redefine any of Froms operands.
template<typename Iterator> template<typename Iterator>
bool ReachingDefAnalysis::isSafeToMove(MachineInstr *From, bool ReachingDefAnalysis::isSafeToMove(MachineInstr *From,
MachineInstr *To) const { MachineInstr *To) const {
if (From->getParent() != To->getParent()) if (From->getParent() != To->getParent() || From == To)
return false; return false;
SmallSet<int, 2> Defs; SmallSet<int, 2> Defs;
// First check that From would compute the same value if moved. // First check that From would compute the same value if moved.
for (auto &MO : From->operands()) { for (auto &MO : From->operands()) {
if (!isValidReg(MO)) if (!isValidReg(MO))
continue; continue;
if (MO.isDef()) if (MO.isDef())
Show All 12 Lines for (auto &MO : I->operands())
if (MO.isReg() && MO.getReg() && Defs.count(MO.getReg())) if (MO.isReg() && MO.getReg() && Defs.count(MO.getReg()))
return false; return false;
} }
return true; return true;
} }
bool ReachingDefAnalysis::isSafeToMoveForwards(MachineInstr *From, bool ReachingDefAnalysis::isSafeToMoveForwards(MachineInstr *From,
MachineInstr *To) const { MachineInstr *To) const {
return isSafeToMove<MachineBasicBlock::reverse_iterator>(From, To); using Iterator = MachineBasicBlock::iterator;
// Walk forwards until we find the instruction.
for (auto I = Iterator(From), E = From->getParent()->end(); I != E; ++I)
if (&*I == To)
return isSafeToMove<Iterator>(From, To);
return false;
} }
bool ReachingDefAnalysis::isSafeToMoveBackwards(MachineInstr *From, bool ReachingDefAnalysis::isSafeToMoveBackwards(MachineInstr *From,
MachineInstr *To) const { MachineInstr *To) const {
return isSafeToMove<MachineBasicBlock::iterator>(From, To); using Iterator = MachineBasicBlock::reverse_iterator;
// Walk backwards until we find the instruction.
for (auto I = Iterator(From), E = From->getParent()->rend(); I != E; ++I)
if (&*I == To)
return isSafeToMove<Iterator>(From, To);
return false;
SjoerdMeijerUnsubmitted
Not Done
ReplyInline Actions

This code is an exact copy of the previous one, except one iterator. This can probably be refactored into one IsSafeToMove function that gets passed in this iterator. But it's a nit, up to you if it is worth doing this.

SjoerdMeijer: This code is an exact copy of the previous one, except one iterator. This can probably be…
samparkerAuthorUnsubmitted
Done
ReplyInline Actions

I thought the same, but each loop uses different sentinels: begin/rbegin and end/rend and I didn't see a way to handle that.

samparker: I thought the same, but each loop uses different sentinels: begin/rbegin and end/rend and I…
SjoerdMeijerUnsubmitted
Not Done
ReplyInline Actions

ok, fair enough

SjoerdMeijer: ok, fair enough
} }
bool ReachingDefAnalysis::isSafeToRemove(MachineInstr *MI, bool ReachingDefAnalysis::isSafeToRemove(MachineInstr *MI,
InstSet &ToRemove) const { InstSet &ToRemove) const {
SmallPtrSet<MachineInstr*, 1> Ignore; SmallPtrSet<MachineInstr*, 1> Ignore;
SmallPtrSet<MachineInstr*, 2> Visited; SmallPtrSet<MachineInstr*, 2> Visited;
return isSafeToRemove(MI, Visited, ToRemove, Ignore); return isSafeToRemove(MI, Visited, ToRemove, Ignore);
} }
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llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-mov.mir

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; CHECK: renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r3, 0, 0, $noreg ; CHECK: renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r3, 0, 0, $noreg
; CHECK: renamable $q0 = nnan ninf nsz MVE_VADDf32 killed renamable $q0, killed renamable $q1, 0, killed $noreg, killed renamable $q0 ; CHECK: renamable $q0 = nnan ninf nsz MVE_VADDf32 killed renamable $q0, killed renamable $q1, 0, killed $noreg, killed renamable $q0
; CHECK: renamable $r3, dead $cpsr = nuw tADDi8 killed renamable $r3, 16, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = nuw tADDi8 killed renamable $r3, 16, 14 /* CC::al */, $noreg
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.3 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.3
; CHECK: bb.4: ; CHECK: bb.4:
; CHECK: successors: %bb.5(0x80000000) ; CHECK: successors: %bb.5(0x80000000)
; CHECK: liveins: $q0, $r0, $r1, $r2, $r4 ; CHECK: liveins: $q0, $r0, $r1, $r2, $r4
; CHECK: renamable $s4 = nnan ninf nsz VADDS renamable $s0, renamable $s1, 14 /* CC::al */, $noreg ; CHECK: renamable $s4 = nnan ninf nsz VADDS renamable $s0, renamable $s1, 14 /* CC::al */, $noreg
; CHECK: $r3 = tMOVr $r1, 14 /* CC::al */, $noreg
; CHECK: $lr = t2DLS killed $r4 ; CHECK: $lr = t2DLS killed $r4
; CHECK: $r3 = tMOVr $r1, 14 /* CC::al */, $noreg
; CHECK: renamable $s4 = nnan ninf nsz VADDS renamable $s2, killed renamable $s4, 14 /* CC::al */, $noreg ; CHECK: renamable $s4 = nnan ninf nsz VADDS renamable $s2, killed renamable $s4, 14 /* CC::al */, $noreg
; CHECK: renamable $s0 = nnan ninf nsz VADDS killed renamable $s3, killed renamable $s4, 14 /* CC::al */, $noreg, implicit killed $q0 ; CHECK: renamable $s0 = nnan ninf nsz VADDS killed renamable $s3, killed renamable $s4, 14 /* CC::al */, $noreg, implicit killed $q0
; CHECK: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg ; CHECK: $s2 = VMOVSR $r1, 14 /* CC::al */, $noreg
; CHECK: renamable $s2 = VUITOS killed renamable $s2, 14 /* CC::al */, $noreg ; CHECK: renamable $s2 = VUITOS killed renamable $s2, 14 /* CC::al */, $noreg
; CHECK: renamable $s4 = nnan ninf nsz VDIVS killed renamable $s0, killed renamable $s2, 14 /* CC::al */, $noreg ; CHECK: renamable $s4 = nnan ninf nsz VDIVS killed renamable $s0, killed renamable $s2, 14 /* CC::al */, $noreg
; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0
; CHECK: bb.5: ; CHECK: bb.5:
; CHECK: successors: %bb.5(0x7c000000), %bb.6(0x04000000) ; CHECK: successors: %bb.5(0x7c000000), %bb.6(0x04000000)
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llvm/test/CodeGen/Thumb2/LowOverheadLoops/lstp-insertion-position.mir

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; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7
; CHECK: renamable $r3, dead $cpsr = tMOVi8 3, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 3, 14 /* CC::al */, $noreg
; CHECK: renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK: renamable $lr = t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $lr = t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3 = tLDRpci %const.0, 14 /* CC::al */, $noreg :: (load 4 from constant-pool) ; CHECK: renamable $r3 = tLDRpci %const.0, 14 /* CC::al */, $noreg :: (load 4 from constant-pool)
; CHECK: renamable $r2, dead $cpsr = tLSRri killed renamable $r2, 2, 14 /* CC::al */, $noreg
; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: $lr = t2DLS killed renamable $lr
; CHECK: renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, undef renamable $q1
; CHECK: renamable $r2, dead $cpsr = tLSRri killed renamable $r2, 2, 14 /* CC::al */, $noreg
; CHECK: $s4 = VMOVS killed $s0, 14 /* CC::al */, $noreg, implicit killed $q1, implicit-def $q1 ; CHECK: $s4 = VMOVS killed $s0, 14 /* CC::al */, $noreg, implicit killed $q1, implicit-def $q1
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $q1, $r0, $r1, $r2 ; CHECK: liveins: $lr, $q1, $r0, $r1, $r2
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg
; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
; CHECK: MVE_VPST 2, implicit $vpr ; CHECK: MVE_VPST 2, implicit $vpr
; CHECK: renamable $r0, renamable $q0 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv13, align 4) ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv13, align 4)
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llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-operand.ll

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; CHECK-NEXT: mov r4, lr ; CHECK-NEXT: mov r4, lr
; CHECK-NEXT: .LBB0_1: @ %do.body.i ; CHECK-NEXT: .LBB0_1: @ %do.body.i
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrw.u32 q1, [r12], #16 ; CHECK-NEXT: vldrw.u32 q1, [r12], #16
; CHECK-NEXT: vadd.f32 q0, q0, q1 ; CHECK-NEXT: vadd.f32 q0, q0, q1
; CHECK-NEXT: letp lr, .LBB0_1 ; CHECK-NEXT: letp lr, .LBB0_1
; CHECK-NEXT: @ %bb.2: @ %arm_mean_f32_mve.exit ; CHECK-NEXT: @ %bb.2: @ %arm_mean_f32_mve.exit
; CHECK-NEXT: vmov s4, r1 ; CHECK-NEXT: vmov s4, r1
; CHECK-NEXT: mov r3, r1
; CHECK-NEXT: dls lr, r4 ; CHECK-NEXT: dls lr, r4
; CHECK-NEXT: vadd.f32 s0, s3, s3 ; CHECK-NEXT: vadd.f32 s0, s3, s3
; CHECK-NEXT: mov r3, r1
samtebbsUnsubmitted
Not Done
ReplyInline Actions

I may be misunderstanding this but won't this overwrite the subtraction to r3 that is done each iteration? So I think this should be outside the loop like it was before.

samtebbs: I may be misunderstanding this but won't this overwrite the subtraction to r3 that is done each…
samparkerAuthorUnsubmitted
Done
ReplyInline Actions

The DLS doesn't actually signal the beginning on the loop, and the mov is still in the preheader. The loop body begins with the vctp.32.

samparker: The DLS doesn't actually signal the beginning on the loop, and the mov is still in the…
; CHECK-NEXT: vcvt.f32.u32 s4, s4 ; CHECK-NEXT: vcvt.f32.u32 s4, s4
; CHECK-NEXT: vdiv.f32 s0, s0, s4 ; CHECK-NEXT: vdiv.f32 s0, s0, s4
; CHECK-NEXT: vmov r12, s0 ; CHECK-NEXT: vmov r12, s0
; CHECK-NEXT: vmov.i32 q0, #0x0 ; CHECK-NEXT: vmov.i32 q0, #0x0
; CHECK-NEXT: .LBB0_3: @ %do.body ; CHECK-NEXT: .LBB0_3: @ %do.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vctp.32 r3 ; CHECK-NEXT: vctp.32 r3
; CHECK-NEXT: subs r3, #4 ; CHECK-NEXT: subs r3, #4
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llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-def-before-start.mir

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; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8
; CHECK: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: t2CMPrs killed renamable $r12, renamable $r3, 11, 14 /* CC::al */, $noreg, implicit-def $cpsr ; CHECK: t2CMPrs killed renamable $r12, renamable $r3, 11, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2IT 0, 8, implicit-def $itstate ; CHECK: t2IT 0, 8, implicit-def $itstate
; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate ; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate
; CHECK: bb.1.vector.ph: ; CHECK: bb.1.vector.ph:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1, $r2, $r3 ; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK: renamable $r12 = t2MOVi 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = nuw t2ADDrs killed renamable $r12, renamable $r3, 11, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2BICri killed renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: $r12 = t2MOVr killed $r3, 14 /* CC::al */, $noreg, $noreg ; CHECK: $r12 = t2MOVr killed $r3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2LSRri killed renamable $r12, 1, 14 /* CC::al */, $noreg, $noreg ; CHECK: $lr = t2DLS killed renamable $lr
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r12
; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: renamable $r12 = t2LSRri killed renamable $r12, 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r12
; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14 /* CC::al */, $noreg ; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14 /* CC::al */, $noreg
; CHECK: renamable $q0 = MVE_VLDRBU32 killed renamable $r4, 0, 0, $noreg :: (load 4 from %ir.scevgep45, align 1) ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg
; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $q0 = MVE_VLDRBU32 killed renamable $r4, 0, 1, renamable $vpr :: (load 4 from %ir.scevgep45, align 1)
; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14 /* CC::al */, $noreg ; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14 /* CC::al */, $noreg
; CHECK: renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $q1 = MVE_VLDRBU32 killed renamable $r4, 0, 0, $noreg :: (load 4 from %ir.scevgep23, align 1) ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $q1 = MVE_VLDRBU32 killed renamable $r4, 0, 1, renamable $vpr :: (load 4 from %ir.scevgep23, align 1)
; CHECK: renamable $q0 = nuw nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = nuw nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 0, killed $noreg :: (store 16 into %ir.lsr.iv1, align 4) ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 ; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv1, align 4)
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.for.cond.cleanup: ; CHECK: bb.3.for.cond.cleanup:
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $r3, $r4, $lr liveins: $r0, $r1, $r2, $r3, $r4, $lr
frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION def_cfa_offset 8
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llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-start-after-def.mir

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; CHECK: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
; CHECK: t2CMPrs killed renamable $r12, renamable $r3, 11, 14 /* CC::al */, $noreg, implicit-def $cpsr ; CHECK: t2CMPrs killed renamable $r12, renamable $r3, 11, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2IT 0, 8, implicit-def $itstate ; CHECK: t2IT 0, 8, implicit-def $itstate
; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate ; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate
; CHECK: bb.1.vector.ph: ; CHECK: bb.1.vector.ph:
; CHECK: successors: %bb.2(0x80000000) ; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1, $r2, $r3 ; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK: renamable $r12 = t2MOVi 3, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2MOVi 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = nuw t2ADDrs killed renamable $r12, renamable $r3, 11, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = nuw t2ADDrs killed renamable $r12, renamable $r3, 11, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2BICri killed renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2BICri killed renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: dead renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: $lr = t2DLS killed renamable $lr
; CHECK: $r12 = t2MOVr killed $r3, 14 /* CC::al */, $noreg, $noreg ; CHECK: $r12 = t2MOVr killed $r3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: renamable $r12 = t2LSRri killed renamable $r12, 1, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2LSRri killed renamable $r12, 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r12
; CHECK: bb.2.vector.body: ; CHECK: bb.2.vector.body:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r12
; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14 /* CC::al */, $noreg ; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14 /* CC::al */, $noreg
; CHECK: renamable $q0 = MVE_VLDRBU32 killed renamable $r4, 0, 0, $noreg :: (load 4 from %ir.scevgep45, align 1) ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg
; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $q0 = MVE_VLDRBU32 killed renamable $r4, 0, 1, renamable $vpr :: (load 4 from %ir.scevgep45, align 1)
; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14 /* CC::al */, $noreg ; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14 /* CC::al */, $noreg
; CHECK: renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg ; CHECK: renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $q1 = MVE_VLDRBU32 killed renamable $r4, 0, 0, $noreg :: (load 4 from %ir.scevgep23, align 1) ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg
; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $q1 = MVE_VLDRBU32 killed renamable $r4, 0, 1, renamable $vpr :: (load 4 from %ir.scevgep23, align 1)
; CHECK: renamable $q0 = nuw nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = nuw nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 0, killed $noreg :: (store 16 into %ir.lsr.iv1, align 4) ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 ; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv1, align 4)
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.for.cond.cleanup: ; CHECK: bb.3.for.cond.cleanup:
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc
bb.0.entry: bb.0.entry:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $r3, $r4, $lr liveins: $r0, $r1, $r2, $r3, $r4, $lr
frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION def_cfa_offset 8
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