[PowerPC] Fix for compiler side issue in PCRelative Local Exec

[stefanp]

Summary

Stop combining loads and stores with PPCISD::ADD_TLS before we can merge the
node with with TLS_LOCAL_EXEC_MAT_ADDR. The issue is that
TLS_LOCAL_EXEC_MAT_ADDR cannot be selected by itself and requires the previous
ADD_TLS node that goes with it. However, we sometimes try to combine ADD_TLS
with loads and stores that come after it. If this happens then the ADD_TLS is
removed and TLS_LOCAL_EXEC_MAT_ADDR cannot be selected.

While this bug fix will address the issue it my not be ideal from a performance
perspective as we may be able to add patterns to combine TLS_LOCAL_EXEC_MAT_ADDR
with ADD_TLS with the load and store that comes after it all in one. However,
this is beyond the scope of this patch.

[NeHuang]

LGTM.

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

 
 bool PPCDAGToDAGISel::tryTLSXFormStore(StoreSDNode *ST) {
   SDValue Base = ST->getBasePtr();
   if (Base.getOpcode() != PPCISD::ADD_TLS)
     return false;
   SDValue Offset = ST->getOffset();
   if (!Offset.isUndef())
     return false;
+  if (Base.getOperand(1).getOpcode() == PPCISD::TLS_LOCAL_EXEC_MAT_ADDR)
+    return false;
 
   SDLoc dl(ST);
   EVT MemVT = ST->getMemoryVT();
   EVT RegVT = ST->getValue().getValueType();
 
   unsigned Opcode;
   switch (MemVT.getSimpleVT().SimpleTy) {
     default:

llvm/test/CodeGen/PowerPC/pcrel-tls-local-exec.ll

 ; CHECK-O-NEXT:    0000000000000020:  R_PPC64_TPREL34 x
 ; CHECK-O-NEXT:    28: lwz 3, 0(3)
 ; CHECK-O-NEXT:    2c: blr
 entry:
   %0 = load i32, i32* @x, align 4
   ret i32 %0
 }
 
+define void @LocalExecValueStore(i32 %in) {
+; CHECK-S-LABEL: LocalExecValueStore:
+; CHECK-S:       # %bb.0: # %entry
+; CHECK-S-NEXT:    paddi r4, r13, x@TPREL, 0
+; CHECK-S-NEXT:    stw r3, 0(r4)
+; CHECK-S-NEXT:    blr
+; CHECK-O-LABEL: <LocalExecValueStore>:
+; CHECK-O:         40: paddi 4, 13, 0, 0
+; CHECK-O-NEXT:    0000000000000040:  R_PPC64_TPREL34 x
+; CHECK-O-NEXT:    48: stw 3, 0(4)
+; CHECK-O-NEXT:    4c: blr
+entry:
+  store i32 %in, i32* @x, align 4
+  ret void
+}
+
 define i32 @LocalExecValueLoadOffset() {
 ; CHECK-S-LABEL: LocalExecValueLoadOffset:
 ; CHECK-S:       # %bb.0: # %entry
 ; CHECK-S-NEXT:    paddi r3, r13, y@TPREL, 0
 ; CHECK-S-NEXT:    lwz r3, 12(r3)
 ; CHECK-S-NEXT:    blr
 ; CHECK-O-LABEL: <LocalExecValueLoadOffset>:
-; CHECK-O:         40: paddi 3, 13, 0, 0
-; CHECK-O-NEXT:    0000000000000040:  R_PPC64_TPREL34 y
-; CHECK-O-NEXT:    48: lwz 3, 12(3)
-; CHECK-O-NEXT:    4c: blr
+; CHECK-O:         60: paddi 3, 13, 0, 0
+; CHECK-O-NEXT:    0000000000000060:  R_PPC64_TPREL34 y
+; CHECK-O-NEXT:    68: lwz 3, 12(3)
+; CHECK-O-NEXT:    6c: blr
 entry:
   %0 = load i32, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @y, i64 0, i64 3), align 4
   ret i32 %0
 }
 
 
 define i32* @LocalExecValueLoadOffsetNoLoad() {
 ; CHECK-S-LABEL: LocalExecValueLoadOffsetNoLoad:
 ; CHECK-S:       # %bb.0: # %entry
 ; CHECK-S-NEXT:    paddi r3, r13, y@TPREL, 0
 ; CHECK-S-NEXT:    addi r3, r3, 12
 ; CHECK-S-NEXT:    blr
 ; CHECK-O-LABEL: <LocalExecValueLoadOffsetNoLoad>:
-; CHECK-O:         60: paddi 3, 13, 0, 0
-; CHECK-O-NEXT:    0000000000000060:  R_PPC64_TPREL34 y
-; CHECK-O-NEXT:    68: addi 3, 3, 12
-; CHECK-O-NEXT:    6c: blr
+; CHECK-O:         80: paddi 3, 13, 0, 0
+; CHECK-O-NEXT:    0000000000000080:  R_PPC64_TPREL34 y
+; CHECK-O-NEXT:    88: addi 3, 3, 12
+; CHECK-O-NEXT:    8c: blr
 entry:
   ret i32* getelementptr inbounds ([5 x i32], [5 x i32]* @y, i64 0, i64 3)
 }