Page MenuHomePhabricator

[AArch64] Enable Cortex-A55 schedmodel
ClosedPublic

Authored by SjoerdMeijer on Sep 21 2020, 4:12 AM.

Details

Summary

This patch enables the the Cortex-A55 model, which we can apply after we're happy with the schedmodel improvements that we still need to do.

The added LLVM-MCA test is based on all the basic A64 instruction taken from this disassembler test:

llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt

In a follow up, we can complete and fill in other instructions.

Diff Detail

Event Timeline

SjoerdMeijer created this revision.Sep 21 2020, 4:12 AM
SjoerdMeijer requested review of this revision.Sep 21 2020, 4:12 AM

Nice idea on how to write a test, even if it's not the cleanest thing I've ever seen.

It doesn't seem to have a lot of neon, but we can address that as we need to.

llvm/test/tools/llvm-mca/AArch64/Cortex/A55-basic-instructions.s
1308

Can you remove most of these msr/mrs's. We only need 1. Maybe same for dsb/dmb, they have little value in scheduling, usually.

  • pruned the test case, added comments for the different instruction categories to make the test more readable,
  • fixed latencies for the FDIV and FSQRT instructions,
  • regarding @evgeny777 's comment "WriteLD should be 3 cycles, not 4". I have kept it as it was, because in a first benchmark run I tried this regressed things a bit.
This revision is now accepted and ready to land.Nov 26 2020, 3:11 PM

Thanks. While I do have plans to look into this more soon, I think it's time to commit this thing as it has been proven to do some good, so will do that a bit later today.

This revision was automatically updated to reflect the committed changes.