This is an archive of the discontinued LLVM Phabricator instance.

Differential D87704

[AMDGPU] Reduce stack pointer alignment
Needs ReviewPublic

Authored by Flakebi on Sep 15 2020, 8:35 AM.

Details

Reviewers
t-tye
madhur13490
arsenm
Summary

HSA still needs this for OpenCL but it is not needed for other
subtargets.

Diff Detail

Event Timeline

Flakebi created this revision.Sep 15 2020, 8:35 AM
Herald added a project: Restricted Project. · View Herald TranscriptSep 15 2020, 8:35 AM
Herald added subscribers: llvm-commits, kerbowa, hiraditya and 8 others. · View Herald Transcript
Flakebi requested review of this revision.Sep 15 2020, 8:35 AM
Herald added a subscriber: wdng. · View Herald TranscriptSep 15 2020, 8:35 AM
arsenm added inline comments.Sep 15 2020, 8:38 AM
llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
944–946

This isn't a real ABI requirement and I don't think should vary based on the triple. Why do you want to re-reduce this?

Flakebi added inline comments.Sep 15 2020, 8:48 AM
llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
944–946

As far as I understand it, an alignment of 16 is needed for OpenCL but otherwise not required (as real memory addresses for lanes are aligned to 4 only anyway).
Forcing an alignment of 16 means that spilling one vgpr will reserve 1 kiB of scratch memory where only 256 Byte are needed.
If a single sgpr needs to be spilled to a vgpr (which is then in turn spilled to scratch), we need 1 kiB of memory for a 4 Byte value, which seems quite a lot to me.

Is there a downside of requiring an alignment of 4? Are there cases outside OpenCL where a higher alignment is required and the stack would need to be realigned?

arsenm added inline comments.Sep 15 2020, 8:51 AM
llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
944–946

It's not needed, it just introduces stack realignment if you have any stack objects with a higher alignment. Values up to 16-bytes are common (and 8 are very common). This isn't a property of the source language since the target ABI still has higher alignments for common types.

arsenm added inline comments.Sep 15 2020, 8:53 AM
llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
944–946

I have been thinking we should add an optimization pass to reduce the alignment of allocas if the address isn't captured

Harbormaster completed remote builds in B71749: Diff 291947.Sep 15 2020, 9:08 AM
arsenm added inline comments.Sep 16 2020, 10:24 AM
llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
944–946

To be clear, reducing this back to 4 (I had it at 4 originally) may be a good plan with some optimizations, but I don't think this should vary based on the triple

Flakebi added inline comments.Oct 2 2020, 2:31 AM
llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
944–946

Thanks for the helpful explanation. I might come back to this in a while.

arsenm resigned from this revision.Nov 18 2022, 5:11 PM

I think this should be abandoned. Requiring 16-byte stack alignment doesn't require 16-byte alignment for a VGPR spill. The spill alignment requirement is only 4. This mostly matters for when stack realignment is necessary. The stack waste comes only in call frame contexts

Herald added a project: Restricted Project. · View Herald TranscriptNov 18 2022, 5:11 PM
Herald added subscribers: kosarev, foad, arsenm. · View Herald Transcript

Revision Contents

Diff 291947

llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h

Show First 20 Lines • Show All 935 Lines • ▼ Show 20 Linespublic:
} }
// Scratch is allocated in 256 dword per wave blocks for the entire // Scratch is allocated in 256 dword per wave blocks for the entire
// wavefront. When viewed from the perspecive of an arbitrary workitem, this // wavefront. When viewed from the perspecive of an arbitrary workitem, this
// is 4-byte aligned. // is 4-byte aligned.
// //
// Only 4-byte alignment is really needed to access anything. Transformations // Only 4-byte alignment is really needed to access anything. Transformations
// on the pointer value itself may rely on the alignment / known low bits of // on the pointer value itself may rely on the alignment / known low bits of
// the pointer. Set this to something above the minimum to avoid needing // the pointer. Set this to something above the minimum for HSA to avoid
// dynamic realignment in common cases. // needing dynamic realignment in common cases.
Align getStackAlignment() const { return Align(16); } Align getStackAlignment() const {
arsenmUnsubmitted
Not Done
ReplyInline Actions

This isn't a real ABI requirement and I don't think should vary based on the triple. Why do you want to re-reduce this?

arsenm: This isn't a real ABI requirement and I don't think should vary based on the triple. Why do you…
FlakebiAuthorUnsubmitted
Not Done
ReplyInline Actions

As far as I understand it, an alignment of 16 is needed for OpenCL but otherwise not required (as real memory addresses for lanes are aligned to 4 only anyway).
Forcing an alignment of 16 means that spilling one vgpr will reserve 1 kiB of scratch memory where only 256 Byte are needed.
If a single sgpr needs to be spilled to a vgpr (which is then in turn spilled to scratch), we need 1 kiB of memory for a 4 Byte value, which seems quite a lot to me.

Is there a downside of requiring an alignment of 4? Are there cases outside OpenCL where a higher alignment is required and the stack would need to be realigned?

Flakebi: As far as I understand it, an alignment of 16 is needed for OpenCL but otherwise not required…
arsenmUnsubmitted
Not Done
ReplyInline Actions

It's not needed, it just introduces stack realignment if you have any stack objects with a higher alignment. Values up to 16-bytes are common (and 8 are very common). This isn't a property of the source language since the target ABI still has higher alignments for common types.

arsenm: It's not needed, it just introduces stack realignment if you have any stack objects with a…
arsenmUnsubmitted
Not Done
ReplyInline Actions

I have been thinking we should add an optimization pass to reduce the alignment of allocas if the address isn't captured

arsenm: I have been thinking we should add an optimization pass to reduce the alignment of allocas if…
arsenmUnsubmitted
Not Done
ReplyInline Actions

To be clear, reducing this back to 4 (I had it at 4 originally) may be a good plan with some optimizations, but I don't think this should vary based on the triple

arsenm: To be clear, reducing this back to 4 (I had it at 4 originally) may be a good plan with some…
FlakebiAuthorUnsubmitted
Not Done
ReplyInline Actions

Thanks for the helpful explanation. I might come back to this in a while.

Flakebi: Thanks for the helpful explanation. I might come back to this in a while.
if (isAmdHsaOS())
return Align(16);
return Align(4);
}
bool enableMachineScheduler() const override { bool enableMachineScheduler() const override {
return true; return true;
} }
bool enableSubRegLiveness() const override { bool enableSubRegLiveness() const override {
return true; return true;
} }
▲ Show 20 Lines • Show All 465 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll

Show First 20 Lines • Show All 260 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @test_call_external_void_func_v32i32([17 x i8]) #0 {
; GFX900: $vgpr26 = COPY [[UV26]](s32) ; GFX900: $vgpr26 = COPY [[UV26]](s32)
; GFX900: $vgpr27 = COPY [[UV27]](s32) ; GFX900: $vgpr27 = COPY [[UV27]](s32)
; GFX900: $vgpr28 = COPY [[UV28]](s32) ; GFX900: $vgpr28 = COPY [[UV28]](s32)
; GFX900: $vgpr29 = COPY [[UV29]](s32) ; GFX900: $vgpr29 = COPY [[UV29]](s32)
; GFX900: $vgpr30 = COPY [[UV30]](s32) ; GFX900: $vgpr30 = COPY [[UV30]](s32)
; GFX900: [[COPY20:%[0-9]+]]:_(p5) = COPY $sp_reg ; GFX900: [[COPY20:%[0-9]+]]:_(p5) = COPY $sp_reg
; GFX900: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX900: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX900: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY20]], [[C4]](s32) ; GFX900: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY20]], [[C4]](s32)
; GFX900: G_STORE [[UV31]](s32), [[PTR_ADD1]](p5) :: (store 4 into stack, align 16, addrspace 5) ; GFX900: G_STORE [[UV31]](s32), [[PTR_ADD1]](p5) :: (store 4 into stack, addrspace 5)
; GFX900: [[COPY21:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg ; GFX900: [[COPY21:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GFX900: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY21]](<4 x s32>) ; GFX900: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY21]](<4 x s32>)
; GFX900: $sgpr4_sgpr5 = COPY [[COPY10]](p4) ; GFX900: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; GFX900: $sgpr6_sgpr7 = COPY [[COPY11]](p4) ; GFX900: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; GFX900: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4) ; GFX900: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; GFX900: $sgpr10_sgpr11 = COPY [[COPY13]](s64) ; GFX900: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
; GFX900: $sgpr12 = COPY [[COPY14]](s32) ; GFX900: $sgpr12 = COPY [[COPY14]](s32)
; GFX900: $sgpr13 = COPY [[COPY15]](s32) ; GFX900: $sgpr13 = COPY [[COPY15]](s32)
▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @test_call_external_void_func_v32i32([17 x i8]) #0 {
; GFX908: $vgpr26 = COPY [[UV26]](s32) ; GFX908: $vgpr26 = COPY [[UV26]](s32)
; GFX908: $vgpr27 = COPY [[UV27]](s32) ; GFX908: $vgpr27 = COPY [[UV27]](s32)
; GFX908: $vgpr28 = COPY [[UV28]](s32) ; GFX908: $vgpr28 = COPY [[UV28]](s32)
; GFX908: $vgpr29 = COPY [[UV29]](s32) ; GFX908: $vgpr29 = COPY [[UV29]](s32)
; GFX908: $vgpr30 = COPY [[UV30]](s32) ; GFX908: $vgpr30 = COPY [[UV30]](s32)
; GFX908: [[COPY20:%[0-9]+]]:_(p5) = COPY $sp_reg ; GFX908: [[COPY20:%[0-9]+]]:_(p5) = COPY $sp_reg
; GFX908: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX908: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX908: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY20]], [[C4]](s32) ; GFX908: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY20]], [[C4]](s32)
; GFX908: G_STORE [[UV31]](s32), [[PTR_ADD1]](p5) :: (store 4 into stack, align 16, addrspace 5) ; GFX908: G_STORE [[UV31]](s32), [[PTR_ADD1]](p5) :: (store 4 into stack, addrspace 5)
; GFX908: [[COPY21:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg ; GFX908: [[COPY21:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GFX908: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY21]](<4 x s32>) ; GFX908: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY21]](<4 x s32>)
; GFX908: $sgpr4_sgpr5 = COPY [[COPY10]](p4) ; GFX908: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; GFX908: $sgpr6_sgpr7 = COPY [[COPY11]](p4) ; GFX908: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; GFX908: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4) ; GFX908: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; GFX908: $sgpr10_sgpr11 = COPY [[COPY13]](s64) ; GFX908: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
; GFX908: $sgpr12 = COPY [[COPY14]](s32) ; GFX908: $sgpr12 = COPY [[COPY14]](s32)
; GFX908: $sgpr13 = COPY [[COPY15]](s32) ; GFX908: $sgpr13 = COPY [[COPY15]](s32)
▲ Show 20 Lines • Show All 112 Lines • ▼ Show 20 Linesdefine void @test_func_call_external_void_func_v32i32([17 x i8]) #0 {
; GFX900: $vgpr26 = COPY [[UV26]](s32) ; GFX900: $vgpr26 = COPY [[UV26]](s32)
; GFX900: $vgpr27 = COPY [[UV27]](s32) ; GFX900: $vgpr27 = COPY [[UV27]](s32)
; GFX900: $vgpr28 = COPY [[UV28]](s32) ; GFX900: $vgpr28 = COPY [[UV28]](s32)
; GFX900: $vgpr29 = COPY [[UV29]](s32) ; GFX900: $vgpr29 = COPY [[UV29]](s32)
; GFX900: $vgpr30 = COPY [[UV30]](s32) ; GFX900: $vgpr30 = COPY [[UV30]](s32)
; GFX900: [[COPY34:%[0-9]+]]:_(p5) = COPY $sgpr32 ; GFX900: [[COPY34:%[0-9]+]]:_(p5) = COPY $sgpr32
; GFX900: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX900: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX900: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY34]], [[C1]](s32) ; GFX900: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY34]], [[C1]](s32)
; GFX900: G_STORE [[UV31]](s32), [[PTR_ADD]](p5) :: (store 4 into stack, align 16, addrspace 5) ; GFX900: G_STORE [[UV31]](s32), [[PTR_ADD]](p5) :: (store 4 into stack, addrspace 5)
; GFX900: [[COPY35:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3 ; GFX900: [[COPY35:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
; GFX900: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY35]](<4 x s32>) ; GFX900: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY35]](<4 x s32>)
; GFX900: $sgpr4_sgpr5 = COPY [[COPY26]](p4) ; GFX900: $sgpr4_sgpr5 = COPY [[COPY26]](p4)
; GFX900: $sgpr6_sgpr7 = COPY [[COPY27]](p4) ; GFX900: $sgpr6_sgpr7 = COPY [[COPY27]](p4)
; GFX900: $sgpr8_sgpr9 = COPY [[COPY28]](p4) ; GFX900: $sgpr8_sgpr9 = COPY [[COPY28]](p4)
; GFX900: $sgpr10_sgpr11 = COPY [[COPY29]](s64) ; GFX900: $sgpr10_sgpr11 = COPY [[COPY29]](s64)
; GFX900: $sgpr12 = COPY [[COPY30]](s32) ; GFX900: $sgpr12 = COPY [[COPY30]](s32)
; GFX900: $sgpr13 = COPY [[COPY31]](s32) ; GFX900: $sgpr13 = COPY [[COPY31]](s32)
▲ Show 20 Lines • Show All 108 Lines • ▼ Show 20 Linesdefine void @test_func_call_external_void_func_v32i32([17 x i8]) #0 {
; GFX908: $vgpr26 = COPY [[UV26]](s32) ; GFX908: $vgpr26 = COPY [[UV26]](s32)
; GFX908: $vgpr27 = COPY [[UV27]](s32) ; GFX908: $vgpr27 = COPY [[UV27]](s32)
; GFX908: $vgpr28 = COPY [[UV28]](s32) ; GFX908: $vgpr28 = COPY [[UV28]](s32)
; GFX908: $vgpr29 = COPY [[UV29]](s32) ; GFX908: $vgpr29 = COPY [[UV29]](s32)
; GFX908: $vgpr30 = COPY [[UV30]](s32) ; GFX908: $vgpr30 = COPY [[UV30]](s32)
; GFX908: [[COPY34:%[0-9]+]]:_(p5) = COPY $sgpr32 ; GFX908: [[COPY34:%[0-9]+]]:_(p5) = COPY $sgpr32
; GFX908: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX908: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX908: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY34]], [[C1]](s32) ; GFX908: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY34]], [[C1]](s32)
; GFX908: G_STORE [[UV31]](s32), [[PTR_ADD]](p5) :: (store 4 into stack, align 16, addrspace 5) ; GFX908: G_STORE [[UV31]](s32), [[PTR_ADD]](p5) :: (store 4 into stack, addrspace 5)
; GFX908: [[COPY35:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3 ; GFX908: [[COPY35:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
; GFX908: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY35]](<4 x s32>) ; GFX908: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY35]](<4 x s32>)
; GFX908: $sgpr4_sgpr5 = COPY [[COPY26]](p4) ; GFX908: $sgpr4_sgpr5 = COPY [[COPY26]](p4)
; GFX908: $sgpr6_sgpr7 = COPY [[COPY27]](p4) ; GFX908: $sgpr6_sgpr7 = COPY [[COPY27]](p4)
; GFX908: $sgpr8_sgpr9 = COPY [[COPY28]](p4) ; GFX908: $sgpr8_sgpr9 = COPY [[COPY28]](p4)
; GFX908: $sgpr10_sgpr11 = COPY [[COPY29]](s64) ; GFX908: $sgpr10_sgpr11 = COPY [[COPY29]](s64)
; GFX908: $sgpr12 = COPY [[COPY30]](s32) ; GFX908: $sgpr12 = COPY [[COPY30]](s32)
; GFX908: $sgpr13 = COPY [[COPY31]](s32) ; GFX908: $sgpr13 = COPY [[COPY31]](s32)
▲ Show 20 Lines • Show All 631 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 2,383 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @test_call_external_void_func_v63i16() #0 {
; CHECK: $vgpr26 = COPY [[UV26]](<2 x s16>) ; CHECK: $vgpr26 = COPY [[UV26]](<2 x s16>)
; CHECK: $vgpr27 = COPY [[UV27]](<2 x s16>) ; CHECK: $vgpr27 = COPY [[UV27]](<2 x s16>)
; CHECK: $vgpr28 = COPY [[UV28]](<2 x s16>) ; CHECK: $vgpr28 = COPY [[UV28]](<2 x s16>)
; CHECK: $vgpr29 = COPY [[UV29]](<2 x s16>) ; CHECK: $vgpr29 = COPY [[UV29]](<2 x s16>)
; CHECK: $vgpr30 = COPY [[UV30]](<2 x s16>) ; CHECK: $vgpr30 = COPY [[UV30]](<2 x s16>)
; CHECK: [[COPY20:%[0-9]+]]:_(p5) = COPY $sp_reg ; CHECK: [[COPY20:%[0-9]+]]:_(p5) = COPY $sp_reg
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY20]], [[C3]](s32) ; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY20]], [[C3]](s32)
; CHECK: G_STORE [[UV31]](<2 x s16>), [[PTR_ADD1]](p5) :: (store 4 into stack, align 16, addrspace 5) ; CHECK: G_STORE [[UV31]](<2 x s16>), [[PTR_ADD1]](p5) :: (store 4 into stack, addrspace 5)
; CHECK: [[COPY21:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg ; CHECK: [[COPY21:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY21]](<4 x s32>) ; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY21]](<4 x s32>)
; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4) ; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4) ; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; CHECK: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4) ; CHECK: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; CHECK: $sgpr10_sgpr11 = COPY [[COPY13]](s64) ; CHECK: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
; CHECK: $sgpr12 = COPY [[COPY14]](s32) ; CHECK: $sgpr12 = COPY [[COPY14]](s32)
; CHECK: $sgpr13 = COPY [[COPY15]](s32) ; CHECK: $sgpr13 = COPY [[COPY15]](s32)
▲ Show 20 Lines • Show All 75 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @test_call_external_void_func_v65i16() #0 {
; CHECK: $vgpr26 = COPY [[UV26]](<2 x s16>) ; CHECK: $vgpr26 = COPY [[UV26]](<2 x s16>)
; CHECK: $vgpr27 = COPY [[UV27]](<2 x s16>) ; CHECK: $vgpr27 = COPY [[UV27]](<2 x s16>)
; CHECK: $vgpr28 = COPY [[UV28]](<2 x s16>) ; CHECK: $vgpr28 = COPY [[UV28]](<2 x s16>)
; CHECK: $vgpr29 = COPY [[UV29]](<2 x s16>) ; CHECK: $vgpr29 = COPY [[UV29]](<2 x s16>)
; CHECK: $vgpr30 = COPY [[UV30]](<2 x s16>) ; CHECK: $vgpr30 = COPY [[UV30]](<2 x s16>)
; CHECK: [[COPY20:%[0-9]+]]:_(p5) = COPY $sp_reg ; CHECK: [[COPY20:%[0-9]+]]:_(p5) = COPY $sp_reg
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY20]], [[C3]](s32) ; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY20]], [[C3]](s32)
; CHECK: G_STORE [[UV31]](<2 x s16>), [[PTR_ADD1]](p5) :: (store 4 into stack, align 16, addrspace 5) ; CHECK: G_STORE [[UV31]](<2 x s16>), [[PTR_ADD1]](p5) :: (store 4 into stack, addrspace 5)
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY20]], [[C4]](s32) ; CHECK: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY20]], [[C4]](s32)
; CHECK: G_STORE [[UV32]](<2 x s16>), [[PTR_ADD2]](p5) :: (store 4 into stack + 4, addrspace 5) ; CHECK: G_STORE [[UV32]](<2 x s16>), [[PTR_ADD2]](p5) :: (store 4 into stack + 4, addrspace 5)
; CHECK: [[COPY21:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg ; CHECK: [[COPY21:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY21]](<4 x s32>) ; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY21]](<4 x s32>)
; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4) ; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4) ; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; CHECK: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4) ; CHECK: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
▲ Show 20 Lines • Show All 76 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @test_call_external_void_func_v66i16() #0 {
; CHECK: $vgpr26 = COPY [[UV26]](<2 x s16>) ; CHECK: $vgpr26 = COPY [[UV26]](<2 x s16>)
; CHECK: $vgpr27 = COPY [[UV27]](<2 x s16>) ; CHECK: $vgpr27 = COPY [[UV27]](<2 x s16>)
; CHECK: $vgpr28 = COPY [[UV28]](<2 x s16>) ; CHECK: $vgpr28 = COPY [[UV28]](<2 x s16>)
; CHECK: $vgpr29 = COPY [[UV29]](<2 x s16>) ; CHECK: $vgpr29 = COPY [[UV29]](<2 x s16>)
; CHECK: $vgpr30 = COPY [[UV30]](<2 x s16>) ; CHECK: $vgpr30 = COPY [[UV30]](<2 x s16>)
; CHECK: [[COPY20:%[0-9]+]]:_(p5) = COPY $sp_reg ; CHECK: [[COPY20:%[0-9]+]]:_(p5) = COPY $sp_reg
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY20]], [[C3]](s32) ; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY20]], [[C3]](s32)
; CHECK: G_STORE [[UV31]](<2 x s16>), [[PTR_ADD1]](p5) :: (store 4 into stack, align 16, addrspace 5) ; CHECK: G_STORE [[UV31]](<2 x s16>), [[PTR_ADD1]](p5) :: (store 4 into stack, addrspace 5)
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY20]], [[C4]](s32) ; CHECK: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY20]], [[C4]](s32)
; CHECK: G_STORE [[UV32]](<2 x s16>), [[PTR_ADD2]](p5) :: (store 4 into stack + 4, addrspace 5) ; CHECK: G_STORE [[UV32]](<2 x s16>), [[PTR_ADD2]](p5) :: (store 4 into stack + 4, addrspace 5)
; CHECK: [[COPY21:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg ; CHECK: [[COPY21:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY21]](<4 x s32>) ; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY21]](<4 x s32>)
; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4) ; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4) ; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; CHECK: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4) ; CHECK: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
▲ Show 20 Lines • Show All 758 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @test_call_external_void_func_v32i32() #0 {
; CHECK: $vgpr26 = COPY [[UV26]](s32) ; CHECK: $vgpr26 = COPY [[UV26]](s32)
; CHECK: $vgpr27 = COPY [[UV27]](s32) ; CHECK: $vgpr27 = COPY [[UV27]](s32)
; CHECK: $vgpr28 = COPY [[UV28]](s32) ; CHECK: $vgpr28 = COPY [[UV28]](s32)
; CHECK: $vgpr29 = COPY [[UV29]](s32) ; CHECK: $vgpr29 = COPY [[UV29]](s32)
; CHECK: $vgpr30 = COPY [[UV30]](s32) ; CHECK: $vgpr30 = COPY [[UV30]](s32)
; CHECK: [[COPY20:%[0-9]+]]:_(p5) = COPY $sp_reg ; CHECK: [[COPY20:%[0-9]+]]:_(p5) = COPY $sp_reg
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY20]], [[C3]](s32) ; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY20]], [[C3]](s32)
; CHECK: G_STORE [[UV31]](s32), [[PTR_ADD1]](p5) :: (store 4 into stack, align 16, addrspace 5) ; CHECK: G_STORE [[UV31]](s32), [[PTR_ADD1]](p5) :: (store 4 into stack, addrspace 5)
; CHECK: [[COPY21:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg ; CHECK: [[COPY21:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY21]](<4 x s32>) ; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY21]](<4 x s32>)
; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4) ; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4) ; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; CHECK: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4) ; CHECK: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; CHECK: $sgpr10_sgpr11 = COPY [[COPY13]](s64) ; CHECK: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
; CHECK: $sgpr12 = COPY [[COPY14]](s32) ; CHECK: $sgpr12 = COPY [[COPY14]](s32)
; CHECK: $sgpr13 = COPY [[COPY15]](s32) ; CHECK: $sgpr13 = COPY [[COPY15]](s32)
▲ Show 20 Lines • Show All 78 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @test_call_external_void_func_v32i32_i32(i32) #0 {
; CHECK: $vgpr26 = COPY [[UV26]](s32) ; CHECK: $vgpr26 = COPY [[UV26]](s32)
; CHECK: $vgpr27 = COPY [[UV27]](s32) ; CHECK: $vgpr27 = COPY [[UV27]](s32)
; CHECK: $vgpr28 = COPY [[UV28]](s32) ; CHECK: $vgpr28 = COPY [[UV28]](s32)
; CHECK: $vgpr29 = COPY [[UV29]](s32) ; CHECK: $vgpr29 = COPY [[UV29]](s32)
; CHECK: $vgpr30 = COPY [[UV30]](s32) ; CHECK: $vgpr30 = COPY [[UV30]](s32)
; CHECK: [[COPY20:%[0-9]+]]:_(p5) = COPY $sp_reg ; CHECK: [[COPY20:%[0-9]+]]:_(p5) = COPY $sp_reg
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY20]], [[C3]](s32) ; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY20]], [[C3]](s32)
; CHECK: G_STORE [[UV31]](s32), [[PTR_ADD1]](p5) :: (store 4 into stack, align 16, addrspace 5) ; CHECK: G_STORE [[UV31]](s32), [[PTR_ADD1]](p5) :: (store 4 into stack, addrspace 5)
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY20]], [[C4]](s32) ; CHECK: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY20]], [[C4]](s32)
; CHECK: G_STORE [[LOAD2]](s32), [[PTR_ADD2]](p5) :: (store 4 into stack + 4, addrspace 5) ; CHECK: G_STORE [[LOAD2]](s32), [[PTR_ADD2]](p5) :: (store 4 into stack + 4, addrspace 5)
; CHECK: [[COPY21:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg ; CHECK: [[COPY21:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY21]](<4 x s32>) ; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY21]](<4 x s32>)
; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4) ; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4) ; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; CHECK: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4) ; CHECK: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
▲ Show 20 Lines • Show All 85 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @test_call_external_void_func_v32i32_i8_i8_i16() #0 {
; CHECK: $vgpr26 = COPY [[UV26]](s32) ; CHECK: $vgpr26 = COPY [[UV26]](s32)
; CHECK: $vgpr27 = COPY [[UV27]](s32) ; CHECK: $vgpr27 = COPY [[UV27]](s32)
; CHECK: $vgpr28 = COPY [[UV28]](s32) ; CHECK: $vgpr28 = COPY [[UV28]](s32)
; CHECK: $vgpr29 = COPY [[UV29]](s32) ; CHECK: $vgpr29 = COPY [[UV29]](s32)
; CHECK: $vgpr30 = COPY [[UV30]](s32) ; CHECK: $vgpr30 = COPY [[UV30]](s32)
; CHECK: [[COPY21:%[0-9]+]]:_(p5) = COPY $sp_reg ; CHECK: [[COPY21:%[0-9]+]]:_(p5) = COPY $sp_reg
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY21]], [[C3]](s32) ; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY21]], [[C3]](s32)
; CHECK: G_STORE [[UV31]](s32), [[PTR_ADD1]](p5) :: (store 4 into stack, align 16, addrspace 5) ; CHECK: G_STORE [[UV31]](s32), [[PTR_ADD1]](p5) :: (store 4 into stack, addrspace 5)
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY21]], [[C4]](s32) ; CHECK: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY21]], [[C4]](s32)
; CHECK: G_STORE [[ANYEXT]](s32), [[PTR_ADD2]](p5) :: (store 4 into stack + 4, addrspace 5) ; CHECK: G_STORE [[ANYEXT]](s32), [[PTR_ADD2]](p5) :: (store 4 into stack + 4, addrspace 5)
; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[PTR_ADD3:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY21]], [[C5]](s32) ; CHECK: [[PTR_ADD3:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY21]], [[C5]](s32)
; CHECK: G_STORE [[ANYEXT]](s32), [[PTR_ADD3]](p5) :: (store 4 into stack + 8, align 8, addrspace 5) ; CHECK: G_STORE [[ANYEXT]](s32), [[PTR_ADD3]](p5) :: (store 4 into stack + 8, addrspace 5)
; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 12 ; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
; CHECK: [[PTR_ADD4:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY21]], [[C6]](s32) ; CHECK: [[PTR_ADD4:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY21]], [[C6]](s32)
; CHECK: G_STORE [[ANYEXT1]](s32), [[PTR_ADD4]](p5) :: (store 4 into stack + 12, addrspace 5) ; CHECK: G_STORE [[ANYEXT1]](s32), [[PTR_ADD4]](p5) :: (store 4 into stack + 12, addrspace 5)
; CHECK: [[COPY22:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg ; CHECK: [[COPY22:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY22]](<4 x s32>) ; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY22]](<4 x s32>)
; CHECK: $sgpr4_sgpr5 = COPY [[COPY11]](p4) ; CHECK: $sgpr4_sgpr5 = COPY [[COPY11]](p4)
; CHECK: $sgpr6_sgpr7 = COPY [[COPY12]](p4) ; CHECK: $sgpr6_sgpr7 = COPY [[COPY12]](p4)
; CHECK: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4) ; CHECK: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
▲ Show 20 Lines • Show All 85 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @test_call_external_void_func_v32i32_p3_p5() #0 {
; CHECK: $vgpr26 = COPY [[UV26]](s32) ; CHECK: $vgpr26 = COPY [[UV26]](s32)
; CHECK: $vgpr27 = COPY [[UV27]](s32) ; CHECK: $vgpr27 = COPY [[UV27]](s32)
; CHECK: $vgpr28 = COPY [[UV28]](s32) ; CHECK: $vgpr28 = COPY [[UV28]](s32)
; CHECK: $vgpr29 = COPY [[UV29]](s32) ; CHECK: $vgpr29 = COPY [[UV29]](s32)
; CHECK: $vgpr30 = COPY [[UV30]](s32) ; CHECK: $vgpr30 = COPY [[UV30]](s32)
; CHECK: [[COPY21:%[0-9]+]]:_(p5) = COPY $sp_reg ; CHECK: [[COPY21:%[0-9]+]]:_(p5) = COPY $sp_reg
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY21]], [[C3]](s32) ; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY21]], [[C3]](s32)
; CHECK: G_STORE [[UV31]](s32), [[PTR_ADD1]](p5) :: (store 4 into stack, align 16, addrspace 5) ; CHECK: G_STORE [[UV31]](s32), [[PTR_ADD1]](p5) :: (store 4 into stack, addrspace 5)
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY21]], [[C4]](s32) ; CHECK: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY21]], [[C4]](s32)
; CHECK: G_STORE [[LOAD2]](p3), [[PTR_ADD2]](p5) :: (store 4 into stack + 4, addrspace 5) ; CHECK: G_STORE [[LOAD2]](p3), [[PTR_ADD2]](p5) :: (store 4 into stack + 4, addrspace 5)
; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[PTR_ADD3:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY21]], [[C5]](s32) ; CHECK: [[PTR_ADD3:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY21]], [[C5]](s32)
; CHECK: G_STORE [[LOAD3]](p5), [[PTR_ADD3]](p5) :: (store 4 into stack + 8, align 8, addrspace 5) ; CHECK: G_STORE [[LOAD3]](p5), [[PTR_ADD3]](p5) :: (store 4 into stack + 8, addrspace 5)
; CHECK: [[COPY22:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg ; CHECK: [[COPY22:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY22]](<4 x s32>) ; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY22]](<4 x s32>)
; CHECK: $sgpr4_sgpr5 = COPY [[COPY11]](p4) ; CHECK: $sgpr4_sgpr5 = COPY [[COPY11]](p4)
; CHECK: $sgpr6_sgpr7 = COPY [[COPY12]](p4) ; CHECK: $sgpr6_sgpr7 = COPY [[COPY12]](p4)
; CHECK: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4) ; CHECK: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)
; CHECK: $sgpr10_sgpr11 = COPY [[COPY14]](s64) ; CHECK: $sgpr10_sgpr11 = COPY [[COPY14]](s64)
; CHECK: $sgpr12 = COPY [[COPY15]](s32) ; CHECK: $sgpr12 = COPY [[COPY15]](s32)
; CHECK: $sgpr13 = COPY [[COPY16]](s32) ; CHECK: $sgpr13 = COPY [[COPY16]](s32)
▲ Show 20 Lines • Show All 111 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @test_call_external_void_func_byval_struct_i8_i32() #0 {
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]] ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]
; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 20 ; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C5]](s32) ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C5]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]] ; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; CHECK: [[COPY20:%[0-9]+]]:_(p5) = COPY $sp_reg ; CHECK: [[COPY20:%[0-9]+]]:_(p5) = COPY $sp_reg
; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY20]], [[C6]](s32) ; CHECK: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY20]], [[C6]](s32)
; CHECK: G_STORE [[FRAME_INDEX]](p5), [[PTR_ADD2]](p5) :: (store 4 into stack, align 16, addrspace 5) ; CHECK: G_STORE [[FRAME_INDEX]](p5), [[PTR_ADD2]](p5) :: (store 4 into stack, addrspace 5)
; CHECK: [[COPY21:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg ; CHECK: [[COPY21:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY21]](<4 x s32>) ; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY21]](<4 x s32>)
; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4) ; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4) ; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; CHECK: $sgpr8_sgpr9 = COPY [[PTR_ADD1]](p4) ; CHECK: $sgpr8_sgpr9 = COPY [[PTR_ADD1]](p4)
; CHECK: $sgpr10_sgpr11 = COPY [[COPY13]](s64) ; CHECK: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
; CHECK: $sgpr12 = COPY [[COPY14]](s32) ; CHECK: $sgpr12 = COPY [[COPY14]](s32)
; CHECK: $sgpr13 = COPY [[COPY15]](s32) ; CHECK: $sgpr13 = COPY [[COPY15]](s32)
▲ Show 20 Lines • Show All 465 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @stack_passed_arg_alignment_v32i32_f64(<32 x i32> %val, double %tmp) #0 {
; CHECK: $vgpr26 = COPY [[UV26]](s32) ; CHECK: $vgpr26 = COPY [[UV26]](s32)
; CHECK: $vgpr27 = COPY [[UV27]](s32) ; CHECK: $vgpr27 = COPY [[UV27]](s32)
; CHECK: $vgpr28 = COPY [[UV28]](s32) ; CHECK: $vgpr28 = COPY [[UV28]](s32)
; CHECK: $vgpr29 = COPY [[UV29]](s32) ; CHECK: $vgpr29 = COPY [[UV29]](s32)
; CHECK: $vgpr30 = COPY [[UV30]](s32) ; CHECK: $vgpr30 = COPY [[UV30]](s32)
; CHECK: [[COPY20:%[0-9]+]]:_(p5) = COPY $sp_reg ; CHECK: [[COPY20:%[0-9]+]]:_(p5) = COPY $sp_reg
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY20]], [[C4]](s32) ; CHECK: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY20]], [[C4]](s32)
; CHECK: G_STORE [[UV31]](s32), [[PTR_ADD2]](p5) :: (store 4 into stack, align 16, addrspace 5) ; CHECK: G_STORE [[UV31]](s32), [[PTR_ADD2]](p5) :: (store 4 into stack, addrspace 5)
; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 ; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK: [[PTR_ADD3:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY20]], [[C5]](s32) ; CHECK: [[PTR_ADD3:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY20]], [[C5]](s32)
; CHECK: G_STORE [[UV32]](s32), [[PTR_ADD3]](p5) :: (store 4 into stack + 4, addrspace 5) ; CHECK: G_STORE [[UV32]](s32), [[PTR_ADD3]](p5) :: (store 4 into stack + 4, addrspace 5)
; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[PTR_ADD4:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY20]], [[C6]](s32) ; CHECK: [[PTR_ADD4:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY20]], [[C6]](s32)
; CHECK: G_STORE [[UV33]](s32), [[PTR_ADD4]](p5) :: (store 4 into stack + 8, align 8, addrspace 5) ; CHECK: G_STORE [[UV33]](s32), [[PTR_ADD4]](p5) :: (store 4 into stack + 8, addrspace 5)
; CHECK: [[COPY21:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg ; CHECK: [[COPY21:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY21]](<4 x s32>) ; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY21]](<4 x s32>)
; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4) ; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4) ; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
; CHECK: $sgpr8_sgpr9 = COPY [[PTR_ADD1]](p4) ; CHECK: $sgpr8_sgpr9 = COPY [[PTR_ADD1]](p4)
; CHECK: $sgpr10_sgpr11 = COPY [[COPY13]](s64) ; CHECK: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
; CHECK: $sgpr12 = COPY [[COPY14]](s32) ; CHECK: $sgpr12 = COPY [[COPY14]](s32)
; CHECK: $sgpr13 = COPY [[COPY15]](s32) ; CHECK: $sgpr13 = COPY [[COPY15]](s32)
▲ Show 20 Lines • Show All 99 Lines • ▼ Show 20 Linesdefine void @stack_12xv3i32() #0 {
; CHECK: $vgpr26 = COPY [[UV26]](s32) ; CHECK: $vgpr26 = COPY [[UV26]](s32)
; CHECK: $vgpr27 = COPY [[UV27]](s32) ; CHECK: $vgpr27 = COPY [[UV27]](s32)
; CHECK: $vgpr28 = COPY [[UV28]](s32) ; CHECK: $vgpr28 = COPY [[UV28]](s32)
; CHECK: $vgpr29 = COPY [[UV29]](s32) ; CHECK: $vgpr29 = COPY [[UV29]](s32)
; CHECK: $vgpr30 = COPY [[UV30]](s32) ; CHECK: $vgpr30 = COPY [[UV30]](s32)
; CHECK: [[COPY17:%[0-9]+]]:_(p5) = COPY $sgpr32 ; CHECK: [[COPY17:%[0-9]+]]:_(p5) = COPY $sgpr32
; CHECK: [[C16:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C16:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C16]](s32) ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C16]](s32)
; CHECK: G_STORE [[UV31]](s32), [[PTR_ADD]](p5) :: (store 4 into stack, align 16, addrspace 5) ; CHECK: G_STORE [[UV31]](s32), [[PTR_ADD]](p5) :: (store 4 into stack, addrspace 5)
; CHECK: [[C17:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 ; CHECK: [[C17:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C17]](s32) ; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C17]](s32)
; CHECK: G_STORE [[UV32]](s32), [[PTR_ADD1]](p5) :: (store 4 into stack + 4, addrspace 5) ; CHECK: G_STORE [[UV32]](s32), [[PTR_ADD1]](p5) :: (store 4 into stack + 4, addrspace 5)
; CHECK: [[C18:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; CHECK: [[C18:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C18]](s32) ; CHECK: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C18]](s32)
; CHECK: G_STORE [[UV33]](s32), [[PTR_ADD2]](p5) :: (store 4 into stack + 8, align 8, addrspace 5) ; CHECK: G_STORE [[UV33]](s32), [[PTR_ADD2]](p5) :: (store 4 into stack + 8, addrspace 5)
; CHECK: [[C19:%[0-9]+]]:_(s32) = G_CONSTANT i32 12 ; CHECK: [[C19:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
; CHECK: [[PTR_ADD3:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C19]](s32) ; CHECK: [[PTR_ADD3:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C19]](s32)
; CHECK: G_STORE [[UV34]](s32), [[PTR_ADD3]](p5) :: (store 4 into stack + 12, addrspace 5) ; CHECK: G_STORE [[UV34]](s32), [[PTR_ADD3]](p5) :: (store 4 into stack + 12, addrspace 5)
; CHECK: [[C20:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK: [[C20:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[PTR_ADD4:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C20]](s32) ; CHECK: [[PTR_ADD4:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C20]](s32)
; CHECK: G_STORE [[UV35]](s32), [[PTR_ADD4]](p5) :: (store 4 into stack + 16, align 16, addrspace 5) ; CHECK: G_STORE [[UV35]](s32), [[PTR_ADD4]](p5) :: (store 4 into stack + 16, addrspace 5)
; CHECK: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3 ; CHECK: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>) ; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>)
; CHECK: $sgpr4_sgpr5 = COPY [[COPY9]](p4) ; CHECK: $sgpr4_sgpr5 = COPY [[COPY9]](p4)
; CHECK: $sgpr6_sgpr7 = COPY [[COPY10]](p4) ; CHECK: $sgpr6_sgpr7 = COPY [[COPY10]](p4)
; CHECK: $sgpr8_sgpr9 = COPY [[COPY11]](p4) ; CHECK: $sgpr8_sgpr9 = COPY [[COPY11]](p4)
; CHECK: $sgpr10_sgpr11 = COPY [[COPY12]](s64) ; CHECK: $sgpr10_sgpr11 = COPY [[COPY12]](s64)
; CHECK: $sgpr12 = COPY [[COPY13]](s32) ; CHECK: $sgpr12 = COPY [[COPY13]](s32)
; CHECK: $sgpr13 = COPY [[COPY14]](s32) ; CHECK: $sgpr13 = COPY [[COPY14]](s32)
▲ Show 20 Lines • Show All 112 Lines • ▼ Show 20 Linesdefine void @stack_12xv3f32() #0 {
; CHECK: $vgpr26 = COPY [[UV26]](s32) ; CHECK: $vgpr26 = COPY [[UV26]](s32)
; CHECK: $vgpr27 = COPY [[UV27]](s32) ; CHECK: $vgpr27 = COPY [[UV27]](s32)
; CHECK: $vgpr28 = COPY [[UV28]](s32) ; CHECK: $vgpr28 = COPY [[UV28]](s32)
; CHECK: $vgpr29 = COPY [[UV29]](s32) ; CHECK: $vgpr29 = COPY [[UV29]](s32)
; CHECK: $vgpr30 = COPY [[UV30]](s32) ; CHECK: $vgpr30 = COPY [[UV30]](s32)
; CHECK: [[COPY17:%[0-9]+]]:_(p5) = COPY $sgpr32 ; CHECK: [[COPY17:%[0-9]+]]:_(p5) = COPY $sgpr32
; CHECK: [[C16:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C16:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C16]](s32) ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C16]](s32)
; CHECK: G_STORE [[UV31]](s32), [[PTR_ADD]](p5) :: (store 4 into stack, align 16, addrspace 5) ; CHECK: G_STORE [[UV31]](s32), [[PTR_ADD]](p5) :: (store 4 into stack, addrspace 5)
; CHECK: [[C17:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 ; CHECK: [[C17:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C17]](s32) ; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C17]](s32)
; CHECK: G_STORE [[UV32]](s32), [[PTR_ADD1]](p5) :: (store 4 into stack + 4, addrspace 5) ; CHECK: G_STORE [[UV32]](s32), [[PTR_ADD1]](p5) :: (store 4 into stack + 4, addrspace 5)
; CHECK: [[C18:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; CHECK: [[C18:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C18]](s32) ; CHECK: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C18]](s32)
; CHECK: G_STORE [[UV33]](s32), [[PTR_ADD2]](p5) :: (store 4 into stack + 8, align 8, addrspace 5) ; CHECK: G_STORE [[UV33]](s32), [[PTR_ADD2]](p5) :: (store 4 into stack + 8, addrspace 5)
; CHECK: [[C19:%[0-9]+]]:_(s32) = G_CONSTANT i32 12 ; CHECK: [[C19:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
; CHECK: [[PTR_ADD3:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C19]](s32) ; CHECK: [[PTR_ADD3:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C19]](s32)
; CHECK: G_STORE [[UV34]](s32), [[PTR_ADD3]](p5) :: (store 4 into stack + 12, addrspace 5) ; CHECK: G_STORE [[UV34]](s32), [[PTR_ADD3]](p5) :: (store 4 into stack + 12, addrspace 5)
; CHECK: [[C20:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK: [[C20:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[PTR_ADD4:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C20]](s32) ; CHECK: [[PTR_ADD4:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C20]](s32)
; CHECK: G_STORE [[UV35]](s32), [[PTR_ADD4]](p5) :: (store 4 into stack + 16, align 16, addrspace 5) ; CHECK: G_STORE [[UV35]](s32), [[PTR_ADD4]](p5) :: (store 4 into stack + 16, addrspace 5)
; CHECK: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3 ; CHECK: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>) ; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>)
; CHECK: $sgpr4_sgpr5 = COPY [[COPY9]](p4) ; CHECK: $sgpr4_sgpr5 = COPY [[COPY9]](p4)
; CHECK: $sgpr6_sgpr7 = COPY [[COPY10]](p4) ; CHECK: $sgpr6_sgpr7 = COPY [[COPY10]](p4)
; CHECK: $sgpr8_sgpr9 = COPY [[COPY11]](p4) ; CHECK: $sgpr8_sgpr9 = COPY [[COPY11]](p4)
; CHECK: $sgpr10_sgpr11 = COPY [[COPY12]](s64) ; CHECK: $sgpr10_sgpr11 = COPY [[COPY12]](s64)
; CHECK: $sgpr12 = COPY [[COPY13]](s32) ; CHECK: $sgpr12 = COPY [[COPY13]](s32)
; CHECK: $sgpr13 = COPY [[COPY14]](s32) ; CHECK: $sgpr13 = COPY [[COPY14]](s32)
▲ Show 20 Lines • Show All 104 Lines • ▼ Show 20 Linesdefine void @stack_8xv5i32() #0 {
; CHECK: $vgpr26 = COPY [[UV26]](s32) ; CHECK: $vgpr26 = COPY [[UV26]](s32)
; CHECK: $vgpr27 = COPY [[UV27]](s32) ; CHECK: $vgpr27 = COPY [[UV27]](s32)
; CHECK: $vgpr28 = COPY [[UV28]](s32) ; CHECK: $vgpr28 = COPY [[UV28]](s32)
; CHECK: $vgpr29 = COPY [[UV29]](s32) ; CHECK: $vgpr29 = COPY [[UV29]](s32)
; CHECK: $vgpr30 = COPY [[UV30]](s32) ; CHECK: $vgpr30 = COPY [[UV30]](s32)
; CHECK: [[COPY17:%[0-9]+]]:_(p5) = COPY $sgpr32 ; CHECK: [[COPY17:%[0-9]+]]:_(p5) = COPY $sgpr32
; CHECK: [[C16:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C16:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C16]](s32) ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C16]](s32)
; CHECK: G_STORE [[UV31]](s32), [[PTR_ADD]](p5) :: (store 4 into stack, align 16, addrspace 5) ; CHECK: G_STORE [[UV31]](s32), [[PTR_ADD]](p5) :: (store 4 into stack, addrspace 5)
; CHECK: [[C17:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 ; CHECK: [[C17:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C17]](s32) ; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C17]](s32)
; CHECK: G_STORE [[UV32]](s32), [[PTR_ADD1]](p5) :: (store 4 into stack + 4, addrspace 5) ; CHECK: G_STORE [[UV32]](s32), [[PTR_ADD1]](p5) :: (store 4 into stack + 4, addrspace 5)
; CHECK: [[C18:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; CHECK: [[C18:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C18]](s32) ; CHECK: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C18]](s32)
; CHECK: G_STORE [[UV33]](s32), [[PTR_ADD2]](p5) :: (store 4 into stack + 8, align 8, addrspace 5) ; CHECK: G_STORE [[UV33]](s32), [[PTR_ADD2]](p5) :: (store 4 into stack + 8, addrspace 5)
; CHECK: [[C19:%[0-9]+]]:_(s32) = G_CONSTANT i32 12 ; CHECK: [[C19:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
; CHECK: [[PTR_ADD3:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C19]](s32) ; CHECK: [[PTR_ADD3:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C19]](s32)
; CHECK: G_STORE [[UV34]](s32), [[PTR_ADD3]](p5) :: (store 4 into stack + 12, addrspace 5) ; CHECK: G_STORE [[UV34]](s32), [[PTR_ADD3]](p5) :: (store 4 into stack + 12, addrspace 5)
; CHECK: [[C20:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK: [[C20:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[PTR_ADD4:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C20]](s32) ; CHECK: [[PTR_ADD4:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C20]](s32)
; CHECK: G_STORE [[UV35]](s32), [[PTR_ADD4]](p5) :: (store 4 into stack + 16, align 16, addrspace 5) ; CHECK: G_STORE [[UV35]](s32), [[PTR_ADD4]](p5) :: (store 4 into stack + 16, addrspace 5)
; CHECK: [[C21:%[0-9]+]]:_(s32) = G_CONSTANT i32 20 ; CHECK: [[C21:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; CHECK: [[PTR_ADD5:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C21]](s32) ; CHECK: [[PTR_ADD5:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C21]](s32)
; CHECK: G_STORE [[UV36]](s32), [[PTR_ADD5]](p5) :: (store 4 into stack + 20, addrspace 5) ; CHECK: G_STORE [[UV36]](s32), [[PTR_ADD5]](p5) :: (store 4 into stack + 20, addrspace 5)
; CHECK: [[C22:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 ; CHECK: [[C22:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C22]](s32) ; CHECK: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C22]](s32)
; CHECK: G_STORE [[UV37]](s32), [[PTR_ADD6]](p5) :: (store 4 into stack + 24, align 8, addrspace 5) ; CHECK: G_STORE [[UV37]](s32), [[PTR_ADD6]](p5) :: (store 4 into stack + 24, addrspace 5)
; CHECK: [[C23:%[0-9]+]]:_(s32) = G_CONSTANT i32 28 ; CHECK: [[C23:%[0-9]+]]:_(s32) = G_CONSTANT i32 28
; CHECK: [[PTR_ADD7:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C23]](s32) ; CHECK: [[PTR_ADD7:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C23]](s32)
; CHECK: G_STORE [[UV38]](s32), [[PTR_ADD7]](p5) :: (store 4 into stack + 28, addrspace 5) ; CHECK: G_STORE [[UV38]](s32), [[PTR_ADD7]](p5) :: (store 4 into stack + 28, addrspace 5)
; CHECK: [[C24:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 ; CHECK: [[C24:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; CHECK: [[PTR_ADD8:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C24]](s32) ; CHECK: [[PTR_ADD8:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C24]](s32)
; CHECK: G_STORE [[UV39]](s32), [[PTR_ADD8]](p5) :: (store 4 into stack + 32, align 16, addrspace 5) ; CHECK: G_STORE [[UV39]](s32), [[PTR_ADD8]](p5) :: (store 4 into stack + 32, addrspace 5)
; CHECK: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3 ; CHECK: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>) ; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>)
; CHECK: $sgpr4_sgpr5 = COPY [[COPY9]](p4) ; CHECK: $sgpr4_sgpr5 = COPY [[COPY9]](p4)
; CHECK: $sgpr6_sgpr7 = COPY [[COPY10]](p4) ; CHECK: $sgpr6_sgpr7 = COPY [[COPY10]](p4)
; CHECK: $sgpr8_sgpr9 = COPY [[COPY11]](p4) ; CHECK: $sgpr8_sgpr9 = COPY [[COPY11]](p4)
; CHECK: $sgpr10_sgpr11 = COPY [[COPY12]](s64) ; CHECK: $sgpr10_sgpr11 = COPY [[COPY12]](s64)
; CHECK: $sgpr12 = COPY [[COPY13]](s32) ; CHECK: $sgpr12 = COPY [[COPY13]](s32)
; CHECK: $sgpr13 = COPY [[COPY14]](s32) ; CHECK: $sgpr13 = COPY [[COPY14]](s32)
▲ Show 20 Lines • Show All 100 Lines • ▼ Show 20 Linesdefine void @stack_8xv5f32() #0 {
; CHECK: $vgpr26 = COPY [[UV26]](s32) ; CHECK: $vgpr26 = COPY [[UV26]](s32)
; CHECK: $vgpr27 = COPY [[UV27]](s32) ; CHECK: $vgpr27 = COPY [[UV27]](s32)
; CHECK: $vgpr28 = COPY [[UV28]](s32) ; CHECK: $vgpr28 = COPY [[UV28]](s32)
; CHECK: $vgpr29 = COPY [[UV29]](s32) ; CHECK: $vgpr29 = COPY [[UV29]](s32)
; CHECK: $vgpr30 = COPY [[UV30]](s32) ; CHECK: $vgpr30 = COPY [[UV30]](s32)
; CHECK: [[COPY17:%[0-9]+]]:_(p5) = COPY $sgpr32 ; CHECK: [[COPY17:%[0-9]+]]:_(p5) = COPY $sgpr32
; CHECK: [[C16:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C16:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C16]](s32) ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C16]](s32)
; CHECK: G_STORE [[UV31]](s32), [[PTR_ADD]](p5) :: (store 4 into stack, align 16, addrspace 5) ; CHECK: G_STORE [[UV31]](s32), [[PTR_ADD]](p5) :: (store 4 into stack, addrspace 5)
; CHECK: [[C17:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 ; CHECK: [[C17:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C17]](s32) ; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C17]](s32)
; CHECK: G_STORE [[UV32]](s32), [[PTR_ADD1]](p5) :: (store 4 into stack + 4, addrspace 5) ; CHECK: G_STORE [[UV32]](s32), [[PTR_ADD1]](p5) :: (store 4 into stack + 4, addrspace 5)
; CHECK: [[C18:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; CHECK: [[C18:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C18]](s32) ; CHECK: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C18]](s32)
; CHECK: G_STORE [[UV33]](s32), [[PTR_ADD2]](p5) :: (store 4 into stack + 8, align 8, addrspace 5) ; CHECK: G_STORE [[UV33]](s32), [[PTR_ADD2]](p5) :: (store 4 into stack + 8, addrspace 5)
; CHECK: [[C19:%[0-9]+]]:_(s32) = G_CONSTANT i32 12 ; CHECK: [[C19:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
; CHECK: [[PTR_ADD3:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C19]](s32) ; CHECK: [[PTR_ADD3:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C19]](s32)
; CHECK: G_STORE [[UV34]](s32), [[PTR_ADD3]](p5) :: (store 4 into stack + 12, addrspace 5) ; CHECK: G_STORE [[UV34]](s32), [[PTR_ADD3]](p5) :: (store 4 into stack + 12, addrspace 5)
; CHECK: [[C20:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK: [[C20:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[PTR_ADD4:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C20]](s32) ; CHECK: [[PTR_ADD4:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C20]](s32)
; CHECK: G_STORE [[UV35]](s32), [[PTR_ADD4]](p5) :: (store 4 into stack + 16, align 16, addrspace 5) ; CHECK: G_STORE [[UV35]](s32), [[PTR_ADD4]](p5) :: (store 4 into stack + 16, addrspace 5)
; CHECK: [[C21:%[0-9]+]]:_(s32) = G_CONSTANT i32 20 ; CHECK: [[C21:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; CHECK: [[PTR_ADD5:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C21]](s32) ; CHECK: [[PTR_ADD5:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C21]](s32)
; CHECK: G_STORE [[UV36]](s32), [[PTR_ADD5]](p5) :: (store 4 into stack + 20, addrspace 5) ; CHECK: G_STORE [[UV36]](s32), [[PTR_ADD5]](p5) :: (store 4 into stack + 20, addrspace 5)
; CHECK: [[C22:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 ; CHECK: [[C22:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C22]](s32) ; CHECK: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C22]](s32)
; CHECK: G_STORE [[UV37]](s32), [[PTR_ADD6]](p5) :: (store 4 into stack + 24, align 8, addrspace 5) ; CHECK: G_STORE [[UV37]](s32), [[PTR_ADD6]](p5) :: (store 4 into stack + 24, addrspace 5)
; CHECK: [[C23:%[0-9]+]]:_(s32) = G_CONSTANT i32 28 ; CHECK: [[C23:%[0-9]+]]:_(s32) = G_CONSTANT i32 28
; CHECK: [[PTR_ADD7:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C23]](s32) ; CHECK: [[PTR_ADD7:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C23]](s32)
; CHECK: G_STORE [[UV38]](s32), [[PTR_ADD7]](p5) :: (store 4 into stack + 28, addrspace 5) ; CHECK: G_STORE [[UV38]](s32), [[PTR_ADD7]](p5) :: (store 4 into stack + 28, addrspace 5)
; CHECK: [[C24:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 ; CHECK: [[C24:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; CHECK: [[PTR_ADD8:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C24]](s32) ; CHECK: [[PTR_ADD8:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY17]], [[C24]](s32)
; CHECK: G_STORE [[UV39]](s32), [[PTR_ADD8]](p5) :: (store 4 into stack + 32, align 16, addrspace 5) ; CHECK: G_STORE [[UV39]](s32), [[PTR_ADD8]](p5) :: (store 4 into stack + 32, addrspace 5)
; CHECK: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3 ; CHECK: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>) ; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>)
; CHECK: $sgpr4_sgpr5 = COPY [[COPY9]](p4) ; CHECK: $sgpr4_sgpr5 = COPY [[COPY9]](p4)
; CHECK: $sgpr6_sgpr7 = COPY [[COPY10]](p4) ; CHECK: $sgpr6_sgpr7 = COPY [[COPY10]](p4)
; CHECK: $sgpr8_sgpr9 = COPY [[COPY11]](p4) ; CHECK: $sgpr8_sgpr9 = COPY [[COPY11]](p4)
; CHECK: $sgpr10_sgpr11 = COPY [[COPY12]](s64) ; CHECK: $sgpr10_sgpr11 = COPY [[COPY12]](s64)
; CHECK: $sgpr12 = COPY [[COPY13]](s32) ; CHECK: $sgpr12 = COPY [[COPY13]](s32)
; CHECK: $sgpr13 = COPY [[COPY14]](s32) ; CHECK: $sgpr13 = COPY [[COPY14]](s32)
Show All 22 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll

Show First 20 Lines • Show All 753 Lines • ▼ Show 20 Linesdefine void @void_func_v33i32(<33 x i32> %arg0) #0 {
; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr25 ; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr25
; CHECK: [[COPY26:%[0-9]+]]:_(s32) = COPY $vgpr26 ; CHECK: [[COPY26:%[0-9]+]]:_(s32) = COPY $vgpr26
; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY $vgpr27 ; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY $vgpr27
; CHECK: [[COPY28:%[0-9]+]]:_(s32) = COPY $vgpr28 ; CHECK: [[COPY28:%[0-9]+]]:_(s32) = COPY $vgpr28
; CHECK: [[COPY29:%[0-9]+]]:_(s32) = COPY $vgpr29 ; CHECK: [[COPY29:%[0-9]+]]:_(s32) = COPY $vgpr29
; CHECK: [[COPY30:%[0-9]+]]:_(s32) = COPY $vgpr30 ; CHECK: [[COPY30:%[0-9]+]]:_(s32) = COPY $vgpr30
; CHECK: [[COPY31:%[0-9]+]]:_(s32) = COPY $vgpr31 ; CHECK: [[COPY31:%[0-9]+]]:_(s32) = COPY $vgpr31
; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.0 ; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.0
; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p5) :: (invariant load 4 from %fixed-stack.0, align 16, addrspace 5) ; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p5) :: (invariant load 4 from %fixed-stack.0, addrspace 5)
; CHECK: [[COPY32:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 ; CHECK: [[COPY32:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<33 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32), [[LOAD]](s32) ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<33 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32), [[LOAD]](s32)
; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: G_STORE [[BUILD_VECTOR]](<33 x s32>), [[DEF]](p1) :: (store 132 into `<33 x i32> addrspace(1)* undef`, align 256, addrspace 1) ; CHECK: G_STORE [[BUILD_VECTOR]](<33 x s32>), [[DEF]](p1) :: (store 132 into `<33 x i32> addrspace(1)* undef`, align 256, addrspace 1)
; CHECK: [[COPY33:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY32]] ; CHECK: [[COPY33:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY32]]
; CHECK: S_SETPC_B64_return [[COPY33]] ; CHECK: S_SETPC_B64_return [[COPY33]]
store <33 x i32> %arg0, <33 x i32> addrspace(1)* undef store <33 x i32> %arg0, <33 x i32> addrspace(1)* undef
ret void ret void
▲ Show 20 Lines • Show All 378 Lines • ▼ Show 20 Linesdefine void @void_func_v65i16(<65 x i16> %arg0) #0 {
; CHECK: [[COPY25:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr25 ; CHECK: [[COPY25:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr25
; CHECK: [[COPY26:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr26 ; CHECK: [[COPY26:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr26
; CHECK: [[COPY27:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr27 ; CHECK: [[COPY27:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr27
; CHECK: [[COPY28:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr28 ; CHECK: [[COPY28:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr28
; CHECK: [[COPY29:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr29 ; CHECK: [[COPY29:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr29
; CHECK: [[COPY30:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr30 ; CHECK: [[COPY30:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr30
; CHECK: [[COPY31:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr31 ; CHECK: [[COPY31:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr31
; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.0 ; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.0
; CHECK: [[LOAD:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[FRAME_INDEX]](p5) :: (invariant load 4 from %fixed-stack.0, align 16, addrspace 5) ; CHECK: [[LOAD:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[FRAME_INDEX]](p5) :: (invariant load 4 from %fixed-stack.0, addrspace 5)
; CHECK: [[COPY32:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 ; CHECK: [[COPY32:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; CHECK: [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<130 x s16>) = G_CONCAT_VECTORS [[COPY]](<2 x s16>), [[COPY1]](<2 x s16>), [[COPY2]](<2 x s16>), [[COPY3]](<2 x s16>), [[COPY4]](<2 x s16>), [[COPY5]](<2 x s16>), [[COPY6]](<2 x s16>), [[COPY7]](<2 x s16>), [[COPY8]](<2 x s16>), [[COPY9]](<2 x s16>), [[COPY10]](<2 x s16>), [[COPY11]](<2 x s16>), [[COPY12]](<2 x s16>), [[COPY13]](<2 x s16>), [[COPY14]](<2 x s16>), [[COPY15]](<2 x s16>), [[COPY16]](<2 x s16>), [[COPY17]](<2 x s16>), [[COPY18]](<2 x s16>), [[COPY19]](<2 x s16>), [[COPY20]](<2 x s16>), [[COPY21]](<2 x s16>), [[COPY22]](<2 x s16>), [[COPY23]](<2 x s16>), [[COPY24]](<2 x s16>), [[COPY25]](<2 x s16>), [[COPY26]](<2 x s16>), [[COPY27]](<2 x s16>), [[COPY28]](<2 x s16>), [[COPY29]](<2 x s16>), [[COPY30]](<2 x s16>), [[COPY31]](<2 x s16>), [[LOAD]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>) ; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<130 x s16>) = G_CONCAT_VECTORS [[COPY]](<2 x s16>), [[COPY1]](<2 x s16>), [[COPY2]](<2 x s16>), [[COPY3]](<2 x s16>), [[COPY4]](<2 x s16>), [[COPY5]](<2 x s16>), [[COPY6]](<2 x s16>), [[COPY7]](<2 x s16>), [[COPY8]](<2 x s16>), [[COPY9]](<2 x s16>), [[COPY10]](<2 x s16>), [[COPY11]](<2 x s16>), [[COPY12]](<2 x s16>), [[COPY13]](<2 x s16>), [[COPY14]](<2 x s16>), [[COPY15]](<2 x s16>), [[COPY16]](<2 x s16>), [[COPY17]](<2 x s16>), [[COPY18]](<2 x s16>), [[COPY19]](<2 x s16>), [[COPY20]](<2 x s16>), [[COPY21]](<2 x s16>), [[COPY22]](<2 x s16>), [[COPY23]](<2 x s16>), [[COPY24]](<2 x s16>), [[COPY25]](<2 x s16>), [[COPY26]](<2 x s16>), [[COPY27]](<2 x s16>), [[COPY28]](<2 x s16>), [[COPY29]](<2 x s16>), [[COPY30]](<2 x s16>), [[COPY31]](<2 x s16>), [[LOAD]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>)
; CHECK: [[UV:%[0-9]+]]:_(<65 x s16>), [[UV1:%[0-9]+]]:_(<65 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<130 x s16>) ; CHECK: [[UV:%[0-9]+]]:_(<65 x s16>), [[UV1:%[0-9]+]]:_(<65 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<130 x s16>)
; CHECK: [[DEF1:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF ; CHECK: [[DEF1:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: G_STORE [[UV]](<65 x s16>), [[DEF1]](p1) :: (store 130 into `<65 x i16> addrspace(1)* undef`, align 256, addrspace 1) ; CHECK: G_STORE [[UV]](<65 x s16>), [[DEF1]](p1) :: (store 130 into `<65 x i16> addrspace(1)* undef`, align 256, addrspace 1)
; CHECK: [[COPY33:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY32]] ; CHECK: [[COPY33:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY32]]
; CHECK: S_SETPC_B64_return [[COPY33]] ; CHECK: S_SETPC_B64_return [[COPY33]]
▲ Show 20 Lines • Show All 419 Lines • ▼ Show 20 Linesdefine void @void_func_struct_i8_i32({ i8, i32 } %arg0) #0 {
ret void ret void
} }
define void @void_func_byval_struct_i8_i32({ i8, i32 } addrspace(5)* byval %arg0) #0 { define void @void_func_byval_struct_i8_i32({ i8, i32 } addrspace(5)* byval %arg0) #0 {
; CHECK-LABEL: name: void_func_byval_struct_i8_i32 ; CHECK-LABEL: name: void_func_byval_struct_i8_i32
; CHECK: bb.1 (%ir-block.0): ; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $sgpr30_sgpr31 ; CHECK: liveins: $sgpr30_sgpr31
; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.0 ; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.0
; CHECK: [[LOAD:%[0-9]+]]:_(p5) = G_LOAD [[FRAME_INDEX]](p5) :: (invariant load 4 from %fixed-stack.0, align 16, addrspace 5) ; CHECK: [[LOAD:%[0-9]+]]:_(p5) = G_LOAD [[FRAME_INDEX]](p5) :: (invariant load 4 from %fixed-stack.0, addrspace 5)
; CHECK: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 ; CHECK: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[LOAD]](p5) :: (dereferenceable load 1 from %ir.arg0, align 4, addrspace 5) ; CHECK: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[LOAD]](p5) :: (dereferenceable load 1 from %ir.arg0, align 4, addrspace 5)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[LOAD]], [[C]](s32) ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[LOAD]], [[C]](s32)
; CHECK: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (dereferenceable load 4 from %ir.arg0 + 4, addrspace 5) ; CHECK: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (dereferenceable load 4 from %ir.arg0 + 4, addrspace 5)
; CHECK: G_STORE [[LOAD1]](s8), [[DEF]](p1) :: (store 1 into `{ i8, i32 } addrspace(1)* undef`, align 4, addrspace 1) ; CHECK: G_STORE [[LOAD1]](s8), [[DEF]](p1) :: (store 1 into `{ i8, i32 } addrspace(1)* undef`, align 4, addrspace 1)
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[DEF]], [[C1]](s64) ; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[DEF]], [[C1]](s64)
; CHECK: G_STORE [[LOAD2]](s32), [[PTR_ADD1]](p1) :: (store 4 into `{ i8, i32 } addrspace(1)* undef` + 4, addrspace 1) ; CHECK: G_STORE [[LOAD2]](s32), [[PTR_ADD1]](p1) :: (store 4 into `{ i8, i32 } addrspace(1)* undef` + 4, addrspace 1)
; CHECK: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]] ; CHECK: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
; CHECK: S_SETPC_B64_return [[COPY1]] ; CHECK: S_SETPC_B64_return [[COPY1]]
%arg0.load = load { i8, i32 }, { i8, i32 } addrspace(5)* %arg0 %arg0.load = load { i8, i32 }, { i8, i32 } addrspace(5)* %arg0
store { i8, i32 } %arg0.load, { i8, i32 } addrspace(1)* undef store { i8, i32 } %arg0.load, { i8, i32 } addrspace(1)* undef
ret void ret void
} }
define void @void_func_byval_struct_i8_i32_x2({ i8, i32 } addrspace(5)* byval %arg0, { i8, i32 } addrspace(5)* byval %arg1, i32 %arg2) #0 { define void @void_func_byval_struct_i8_i32_x2({ i8, i32 } addrspace(5)* byval %arg0, { i8, i32 } addrspace(5)* byval %arg1, i32 %arg2) #0 {
; CHECK-LABEL: name: void_func_byval_struct_i8_i32_x2 ; CHECK-LABEL: name: void_func_byval_struct_i8_i32_x2
; CHECK: bb.1 (%ir-block.0): ; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $vgpr0, $sgpr30_sgpr31 ; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.1 ; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.1
; CHECK: [[LOAD:%[0-9]+]]:_(p5) = G_LOAD [[FRAME_INDEX]](p5) :: (invariant load 4 from %fixed-stack.1, align 16, addrspace 5) ; CHECK: [[LOAD:%[0-9]+]]:_(p5) = G_LOAD [[FRAME_INDEX]](p5) :: (invariant load 4 from %fixed-stack.1, addrspace 5)
; CHECK: [[FRAME_INDEX1:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.0 ; CHECK: [[FRAME_INDEX1:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.0
; CHECK: [[LOAD1:%[0-9]+]]:_(p5) = G_LOAD [[FRAME_INDEX1]](p5) :: (invariant load 4 from %fixed-stack.0, align 8, addrspace 5) ; CHECK: [[LOAD1:%[0-9]+]]:_(p5) = G_LOAD [[FRAME_INDEX1]](p5) :: (invariant load 4 from %fixed-stack.0, addrspace 5)
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 ; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: [[DEF1:%[0-9]+]]:_(p3) = G_IMPLICIT_DEF ; CHECK: [[DEF1:%[0-9]+]]:_(p3) = G_IMPLICIT_DEF
; CHECK: [[LOAD2:%[0-9]+]]:_(s8) = G_LOAD [[LOAD]](p5) :: (volatile dereferenceable load 1 from %ir.arg0, align 4, addrspace 5) ; CHECK: [[LOAD2:%[0-9]+]]:_(s8) = G_LOAD [[LOAD]](p5) :: (volatile dereferenceable load 1 from %ir.arg0, align 4, addrspace 5)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[LOAD]], [[C]](s32) ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[LOAD]], [[C]](s32)
; CHECK: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (volatile dereferenceable load 4 from %ir.arg0 + 4, addrspace 5) ; CHECK: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (volatile dereferenceable load 4 from %ir.arg0 + 4, addrspace 5)
Show All 18 Linesdefine void @void_func_byval_struct_i8_i32_x2({ i8, i32 } addrspace(5)* byval %arg0, { i8, i32 } addrspace(5)* byval %arg1, i32 %arg2) #0 {
ret void ret void
} }
define void @void_func_byval_i32_byval_i64(i32 addrspace(5)* byval %arg0, i64 addrspace(5)* byval %arg1) #0 { define void @void_func_byval_i32_byval_i64(i32 addrspace(5)* byval %arg0, i64 addrspace(5)* byval %arg1) #0 {
; CHECK-LABEL: name: void_func_byval_i32_byval_i64 ; CHECK-LABEL: name: void_func_byval_i32_byval_i64
; CHECK: bb.1 (%ir-block.0): ; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $sgpr30_sgpr31 ; CHECK: liveins: $sgpr30_sgpr31
; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.1 ; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.1
; CHECK: [[LOAD:%[0-9]+]]:_(p5) = G_LOAD [[FRAME_INDEX]](p5) :: (invariant load 4 from %fixed-stack.1, align 16, addrspace 5) ; CHECK: [[LOAD:%[0-9]+]]:_(p5) = G_LOAD [[FRAME_INDEX]](p5) :: (invariant load 4 from %fixed-stack.1, addrspace 5)
; CHECK: [[FRAME_INDEX1:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.0 ; CHECK: [[FRAME_INDEX1:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.0
; CHECK: [[LOAD1:%[0-9]+]]:_(p5) = G_LOAD [[FRAME_INDEX1]](p5) :: (invariant load 4 from %fixed-stack.0, align 8, addrspace 5) ; CHECK: [[LOAD1:%[0-9]+]]:_(p5) = G_LOAD [[FRAME_INDEX1]](p5) :: (invariant load 4 from %fixed-stack.0, addrspace 5)
; CHECK: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 ; CHECK: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: [[COPY1:%[0-9]+]]:_(p1) = COPY [[DEF]](p1) ; CHECK: [[COPY1:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)
; CHECK: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[LOAD]](p5) :: (dereferenceable load 4 from %ir.arg0, addrspace 5) ; CHECK: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[LOAD]](p5) :: (dereferenceable load 4 from %ir.arg0, addrspace 5)
; CHECK: [[LOAD3:%[0-9]+]]:_(s64) = G_LOAD [[LOAD1]](p5) :: (dereferenceable load 8 from %ir.arg1, addrspace 5) ; CHECK: [[LOAD3:%[0-9]+]]:_(s64) = G_LOAD [[LOAD1]](p5) :: (dereferenceable load 8 from %ir.arg1, addrspace 5)
; CHECK: G_STORE [[LOAD2]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1) ; CHECK: G_STORE [[LOAD2]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
; CHECK: G_STORE [[LOAD3]](s64), [[COPY1]](p1) :: (store 8 into `i64 addrspace(1)* undef`, addrspace 1) ; CHECK: G_STORE [[LOAD3]](s64), [[COPY1]](p1) :: (store 8 into `i64 addrspace(1)* undef`, addrspace 1)
; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]] ; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
Show All 37 Linesdefine void @void_func_v32i32_i32_i64(<32 x i32> %arg0, i32 %arg1, i64 %arg2) #0 {
; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr25 ; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr25
; CHECK: [[COPY26:%[0-9]+]]:_(s32) = COPY $vgpr26 ; CHECK: [[COPY26:%[0-9]+]]:_(s32) = COPY $vgpr26
; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY $vgpr27 ; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY $vgpr27
; CHECK: [[COPY28:%[0-9]+]]:_(s32) = COPY $vgpr28 ; CHECK: [[COPY28:%[0-9]+]]:_(s32) = COPY $vgpr28
; CHECK: [[COPY29:%[0-9]+]]:_(s32) = COPY $vgpr29 ; CHECK: [[COPY29:%[0-9]+]]:_(s32) = COPY $vgpr29
; CHECK: [[COPY30:%[0-9]+]]:_(s32) = COPY $vgpr30 ; CHECK: [[COPY30:%[0-9]+]]:_(s32) = COPY $vgpr30
; CHECK: [[COPY31:%[0-9]+]]:_(s32) = COPY $vgpr31 ; CHECK: [[COPY31:%[0-9]+]]:_(s32) = COPY $vgpr31
; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.2 ; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.2
; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p5) :: (invariant load 4 from %fixed-stack.2, align 16, addrspace 5) ; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p5) :: (invariant load 4 from %fixed-stack.2, addrspace 5)
; CHECK: [[FRAME_INDEX1:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.1 ; CHECK: [[FRAME_INDEX1:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.1
; CHECK: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p5) :: (invariant load 4 from %fixed-stack.1, addrspace 5) ; CHECK: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p5) :: (invariant load 4 from %fixed-stack.1, addrspace 5)
; CHECK: [[FRAME_INDEX2:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.0 ; CHECK: [[FRAME_INDEX2:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.0
; CHECK: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX2]](p5) :: (invariant load 4 from %fixed-stack.0, align 8, addrspace 5) ; CHECK: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX2]](p5) :: (invariant load 4 from %fixed-stack.0, addrspace 5)
; CHECK: [[COPY32:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 ; CHECK: [[COPY32:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32) ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32)
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD1]](s32), [[LOAD2]](s32) ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD1]](s32), [[LOAD2]](s32)
; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: [[COPY33:%[0-9]+]]:_(p1) = COPY [[DEF]](p1) ; CHECK: [[COPY33:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)
; CHECK: [[COPY34:%[0-9]+]]:_(p1) = COPY [[DEF]](p1) ; CHECK: [[COPY34:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)
; CHECK: G_STORE [[BUILD_VECTOR]](<32 x s32>), [[DEF]](p1) :: (volatile store 128 into `<32 x i32> addrspace(1)* undef`, addrspace 1) ; CHECK: G_STORE [[BUILD_VECTOR]](<32 x s32>), [[DEF]](p1) :: (volatile store 128 into `<32 x i32> addrspace(1)* undef`, addrspace 1)
; CHECK: G_STORE [[LOAD]](s32), [[COPY33]](p1) :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1) ; CHECK: G_STORE [[LOAD]](s32), [[COPY33]](p1) :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)
Show All 39 Linesdefine void @void_func_v32i32_i1_i8_i16(<32 x i32> %arg0, i1 %arg1, i8 %arg2, i16 %arg3, half %arg4) #0 {
; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr25 ; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr25
; CHECK: [[COPY26:%[0-9]+]]:_(s32) = COPY $vgpr26 ; CHECK: [[COPY26:%[0-9]+]]:_(s32) = COPY $vgpr26
; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY $vgpr27 ; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY $vgpr27
; CHECK: [[COPY28:%[0-9]+]]:_(s32) = COPY $vgpr28 ; CHECK: [[COPY28:%[0-9]+]]:_(s32) = COPY $vgpr28
; CHECK: [[COPY29:%[0-9]+]]:_(s32) = COPY $vgpr29 ; CHECK: [[COPY29:%[0-9]+]]:_(s32) = COPY $vgpr29
; CHECK: [[COPY30:%[0-9]+]]:_(s32) = COPY $vgpr30 ; CHECK: [[COPY30:%[0-9]+]]:_(s32) = COPY $vgpr30
; CHECK: [[COPY31:%[0-9]+]]:_(s32) = COPY $vgpr31 ; CHECK: [[COPY31:%[0-9]+]]:_(s32) = COPY $vgpr31
; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.3 ; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.3
; CHECK: [[LOAD:%[0-9]+]]:_(s1) = G_LOAD [[FRAME_INDEX]](p5) :: (invariant load 1 from %fixed-stack.3, align 16, addrspace 5) ; CHECK: [[LOAD:%[0-9]+]]:_(s1) = G_LOAD [[FRAME_INDEX]](p5) :: (invariant load 1 from %fixed-stack.3, align 4, addrspace 5)
; CHECK: [[FRAME_INDEX1:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.2 ; CHECK: [[FRAME_INDEX1:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.2
; CHECK: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[FRAME_INDEX1]](p5) :: (invariant load 1 from %fixed-stack.2, align 4, addrspace 5) ; CHECK: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[FRAME_INDEX1]](p5) :: (invariant load 1 from %fixed-stack.2, align 4, addrspace 5)
; CHECK: [[FRAME_INDEX2:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.1 ; CHECK: [[FRAME_INDEX2:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.1
; CHECK: [[LOAD2:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX2]](p5) :: (invariant load 2 from %fixed-stack.1, align 8, addrspace 5) ; CHECK: [[LOAD2:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX2]](p5) :: (invariant load 2 from %fixed-stack.1, align 4, addrspace 5)
; CHECK: [[FRAME_INDEX3:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.0 ; CHECK: [[FRAME_INDEX3:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.0
; CHECK: [[LOAD3:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX3]](p5) :: (invariant load 2 from %fixed-stack.0, align 4, addrspace 5) ; CHECK: [[LOAD3:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX3]](p5) :: (invariant load 2 from %fixed-stack.0, align 4, addrspace 5)
; CHECK: [[COPY32:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 ; CHECK: [[COPY32:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32) ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32)
; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: [[COPY33:%[0-9]+]]:_(p1) = COPY [[DEF]](p1) ; CHECK: [[COPY33:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)
; CHECK: [[COPY34:%[0-9]+]]:_(p1) = COPY [[DEF]](p1) ; CHECK: [[COPY34:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)
; CHECK: [[COPY35:%[0-9]+]]:_(p1) = COPY [[DEF]](p1) ; CHECK: [[COPY35:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Linesdefine void @void_func_v32i32_p3_p5_i16(<32 x i32> %arg0, i8 addrspace(3)* %arg1, i8 addrspace(5)* %arg2) #0 {
; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr25 ; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr25
; CHECK: [[COPY26:%[0-9]+]]:_(s32) = COPY $vgpr26 ; CHECK: [[COPY26:%[0-9]+]]:_(s32) = COPY $vgpr26
; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY $vgpr27 ; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY $vgpr27
; CHECK: [[COPY28:%[0-9]+]]:_(s32) = COPY $vgpr28 ; CHECK: [[COPY28:%[0-9]+]]:_(s32) = COPY $vgpr28
; CHECK: [[COPY29:%[0-9]+]]:_(s32) = COPY $vgpr29 ; CHECK: [[COPY29:%[0-9]+]]:_(s32) = COPY $vgpr29
; CHECK: [[COPY30:%[0-9]+]]:_(s32) = COPY $vgpr30 ; CHECK: [[COPY30:%[0-9]+]]:_(s32) = COPY $vgpr30
; CHECK: [[COPY31:%[0-9]+]]:_(s32) = COPY $vgpr31 ; CHECK: [[COPY31:%[0-9]+]]:_(s32) = COPY $vgpr31
; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.1 ; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.1
; CHECK: [[LOAD:%[0-9]+]]:_(p3) = G_LOAD [[FRAME_INDEX]](p5) :: (invariant load 4 from %fixed-stack.1, align 16, addrspace 5) ; CHECK: [[LOAD:%[0-9]+]]:_(p3) = G_LOAD [[FRAME_INDEX]](p5) :: (invariant load 4 from %fixed-stack.1, addrspace 5)
; CHECK: [[FRAME_INDEX1:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.0 ; CHECK: [[FRAME_INDEX1:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.0
; CHECK: [[LOAD1:%[0-9]+]]:_(p5) = G_LOAD [[FRAME_INDEX1]](p5) :: (invariant load 4 from %fixed-stack.0, addrspace 5) ; CHECK: [[LOAD1:%[0-9]+]]:_(p5) = G_LOAD [[FRAME_INDEX1]](p5) :: (invariant load 4 from %fixed-stack.0, addrspace 5)
; CHECK: [[COPY32:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 ; CHECK: [[COPY32:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32) ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32)
; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: [[COPY33:%[0-9]+]]:_(p1) = COPY [[DEF]](p1) ; CHECK: [[COPY33:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)
; CHECK: [[COPY34:%[0-9]+]]:_(p1) = COPY [[DEF]](p1) ; CHECK: [[COPY34:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)
; CHECK: G_STORE [[BUILD_VECTOR]](<32 x s32>), [[DEF]](p1) :: (volatile store 128 into `<32 x i32> addrspace(1)* undef`, addrspace 1) ; CHECK: G_STORE [[BUILD_VECTOR]](<32 x s32>), [[DEF]](p1) :: (volatile store 128 into `<32 x i32> addrspace(1)* undef`, addrspace 1)
Show All 39 Linesdefine void @void_func_v32i32_v2i32_v2f32(<32 x i32> %arg0, <2 x i32> %arg1, <2 x float> %arg2) #0 {
; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr25 ; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr25
; CHECK: [[COPY26:%[0-9]+]]:_(s32) = COPY $vgpr26 ; CHECK: [[COPY26:%[0-9]+]]:_(s32) = COPY $vgpr26
; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY $vgpr27 ; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY $vgpr27
; CHECK: [[COPY28:%[0-9]+]]:_(s32) = COPY $vgpr28 ; CHECK: [[COPY28:%[0-9]+]]:_(s32) = COPY $vgpr28
; CHECK: [[COPY29:%[0-9]+]]:_(s32) = COPY $vgpr29 ; CHECK: [[COPY29:%[0-9]+]]:_(s32) = COPY $vgpr29
; CHECK: [[COPY30:%[0-9]+]]:_(s32) = COPY $vgpr30 ; CHECK: [[COPY30:%[0-9]+]]:_(s32) = COPY $vgpr30
; CHECK: [[COPY31:%[0-9]+]]:_(s32) = COPY $vgpr31 ; CHECK: [[COPY31:%[0-9]+]]:_(s32) = COPY $vgpr31
; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.3 ; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.3
; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p5) :: (invariant load 4 from %fixed-stack.3, align 16, addrspace 5) ; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p5) :: (invariant load 4 from %fixed-stack.3, addrspace 5)
; CHECK: [[FRAME_INDEX1:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.2 ; CHECK: [[FRAME_INDEX1:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.2
; CHECK: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p5) :: (invariant load 4 from %fixed-stack.2, addrspace 5) ; CHECK: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p5) :: (invariant load 4 from %fixed-stack.2, addrspace 5)
; CHECK: [[FRAME_INDEX2:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.1 ; CHECK: [[FRAME_INDEX2:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.1
; CHECK: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX2]](p5) :: (invariant load 4 from %fixed-stack.1, align 8, addrspace 5) ; CHECK: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX2]](p5) :: (invariant load 4 from %fixed-stack.1, addrspace 5)
; CHECK: [[FRAME_INDEX3:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.0 ; CHECK: [[FRAME_INDEX3:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.0
; CHECK: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX3]](p5) :: (invariant load 4 from %fixed-stack.0, addrspace 5) ; CHECK: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX3]](p5) :: (invariant load 4 from %fixed-stack.0, addrspace 5)
; CHECK: [[COPY32:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 ; CHECK: [[COPY32:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32) ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32)
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32) ; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32)
; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[LOAD2]](s32), [[LOAD3]](s32) ; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[LOAD2]](s32), [[LOAD3]](s32)
; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: [[COPY33:%[0-9]+]]:_(p1) = COPY [[DEF]](p1) ; CHECK: [[COPY33:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Linesdefine void @void_func_v32i32_v2i16_v2f16(<32 x i32> %arg0, <2 x i16> %arg1, <2 x half> %arg2) #0 {
; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr25 ; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr25
; CHECK: [[COPY26:%[0-9]+]]:_(s32) = COPY $vgpr26 ; CHECK: [[COPY26:%[0-9]+]]:_(s32) = COPY $vgpr26
; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY $vgpr27 ; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY $vgpr27
; CHECK: [[COPY28:%[0-9]+]]:_(s32) = COPY $vgpr28 ; CHECK: [[COPY28:%[0-9]+]]:_(s32) = COPY $vgpr28
; CHECK: [[COPY29:%[0-9]+]]:_(s32) = COPY $vgpr29 ; CHECK: [[COPY29:%[0-9]+]]:_(s32) = COPY $vgpr29
; CHECK: [[COPY30:%[0-9]+]]:_(s32) = COPY $vgpr30 ; CHECK: [[COPY30:%[0-9]+]]:_(s32) = COPY $vgpr30
; CHECK: [[COPY31:%[0-9]+]]:_(s32) = COPY $vgpr31 ; CHECK: [[COPY31:%[0-9]+]]:_(s32) = COPY $vgpr31
; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.1 ; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.1
; CHECK: [[LOAD:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[FRAME_INDEX]](p5) :: (invariant load 4 from %fixed-stack.1, align 16, addrspace 5) ; CHECK: [[LOAD:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[FRAME_INDEX]](p5) :: (invariant load 4 from %fixed-stack.1, addrspace 5)
; CHECK: [[FRAME_INDEX1:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.0 ; CHECK: [[FRAME_INDEX1:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.0
; CHECK: [[LOAD1:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[FRAME_INDEX1]](p5) :: (invariant load 4 from %fixed-stack.0, addrspace 5) ; CHECK: [[LOAD1:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[FRAME_INDEX1]](p5) :: (invariant load 4 from %fixed-stack.0, addrspace 5)
; CHECK: [[COPY32:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 ; CHECK: [[COPY32:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32) ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32)
; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: [[COPY33:%[0-9]+]]:_(p1) = COPY [[DEF]](p1) ; CHECK: [[COPY33:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)
; CHECK: [[COPY34:%[0-9]+]]:_(p1) = COPY [[DEF]](p1) ; CHECK: [[COPY34:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)
; CHECK: G_STORE [[BUILD_VECTOR]](<32 x s32>), [[DEF]](p1) :: (volatile store 128 into `<32 x i32> addrspace(1)* undef`, addrspace 1) ; CHECK: G_STORE [[BUILD_VECTOR]](<32 x s32>), [[DEF]](p1) :: (volatile store 128 into `<32 x i32> addrspace(1)* undef`, addrspace 1)
Show All 39 Linesdefine void @void_func_v32i32_v2i64_v2f64(<32 x i32> %arg0, <2 x i64> %arg1, <2 x double> %arg2) #0 {
; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr25 ; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr25
; CHECK: [[COPY26:%[0-9]+]]:_(s32) = COPY $vgpr26 ; CHECK: [[COPY26:%[0-9]+]]:_(s32) = COPY $vgpr26
; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY $vgpr27 ; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY $vgpr27
; CHECK: [[COPY28:%[0-9]+]]:_(s32) = COPY $vgpr28 ; CHECK: [[COPY28:%[0-9]+]]:_(s32) = COPY $vgpr28
; CHECK: [[COPY29:%[0-9]+]]:_(s32) = COPY $vgpr29 ; CHECK: [[COPY29:%[0-9]+]]:_(s32) = COPY $vgpr29
; CHECK: [[COPY30:%[0-9]+]]:_(s32) = COPY $vgpr30 ; CHECK: [[COPY30:%[0-9]+]]:_(s32) = COPY $vgpr30
; CHECK: [[COPY31:%[0-9]+]]:_(s32) = COPY $vgpr31 ; CHECK: [[COPY31:%[0-9]+]]:_(s32) = COPY $vgpr31
; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.7 ; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.7
; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p5) :: (invariant load 4 from %fixed-stack.7, align 16, addrspace 5) ; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p5) :: (invariant load 4 from %fixed-stack.7, addrspace 5)
; CHECK: [[FRAME_INDEX1:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.6 ; CHECK: [[FRAME_INDEX1:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.6
; CHECK: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p5) :: (invariant load 4 from %fixed-stack.6, addrspace 5) ; CHECK: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p5) :: (invariant load 4 from %fixed-stack.6, addrspace 5)
; CHECK: [[FRAME_INDEX2:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.5 ; CHECK: [[FRAME_INDEX2:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.5
; CHECK: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX2]](p5) :: (invariant load 4 from %fixed-stack.5, align 8, addrspace 5) ; CHECK: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX2]](p5) :: (invariant load 4 from %fixed-stack.5, addrspace 5)
; CHECK: [[FRAME_INDEX3:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.4 ; CHECK: [[FRAME_INDEX3:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.4
; CHECK: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX3]](p5) :: (invariant load 4 from %fixed-stack.4, addrspace 5) ; CHECK: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX3]](p5) :: (invariant load 4 from %fixed-stack.4, addrspace 5)
; CHECK: [[FRAME_INDEX4:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.3 ; CHECK: [[FRAME_INDEX4:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.3
; CHECK: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX4]](p5) :: (invariant load 4 from %fixed-stack.3, align 16, addrspace 5) ; CHECK: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX4]](p5) :: (invariant load 4 from %fixed-stack.3, addrspace 5)
; CHECK: [[FRAME_INDEX5:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.2 ; CHECK: [[FRAME_INDEX5:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.2
; CHECK: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX5]](p5) :: (invariant load 4 from %fixed-stack.2, addrspace 5) ; CHECK: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX5]](p5) :: (invariant load 4 from %fixed-stack.2, addrspace 5)
; CHECK: [[FRAME_INDEX6:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.1 ; CHECK: [[FRAME_INDEX6:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.1
; CHECK: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX6]](p5) :: (invariant load 4 from %fixed-stack.1, align 8, addrspace 5) ; CHECK: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX6]](p5) :: (invariant load 4 from %fixed-stack.1, addrspace 5)
; CHECK: [[FRAME_INDEX7:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.0 ; CHECK: [[FRAME_INDEX7:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.0
; CHECK: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX7]](p5) :: (invariant load 4 from %fixed-stack.0, addrspace 5) ; CHECK: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX7]](p5) :: (invariant load 4 from %fixed-stack.0, addrspace 5)
; CHECK: [[COPY32:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 ; CHECK: [[COPY32:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32) ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32)
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD]](s32), [[LOAD1]](s32) ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD]](s32), [[LOAD1]](s32)
; CHECK: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD2]](s32), [[LOAD3]](s32) ; CHECK: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD2]](s32), [[LOAD3]](s32)
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64) ; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64)
; CHECK: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD4]](s32), [[LOAD5]](s32) ; CHECK: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD4]](s32), [[LOAD5]](s32)
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Linesdefine void @void_func_v32i32_v4i32_v4f32(<32 x i32> %arg0, <4 x i32> %arg1, <4 x float> %arg2) #0 {
; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr25 ; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr25
; CHECK: [[COPY26:%[0-9]+]]:_(s32) = COPY $vgpr26 ; CHECK: [[COPY26:%[0-9]+]]:_(s32) = COPY $vgpr26
; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY $vgpr27 ; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY $vgpr27
; CHECK: [[COPY28:%[0-9]+]]:_(s32) = COPY $vgpr28 ; CHECK: [[COPY28:%[0-9]+]]:_(s32) = COPY $vgpr28
; CHECK: [[COPY29:%[0-9]+]]:_(s32) = COPY $vgpr29 ; CHECK: [[COPY29:%[0-9]+]]:_(s32) = COPY $vgpr29
; CHECK: [[COPY30:%[0-9]+]]:_(s32) = COPY $vgpr30 ; CHECK: [[COPY30:%[0-9]+]]:_(s32) = COPY $vgpr30
; CHECK: [[COPY31:%[0-9]+]]:_(s32) = COPY $vgpr31 ; CHECK: [[COPY31:%[0-9]+]]:_(s32) = COPY $vgpr31
; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.7 ; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.7
; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p5) :: (invariant load 4 from %fixed-stack.7, align 16, addrspace 5) ; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p5) :: (invariant load 4 from %fixed-stack.7, addrspace 5)
; CHECK: [[FRAME_INDEX1:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.6 ; CHECK: [[FRAME_INDEX1:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.6
; CHECK: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p5) :: (invariant load 4 from %fixed-stack.6, addrspace 5) ; CHECK: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p5) :: (invariant load 4 from %fixed-stack.6, addrspace 5)
; CHECK: [[FRAME_INDEX2:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.5 ; CHECK: [[FRAME_INDEX2:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.5
; CHECK: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX2]](p5) :: (invariant load 4 from %fixed-stack.5, align 8, addrspace 5) ; CHECK: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX2]](p5) :: (invariant load 4 from %fixed-stack.5, addrspace 5)
; CHECK: [[FRAME_INDEX3:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.4 ; CHECK: [[FRAME_INDEX3:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.4
; CHECK: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX3]](p5) :: (invariant load 4 from %fixed-stack.4, addrspace 5) ; CHECK: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX3]](p5) :: (invariant load 4 from %fixed-stack.4, addrspace 5)
; CHECK: [[FRAME_INDEX4:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.3 ; CHECK: [[FRAME_INDEX4:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.3
; CHECK: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX4]](p5) :: (invariant load 4 from %fixed-stack.3, align 16, addrspace 5) ; CHECK: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX4]](p5) :: (invariant load 4 from %fixed-stack.3, addrspace 5)
; CHECK: [[FRAME_INDEX5:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.2 ; CHECK: [[FRAME_INDEX5:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.2
; CHECK: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX5]](p5) :: (invariant load 4 from %fixed-stack.2, addrspace 5) ; CHECK: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX5]](p5) :: (invariant load 4 from %fixed-stack.2, addrspace 5)
; CHECK: [[FRAME_INDEX6:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.1 ; CHECK: [[FRAME_INDEX6:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.1
; CHECK: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX6]](p5) :: (invariant load 4 from %fixed-stack.1, align 8, addrspace 5) ; CHECK: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX6]](p5) :: (invariant load 4 from %fixed-stack.1, addrspace 5)
; CHECK: [[FRAME_INDEX7:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.0 ; CHECK: [[FRAME_INDEX7:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.0
; CHECK: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX7]](p5) :: (invariant load 4 from %fixed-stack.0, addrspace 5) ; CHECK: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX7]](p5) :: (invariant load 4 from %fixed-stack.0, addrspace 5)
; CHECK: [[COPY32:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 ; CHECK: [[COPY32:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32) ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32)
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32) ; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD4]](s32), [[LOAD5]](s32), [[LOAD6]](s32), [[LOAD7]](s32) ; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD4]](s32), [[LOAD5]](s32), [[LOAD6]](s32), [[LOAD7]](s32)
; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: [[COPY33:%[0-9]+]]:_(p1) = COPY [[DEF]](p1) ; CHECK: [[COPY33:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Linesdefine void @void_func_v32i32_v8i32_v8f32(<32 x i32> %arg0, <8 x i32> %arg1, <8 x float> %arg2) #0 {
; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr25 ; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr25
; CHECK: [[COPY26:%[0-9]+]]:_(s32) = COPY $vgpr26 ; CHECK: [[COPY26:%[0-9]+]]:_(s32) = COPY $vgpr26
; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY $vgpr27 ; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY $vgpr27
; CHECK: [[COPY28:%[0-9]+]]:_(s32) = COPY $vgpr28 ; CHECK: [[COPY28:%[0-9]+]]:_(s32) = COPY $vgpr28
; CHECK: [[COPY29:%[0-9]+]]:_(s32) = COPY $vgpr29 ; CHECK: [[COPY29:%[0-9]+]]:_(s32) = COPY $vgpr29
; CHECK: [[COPY30:%[0-9]+]]:_(s32) = COPY $vgpr30 ; CHECK: [[COPY30:%[0-9]+]]:_(s32) = COPY $vgpr30
; CHECK: [[COPY31:%[0-9]+]]:_(s32) = COPY $vgpr31 ; CHECK: [[COPY31:%[0-9]+]]:_(s32) = COPY $vgpr31
; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.15 ; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.15
; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p5) :: (invariant load 4 from %fixed-stack.15, align 16, addrspace 5) ; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p5) :: (invariant load 4 from %fixed-stack.15, addrspace 5)
; CHECK: [[FRAME_INDEX1:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.14 ; CHECK: [[FRAME_INDEX1:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.14
; CHECK: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p5) :: (invariant load 4 from %fixed-stack.14, addrspace 5) ; CHECK: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p5) :: (invariant load 4 from %fixed-stack.14, addrspace 5)
; CHECK: [[FRAME_INDEX2:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.13 ; CHECK: [[FRAME_INDEX2:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.13
; CHECK: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX2]](p5) :: (invariant load 4 from %fixed-stack.13, align 8, addrspace 5) ; CHECK: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX2]](p5) :: (invariant load 4 from %fixed-stack.13, addrspace 5)
; CHECK: [[FRAME_INDEX3:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.12 ; CHECK: [[FRAME_INDEX3:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.12
; CHECK: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX3]](p5) :: (invariant load 4 from %fixed-stack.12, addrspace 5) ; CHECK: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX3]](p5) :: (invariant load 4 from %fixed-stack.12, addrspace 5)
; CHECK: [[FRAME_INDEX4:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.11 ; CHECK: [[FRAME_INDEX4:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.11
; CHECK: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX4]](p5) :: (invariant load 4 from %fixed-stack.11, align 16, addrspace 5) ; CHECK: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX4]](p5) :: (invariant load 4 from %fixed-stack.11, addrspace 5)
; CHECK: [[FRAME_INDEX5:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.10 ; CHECK: [[FRAME_INDEX5:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.10
; CHECK: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX5]](p5) :: (invariant load 4 from %fixed-stack.10, addrspace 5) ; CHECK: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX5]](p5) :: (invariant load 4 from %fixed-stack.10, addrspace 5)
; CHECK: [[FRAME_INDEX6:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.9 ; CHECK: [[FRAME_INDEX6:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.9
; CHECK: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX6]](p5) :: (invariant load 4 from %fixed-stack.9, align 8, addrspace 5) ; CHECK: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX6]](p5) :: (invariant load 4 from %fixed-stack.9, addrspace 5)
; CHECK: [[FRAME_INDEX7:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.8 ; CHECK: [[FRAME_INDEX7:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.8
; CHECK: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX7]](p5) :: (invariant load 4 from %fixed-stack.8, addrspace 5) ; CHECK: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX7]](p5) :: (invariant load 4 from %fixed-stack.8, addrspace 5)
; CHECK: [[FRAME_INDEX8:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.7 ; CHECK: [[FRAME_INDEX8:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.7
; CHECK: [[LOAD8:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX8]](p5) :: (invariant load 4 from %fixed-stack.7, align 16, addrspace 5) ; CHECK: [[LOAD8:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX8]](p5) :: (invariant load 4 from %fixed-stack.7, addrspace 5)
; CHECK: [[FRAME_INDEX9:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.6 ; CHECK: [[FRAME_INDEX9:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.6
; CHECK: [[LOAD9:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX9]](p5) :: (invariant load 4 from %fixed-stack.6, addrspace 5) ; CHECK: [[LOAD9:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX9]](p5) :: (invariant load 4 from %fixed-stack.6, addrspace 5)
; CHECK: [[FRAME_INDEX10:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.5 ; CHECK: [[FRAME_INDEX10:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.5
; CHECK: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX10]](p5) :: (invariant load 4 from %fixed-stack.5, align 8, addrspace 5) ; CHECK: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX10]](p5) :: (invariant load 4 from %fixed-stack.5, addrspace 5)
; CHECK: [[FRAME_INDEX11:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.4 ; CHECK: [[FRAME_INDEX11:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.4
; CHECK: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX11]](p5) :: (invariant load 4 from %fixed-stack.4, addrspace 5) ; CHECK: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX11]](p5) :: (invariant load 4 from %fixed-stack.4, addrspace 5)
; CHECK: [[FRAME_INDEX12:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.3 ; CHECK: [[FRAME_INDEX12:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.3
; CHECK: [[LOAD12:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX12]](p5) :: (invariant load 4 from %fixed-stack.3, align 16, addrspace 5) ; CHECK: [[LOAD12:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX12]](p5) :: (invariant load 4 from %fixed-stack.3, addrspace 5)
; CHECK: [[FRAME_INDEX13:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.2 ; CHECK: [[FRAME_INDEX13:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.2
; CHECK: [[LOAD13:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX13]](p5) :: (invariant load 4 from %fixed-stack.2, addrspace 5) ; CHECK: [[LOAD13:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX13]](p5) :: (invariant load 4 from %fixed-stack.2, addrspace 5)
; CHECK: [[FRAME_INDEX14:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.1 ; CHECK: [[FRAME_INDEX14:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.1
; CHECK: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX14]](p5) :: (invariant load 4 from %fixed-stack.1, align 8, addrspace 5) ; CHECK: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX14]](p5) :: (invariant load 4 from %fixed-stack.1, addrspace 5)
; CHECK: [[FRAME_INDEX15:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.0 ; CHECK: [[FRAME_INDEX15:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.0
; CHECK: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX15]](p5) :: (invariant load 4 from %fixed-stack.0, addrspace 5) ; CHECK: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX15]](p5) :: (invariant load 4 from %fixed-stack.0, addrspace 5)
; CHECK: [[COPY32:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 ; CHECK: [[COPY32:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32) ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32)
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32), [[LOAD4]](s32), [[LOAD5]](s32), [[LOAD6]](s32), [[LOAD7]](s32) ; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32), [[LOAD4]](s32), [[LOAD5]](s32), [[LOAD6]](s32), [[LOAD7]](s32)
; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[LOAD8]](s32), [[LOAD9]](s32), [[LOAD10]](s32), [[LOAD11]](s32), [[LOAD12]](s32), [[LOAD13]](s32), [[LOAD14]](s32), [[LOAD15]](s32) ; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[LOAD8]](s32), [[LOAD9]](s32), [[LOAD10]](s32), [[LOAD11]](s32), [[LOAD12]](s32), [[LOAD13]](s32), [[LOAD14]](s32), [[LOAD15]](s32)
; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: [[COPY33:%[0-9]+]]:_(p1) = COPY [[DEF]](p1) ; CHECK: [[COPY33:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Linesdefine void @void_func_v32i32_v16i32_v16f32(<32 x i32> %arg0, <16 x i32> %arg1, <16 x float> %arg2) #0 {
; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr25 ; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr25
; CHECK: [[COPY26:%[0-9]+]]:_(s32) = COPY $vgpr26 ; CHECK: [[COPY26:%[0-9]+]]:_(s32) = COPY $vgpr26
; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY $vgpr27 ; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY $vgpr27
; CHECK: [[COPY28:%[0-9]+]]:_(s32) = COPY $vgpr28 ; CHECK: [[COPY28:%[0-9]+]]:_(s32) = COPY $vgpr28
; CHECK: [[COPY29:%[0-9]+]]:_(s32) = COPY $vgpr29 ; CHECK: [[COPY29:%[0-9]+]]:_(s32) = COPY $vgpr29
; CHECK: [[COPY30:%[0-9]+]]:_(s32) = COPY $vgpr30 ; CHECK: [[COPY30:%[0-9]+]]:_(s32) = COPY $vgpr30
; CHECK: [[COPY31:%[0-9]+]]:_(s32) = COPY $vgpr31 ; CHECK: [[COPY31:%[0-9]+]]:_(s32) = COPY $vgpr31
; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.31 ; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.31
; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p5) :: (invariant load 4 from %fixed-stack.31, align 16, addrspace 5) ; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p5) :: (invariant load 4 from %fixed-stack.31, addrspace 5)
; CHECK: [[FRAME_INDEX1:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.30 ; CHECK: [[FRAME_INDEX1:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.30
; CHECK: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p5) :: (invariant load 4 from %fixed-stack.30, addrspace 5) ; CHECK: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p5) :: (invariant load 4 from %fixed-stack.30, addrspace 5)
; CHECK: [[FRAME_INDEX2:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.29 ; CHECK: [[FRAME_INDEX2:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.29
; CHECK: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX2]](p5) :: (invariant load 4 from %fixed-stack.29, align 8, addrspace 5) ; CHECK: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX2]](p5) :: (invariant load 4 from %fixed-stack.29, addrspace 5)
; CHECK: [[FRAME_INDEX3:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.28 ; CHECK: [[FRAME_INDEX3:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.28
; CHECK: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX3]](p5) :: (invariant load 4 from %fixed-stack.28, addrspace 5) ; CHECK: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX3]](p5) :: (invariant load 4 from %fixed-stack.28, addrspace 5)
; CHECK: [[FRAME_INDEX4:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.27 ; CHECK: [[FRAME_INDEX4:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.27
; CHECK: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX4]](p5) :: (invariant load 4 from %fixed-stack.27, align 16, addrspace 5) ; CHECK: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX4]](p5) :: (invariant load 4 from %fixed-stack.27, addrspace 5)
; CHECK: [[FRAME_INDEX5:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.26 ; CHECK: [[FRAME_INDEX5:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.26
; CHECK: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX5]](p5) :: (invariant load 4 from %fixed-stack.26, addrspace 5) ; CHECK: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX5]](p5) :: (invariant load 4 from %fixed-stack.26, addrspace 5)
; CHECK: [[FRAME_INDEX6:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.25 ; CHECK: [[FRAME_INDEX6:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.25
; CHECK: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX6]](p5) :: (invariant load 4 from %fixed-stack.25, align 8, addrspace 5) ; CHECK: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX6]](p5) :: (invariant load 4 from %fixed-stack.25, addrspace 5)
; CHECK: [[FRAME_INDEX7:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.24 ; CHECK: [[FRAME_INDEX7:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.24
; CHECK: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX7]](p5) :: (invariant load 4 from %fixed-stack.24, addrspace 5) ; CHECK: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX7]](p5) :: (invariant load 4 from %fixed-stack.24, addrspace 5)
; CHECK: [[FRAME_INDEX8:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.23 ; CHECK: [[FRAME_INDEX8:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.23
; CHECK: [[LOAD8:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX8]](p5) :: (invariant load 4 from %fixed-stack.23, align 16, addrspace 5) ; CHECK: [[LOAD8:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX8]](p5) :: (invariant load 4 from %fixed-stack.23, addrspace 5)
; CHECK: [[FRAME_INDEX9:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.22 ; CHECK: [[FRAME_INDEX9:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.22
; CHECK: [[LOAD9:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX9]](p5) :: (invariant load 4 from %fixed-stack.22, addrspace 5) ; CHECK: [[LOAD9:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX9]](p5) :: (invariant load 4 from %fixed-stack.22, addrspace 5)
; CHECK: [[FRAME_INDEX10:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.21 ; CHECK: [[FRAME_INDEX10:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.21
; CHECK: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX10]](p5) :: (invariant load 4 from %fixed-stack.21, align 8, addrspace 5) ; CHECK: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX10]](p5) :: (invariant load 4 from %fixed-stack.21, addrspace 5)
; CHECK: [[FRAME_INDEX11:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.20 ; CHECK: [[FRAME_INDEX11:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.20
; CHECK: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX11]](p5) :: (invariant load 4 from %fixed-stack.20, addrspace 5) ; CHECK: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX11]](p5) :: (invariant load 4 from %fixed-stack.20, addrspace 5)
; CHECK: [[FRAME_INDEX12:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.19 ; CHECK: [[FRAME_INDEX12:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.19
; CHECK: [[LOAD12:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX12]](p5) :: (invariant load 4 from %fixed-stack.19, align 16, addrspace 5) ; CHECK: [[LOAD12:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX12]](p5) :: (invariant load 4 from %fixed-stack.19, addrspace 5)
; CHECK: [[FRAME_INDEX13:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.18 ; CHECK: [[FRAME_INDEX13:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.18
; CHECK: [[LOAD13:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX13]](p5) :: (invariant load 4 from %fixed-stack.18, addrspace 5) ; CHECK: [[LOAD13:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX13]](p5) :: (invariant load 4 from %fixed-stack.18, addrspace 5)
; CHECK: [[FRAME_INDEX14:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.17 ; CHECK: [[FRAME_INDEX14:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.17
; CHECK: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX14]](p5) :: (invariant load 4 from %fixed-stack.17, align 8, addrspace 5) ; CHECK: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX14]](p5) :: (invariant load 4 from %fixed-stack.17, addrspace 5)
; CHECK: [[FRAME_INDEX15:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.16 ; CHECK: [[FRAME_INDEX15:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.16
; CHECK: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX15]](p5) :: (invariant load 4 from %fixed-stack.16, addrspace 5) ; CHECK: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX15]](p5) :: (invariant load 4 from %fixed-stack.16, addrspace 5)
; CHECK: [[FRAME_INDEX16:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.15 ; CHECK: [[FRAME_INDEX16:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.15
; CHECK: [[LOAD16:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX16]](p5) :: (invariant load 4 from %fixed-stack.15, align 16, addrspace 5) ; CHECK: [[LOAD16:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX16]](p5) :: (invariant load 4 from %fixed-stack.15, addrspace 5)
; CHECK: [[FRAME_INDEX17:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.14 ; CHECK: [[FRAME_INDEX17:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.14
; CHECK: [[LOAD17:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX17]](p5) :: (invariant load 4 from %fixed-stack.14, addrspace 5) ; CHECK: [[LOAD17:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX17]](p5) :: (invariant load 4 from %fixed-stack.14, addrspace 5)
; CHECK: [[FRAME_INDEX18:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.13 ; CHECK: [[FRAME_INDEX18:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.13
; CHECK: [[LOAD18:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX18]](p5) :: (invariant load 4 from %fixed-stack.13, align 8, addrspace 5) ; CHECK: [[LOAD18:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX18]](p5) :: (invariant load 4 from %fixed-stack.13, addrspace 5)
; CHECK: [[FRAME_INDEX19:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.12 ; CHECK: [[FRAME_INDEX19:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.12
; CHECK: [[LOAD19:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX19]](p5) :: (invariant load 4 from %fixed-stack.12, addrspace 5) ; CHECK: [[LOAD19:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX19]](p5) :: (invariant load 4 from %fixed-stack.12, addrspace 5)
; CHECK: [[FRAME_INDEX20:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.11 ; CHECK: [[FRAME_INDEX20:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.11
; CHECK: [[LOAD20:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX20]](p5) :: (invariant load 4 from %fixed-stack.11, align 16, addrspace 5) ; CHECK: [[LOAD20:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX20]](p5) :: (invariant load 4 from %fixed-stack.11, addrspace 5)
; CHECK: [[FRAME_INDEX21:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.10 ; CHECK: [[FRAME_INDEX21:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.10
; CHECK: [[LOAD21:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX21]](p5) :: (invariant load 4 from %fixed-stack.10, addrspace 5) ; CHECK: [[LOAD21:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX21]](p5) :: (invariant load 4 from %fixed-stack.10, addrspace 5)
; CHECK: [[FRAME_INDEX22:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.9 ; CHECK: [[FRAME_INDEX22:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.9
; CHECK: [[LOAD22:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX22]](p5) :: (invariant load 4 from %fixed-stack.9, align 8, addrspace 5) ; CHECK: [[LOAD22:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX22]](p5) :: (invariant load 4 from %fixed-stack.9, addrspace 5)
; CHECK: [[FRAME_INDEX23:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.8 ; CHECK: [[FRAME_INDEX23:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.8
; CHECK: [[LOAD23:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX23]](p5) :: (invariant load 4 from %fixed-stack.8, addrspace 5) ; CHECK: [[LOAD23:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX23]](p5) :: (invariant load 4 from %fixed-stack.8, addrspace 5)
; CHECK: [[FRAME_INDEX24:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.7 ; CHECK: [[FRAME_INDEX24:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.7
; CHECK: [[LOAD24:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX24]](p5) :: (invariant load 4 from %fixed-stack.7, align 16, addrspace 5) ; CHECK: [[LOAD24:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX24]](p5) :: (invariant load 4 from %fixed-stack.7, addrspace 5)
; CHECK: [[FRAME_INDEX25:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.6 ; CHECK: [[FRAME_INDEX25:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.6
; CHECK: [[LOAD25:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX25]](p5) :: (invariant load 4 from %fixed-stack.6, addrspace 5) ; CHECK: [[LOAD25:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX25]](p5) :: (invariant load 4 from %fixed-stack.6, addrspace 5)
; CHECK: [[FRAME_INDEX26:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.5 ; CHECK: [[FRAME_INDEX26:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.5
; CHECK: [[LOAD26:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX26]](p5) :: (invariant load 4 from %fixed-stack.5, align 8, addrspace 5) ; CHECK: [[LOAD26:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX26]](p5) :: (invariant load 4 from %fixed-stack.5, addrspace 5)
; CHECK: [[FRAME_INDEX27:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.4 ; CHECK: [[FRAME_INDEX27:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.4
; CHECK: [[LOAD27:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX27]](p5) :: (invariant load 4 from %fixed-stack.4, addrspace 5) ; CHECK: [[LOAD27:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX27]](p5) :: (invariant load 4 from %fixed-stack.4, addrspace 5)
; CHECK: [[FRAME_INDEX28:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.3 ; CHECK: [[FRAME_INDEX28:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.3
; CHECK: [[LOAD28:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX28]](p5) :: (invariant load 4 from %fixed-stack.3, align 16, addrspace 5) ; CHECK: [[LOAD28:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX28]](p5) :: (invariant load 4 from %fixed-stack.3, addrspace 5)
; CHECK: [[FRAME_INDEX29:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.2 ; CHECK: [[FRAME_INDEX29:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.2
; CHECK: [[LOAD29:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX29]](p5) :: (invariant load 4 from %fixed-stack.2, addrspace 5) ; CHECK: [[LOAD29:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX29]](p5) :: (invariant load 4 from %fixed-stack.2, addrspace 5)
; CHECK: [[FRAME_INDEX30:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.1 ; CHECK: [[FRAME_INDEX30:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.1
; CHECK: [[LOAD30:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX30]](p5) :: (invariant load 4 from %fixed-stack.1, align 8, addrspace 5) ; CHECK: [[LOAD30:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX30]](p5) :: (invariant load 4 from %fixed-stack.1, addrspace 5)
; CHECK: [[FRAME_INDEX31:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.0 ; CHECK: [[FRAME_INDEX31:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.0
; CHECK: [[LOAD31:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX31]](p5) :: (invariant load 4 from %fixed-stack.0, addrspace 5) ; CHECK: [[LOAD31:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX31]](p5) :: (invariant load 4 from %fixed-stack.0, addrspace 5)
; CHECK: [[COPY32:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 ; CHECK: [[COPY32:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32) ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32)
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<16 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32), [[LOAD4]](s32), [[LOAD5]](s32), [[LOAD6]](s32), [[LOAD7]](s32), [[LOAD8]](s32), [[LOAD9]](s32), [[LOAD10]](s32), [[LOAD11]](s32), [[LOAD12]](s32), [[LOAD13]](s32), [[LOAD14]](s32), [[LOAD15]](s32) ; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<16 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32), [[LOAD4]](s32), [[LOAD5]](s32), [[LOAD6]](s32), [[LOAD7]](s32), [[LOAD8]](s32), [[LOAD9]](s32), [[LOAD10]](s32), [[LOAD11]](s32), [[LOAD12]](s32), [[LOAD13]](s32), [[LOAD14]](s32), [[LOAD15]](s32)
; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<16 x s32>) = G_BUILD_VECTOR [[LOAD16]](s32), [[LOAD17]](s32), [[LOAD18]](s32), [[LOAD19]](s32), [[LOAD20]](s32), [[LOAD21]](s32), [[LOAD22]](s32), [[LOAD23]](s32), [[LOAD24]](s32), [[LOAD25]](s32), [[LOAD26]](s32), [[LOAD27]](s32), [[LOAD28]](s32), [[LOAD29]](s32), [[LOAD30]](s32), [[LOAD31]](s32) ; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<16 x s32>) = G_BUILD_VECTOR [[LOAD16]](s32), [[LOAD17]](s32), [[LOAD18]](s32), [[LOAD19]](s32), [[LOAD20]](s32), [[LOAD21]](s32), [[LOAD22]](s32), [[LOAD23]](s32), [[LOAD24]](s32), [[LOAD25]](s32), [[LOAD26]](s32), [[LOAD27]](s32), [[LOAD28]](s32), [[LOAD29]](s32), [[LOAD30]](s32), [[LOAD31]](s32)
; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: [[COPY33:%[0-9]+]]:_(p1) = COPY [[DEF]](p1) ; CHECK: [[COPY33:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)
▲ Show 20 Lines • Show All 158 Lines • ▼ Show 20 Linesdefine void @void_func_v32i32_v16i8(<32 x i32> %arg0, <16 x i8> %arg1) #0 {
; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr25 ; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY $vgpr25
; CHECK: [[COPY26:%[0-9]+]]:_(s32) = COPY $vgpr26 ; CHECK: [[COPY26:%[0-9]+]]:_(s32) = COPY $vgpr26
; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY $vgpr27 ; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY $vgpr27
; CHECK: [[COPY28:%[0-9]+]]:_(s32) = COPY $vgpr28 ; CHECK: [[COPY28:%[0-9]+]]:_(s32) = COPY $vgpr28
; CHECK: [[COPY29:%[0-9]+]]:_(s32) = COPY $vgpr29 ; CHECK: [[COPY29:%[0-9]+]]:_(s32) = COPY $vgpr29
; CHECK: [[COPY30:%[0-9]+]]:_(s32) = COPY $vgpr30 ; CHECK: [[COPY30:%[0-9]+]]:_(s32) = COPY $vgpr30
; CHECK: [[COPY31:%[0-9]+]]:_(s32) = COPY $vgpr31 ; CHECK: [[COPY31:%[0-9]+]]:_(s32) = COPY $vgpr31
; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.15 ; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.15
; CHECK: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX]](p5) :: (invariant load 2 from %fixed-stack.15, align 16, addrspace 5) ; CHECK: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX]](p5) :: (invariant load 2 from %fixed-stack.15, align 4, addrspace 5)
; CHECK: [[FRAME_INDEX1:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.14 ; CHECK: [[FRAME_INDEX1:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.14
; CHECK: [[LOAD1:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX1]](p5) :: (invariant load 2 from %fixed-stack.14, align 4, addrspace 5) ; CHECK: [[LOAD1:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX1]](p5) :: (invariant load 2 from %fixed-stack.14, align 4, addrspace 5)
; CHECK: [[FRAME_INDEX2:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.13 ; CHECK: [[FRAME_INDEX2:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.13
; CHECK: [[LOAD2:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX2]](p5) :: (invariant load 2 from %fixed-stack.13, align 8, addrspace 5) ; CHECK: [[LOAD2:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX2]](p5) :: (invariant load 2 from %fixed-stack.13, align 4, addrspace 5)
; CHECK: [[FRAME_INDEX3:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.12 ; CHECK: [[FRAME_INDEX3:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.12
; CHECK: [[LOAD3:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX3]](p5) :: (invariant load 2 from %fixed-stack.12, align 4, addrspace 5) ; CHECK: [[LOAD3:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX3]](p5) :: (invariant load 2 from %fixed-stack.12, align 4, addrspace 5)
; CHECK: [[FRAME_INDEX4:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.11 ; CHECK: [[FRAME_INDEX4:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.11
; CHECK: [[LOAD4:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX4]](p5) :: (invariant load 2 from %fixed-stack.11, align 16, addrspace 5) ; CHECK: [[LOAD4:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX4]](p5) :: (invariant load 2 from %fixed-stack.11, align 4, addrspace 5)
; CHECK: [[FRAME_INDEX5:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.10 ; CHECK: [[FRAME_INDEX5:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.10
; CHECK: [[LOAD5:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX5]](p5) :: (invariant load 2 from %fixed-stack.10, align 4, addrspace 5) ; CHECK: [[LOAD5:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX5]](p5) :: (invariant load 2 from %fixed-stack.10, align 4, addrspace 5)
; CHECK: [[FRAME_INDEX6:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.9 ; CHECK: [[FRAME_INDEX6:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.9
; CHECK: [[LOAD6:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX6]](p5) :: (invariant load 2 from %fixed-stack.9, align 8, addrspace 5) ; CHECK: [[LOAD6:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX6]](p5) :: (invariant load 2 from %fixed-stack.9, align 4, addrspace 5)
; CHECK: [[FRAME_INDEX7:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.8 ; CHECK: [[FRAME_INDEX7:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.8
; CHECK: [[LOAD7:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX7]](p5) :: (invariant load 2 from %fixed-stack.8, align 4, addrspace 5) ; CHECK: [[LOAD7:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX7]](p5) :: (invariant load 2 from %fixed-stack.8, align 4, addrspace 5)
; CHECK: [[FRAME_INDEX8:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.7 ; CHECK: [[FRAME_INDEX8:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.7
; CHECK: [[LOAD8:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX8]](p5) :: (invariant load 2 from %fixed-stack.7, align 16, addrspace 5) ; CHECK: [[LOAD8:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX8]](p5) :: (invariant load 2 from %fixed-stack.7, align 4, addrspace 5)
; CHECK: [[FRAME_INDEX9:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.6 ; CHECK: [[FRAME_INDEX9:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.6
; CHECK: [[LOAD9:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX9]](p5) :: (invariant load 2 from %fixed-stack.6, align 4, addrspace 5) ; CHECK: [[LOAD9:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX9]](p5) :: (invariant load 2 from %fixed-stack.6, align 4, addrspace 5)
; CHECK: [[FRAME_INDEX10:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.5 ; CHECK: [[FRAME_INDEX10:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.5
; CHECK: [[LOAD10:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX10]](p5) :: (invariant load 2 from %fixed-stack.5, align 8, addrspace 5) ; CHECK: [[LOAD10:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX10]](p5) :: (invariant load 2 from %fixed-stack.5, align 4, addrspace 5)
; CHECK: [[FRAME_INDEX11:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.4 ; CHECK: [[FRAME_INDEX11:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.4
; CHECK: [[LOAD11:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX11]](p5) :: (invariant load 2 from %fixed-stack.4, align 4, addrspace 5) ; CHECK: [[LOAD11:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX11]](p5) :: (invariant load 2 from %fixed-stack.4, align 4, addrspace 5)
; CHECK: [[FRAME_INDEX12:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.3 ; CHECK: [[FRAME_INDEX12:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.3
; CHECK: [[LOAD12:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX12]](p5) :: (invariant load 2 from %fixed-stack.3, align 16, addrspace 5) ; CHECK: [[LOAD12:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX12]](p5) :: (invariant load 2 from %fixed-stack.3, align 4, addrspace 5)
; CHECK: [[FRAME_INDEX13:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.2 ; CHECK: [[FRAME_INDEX13:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.2
; CHECK: [[LOAD13:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX13]](p5) :: (invariant load 2 from %fixed-stack.2, align 4, addrspace 5) ; CHECK: [[LOAD13:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX13]](p5) :: (invariant load 2 from %fixed-stack.2, align 4, addrspace 5)
; CHECK: [[FRAME_INDEX14:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.1 ; CHECK: [[FRAME_INDEX14:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.1
; CHECK: [[LOAD14:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX14]](p5) :: (invariant load 2 from %fixed-stack.1, align 8, addrspace 5) ; CHECK: [[LOAD14:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX14]](p5) :: (invariant load 2 from %fixed-stack.1, align 4, addrspace 5)
; CHECK: [[FRAME_INDEX15:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.0 ; CHECK: [[FRAME_INDEX15:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.0
; CHECK: [[LOAD15:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX15]](p5) :: (invariant load 2 from %fixed-stack.0, align 4, addrspace 5) ; CHECK: [[LOAD15:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX15]](p5) :: (invariant load 2 from %fixed-stack.0, align 4, addrspace 5)
; CHECK: [[COPY32:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 ; CHECK: [[COPY32:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32) ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32)
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<16 x s16>) = G_BUILD_VECTOR [[LOAD]](s16), [[LOAD1]](s16), [[LOAD2]](s16), [[LOAD3]](s16), [[LOAD4]](s16), [[LOAD5]](s16), [[LOAD6]](s16), [[LOAD7]](s16), [[LOAD8]](s16), [[LOAD9]](s16), [[LOAD10]](s16), [[LOAD11]](s16), [[LOAD12]](s16), [[LOAD13]](s16), [[LOAD14]](s16), [[LOAD15]](s16) ; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<16 x s16>) = G_BUILD_VECTOR [[LOAD]](s16), [[LOAD1]](s16), [[LOAD2]](s16), [[LOAD3]](s16), [[LOAD4]](s16), [[LOAD5]](s16), [[LOAD6]](s16), [[LOAD7]](s16), [[LOAD8]](s16), [[LOAD9]](s16), [[LOAD10]](s16), [[LOAD11]](s16), [[LOAD12]](s16), [[LOAD13]](s16), [[LOAD14]](s16), [[LOAD15]](s16)
; CHECK: [[TRUNC:%[0-9]+]]:_(<16 x s8>) = G_TRUNC [[BUILD_VECTOR1]](<16 x s16>) ; CHECK: [[TRUNC:%[0-9]+]]:_(<16 x s8>) = G_TRUNC [[BUILD_VECTOR1]](<16 x s16>)
; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; CHECK: [[COPY33:%[0-9]+]]:_(p1) = COPY [[DEF]](p1) ; CHECK: [[COPY33:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)
Show All 10 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-dyn-stackalloc.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck -check-prefix=WAVE64 %s # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck -check-prefix=WAVE64-NONHSA %s
# XUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck -check-prefix=WAVE64 %s # XUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck -check-prefix=WAVE64-NONHSA %s
# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck -check-prefix=WAVE32 %s # RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck -check-prefix=WAVE32-NONHSA %s
# XUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck -check-prefix=WAVE32 %s # XUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck -check-prefix=WAVE32-NONHSA %s
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck -check-prefix=WAVE64-HSA %s
# XUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck -check-prefix=WAVE64-HSA %s
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck -check-prefix=WAVE32-HSA %s
# XUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck -check-prefix=WAVE32-HSA %s
--- ---
name: test_dyn_stackalloc_sgpr_align1 name: test_dyn_stackalloc_sgpr_align1
legalized: true legalized: true
frameInfo: frameInfo:
maxAlignment: 2 maxAlignment: 2
stack: stack:
- { id: 0, type: variable-sized, alignment: 1 } - { id: 0, type: variable-sized, alignment: 1 }
body: | body: |
bb.0: bb.0:
liveins: $sgpr0 liveins: $sgpr0
; WAVE64-LABEL: name: test_dyn_stackalloc_sgpr_align1 ; WAVE64-NONHSA-LABEL: name: test_dyn_stackalloc_sgpr_align1
; WAVE64: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; WAVE64-NONHSA: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; WAVE64: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6 ; WAVE64-NONHSA: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6
; WAVE64: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32) ; WAVE64-NONHSA: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32)
; WAVE64: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg ; WAVE64-NONHSA: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
; WAVE64: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32) ; WAVE64-NONHSA: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
; WAVE64: S_ENDPGM 0, implicit [[PTR_ADD]](p5) ; WAVE64-NONHSA: S_ENDPGM 0, implicit [[PTR_ADD]](p5)
; WAVE32-LABEL: name: test_dyn_stackalloc_sgpr_align1 ; WAVE32-NONHSA-LABEL: name: test_dyn_stackalloc_sgpr_align1
; WAVE32: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; WAVE32-NONHSA: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; WAVE32: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5 ; WAVE32-NONHSA: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5
; WAVE32: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32) ; WAVE32-NONHSA: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32)
; WAVE32: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg ; WAVE32-NONHSA: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
; WAVE32: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32) ; WAVE32-NONHSA: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
; WAVE32: S_ENDPGM 0, implicit [[PTR_ADD]](p5) ; WAVE32-NONHSA: S_ENDPGM 0, implicit [[PTR_ADD]](p5)
; WAVE64-HSA-LABEL: name: test_dyn_stackalloc_sgpr_align1
; WAVE64-HSA: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; WAVE64-HSA: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6
; WAVE64-HSA: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32)
; WAVE64-HSA: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
; WAVE64-HSA: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
; WAVE64-HSA: S_ENDPGM 0, implicit [[PTR_ADD]](p5)
; WAVE32-HSA-LABEL: name: test_dyn_stackalloc_sgpr_align1
; WAVE32-HSA: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; WAVE32-HSA: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5
; WAVE32-HSA: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32)
; WAVE32-HSA: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
; WAVE32-HSA: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
; WAVE32-HSA: S_ENDPGM 0, implicit [[PTR_ADD]](p5)
%0:_(s32) = COPY $sgpr0 %0:_(s32) = COPY $sgpr0
%1:_(p5) = G_DYN_STACKALLOC %0, 1 %1:_(p5) = G_DYN_STACKALLOC %0, 1
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
--- ---
name: test_dyn_stackalloc_sgpr_align2 name: test_dyn_stackalloc_sgpr_align2
legalized: true legalized: true
frameInfo: frameInfo:
maxAlignment: 2 maxAlignment: 2
stack: stack:
- { id: 0, type: variable-sized, alignment: 2 } - { id: 0, type: variable-sized, alignment: 2 }
body: | body: |
bb.0: bb.0:
liveins: $sgpr0 liveins: $sgpr0
; WAVE64-LABEL: name: test_dyn_stackalloc_sgpr_align2 ; WAVE64-NONHSA-LABEL: name: test_dyn_stackalloc_sgpr_align2
; WAVE64: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; WAVE64-NONHSA: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; WAVE64: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6 ; WAVE64-NONHSA: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6
; WAVE64: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32) ; WAVE64-NONHSA: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32)
; WAVE64: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg ; WAVE64-NONHSA: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
; WAVE64: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32) ; WAVE64-NONHSA: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
; WAVE64: S_ENDPGM 0, implicit [[PTR_ADD]](p5) ; WAVE64-NONHSA: S_ENDPGM 0, implicit [[PTR_ADD]](p5)
; WAVE32-LABEL: name: test_dyn_stackalloc_sgpr_align2 ; WAVE32-NONHSA-LABEL: name: test_dyn_stackalloc_sgpr_align2
; WAVE32: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; WAVE32-NONHSA: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; WAVE32: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5 ; WAVE32-NONHSA: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5
; WAVE32: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32) ; WAVE32-NONHSA: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32)
; WAVE32: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg ; WAVE32-NONHSA: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
; WAVE32: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32) ; WAVE32-NONHSA: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
; WAVE32: S_ENDPGM 0, implicit [[PTR_ADD]](p5) ; WAVE32-NONHSA: S_ENDPGM 0, implicit [[PTR_ADD]](p5)
; WAVE64-HSA-LABEL: name: test_dyn_stackalloc_sgpr_align2
; WAVE64-HSA: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; WAVE64-HSA: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6
; WAVE64-HSA: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32)
; WAVE64-HSA: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
; WAVE64-HSA: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
; WAVE64-HSA: S_ENDPGM 0, implicit [[PTR_ADD]](p5)
; WAVE32-HSA-LABEL: name: test_dyn_stackalloc_sgpr_align2
; WAVE32-HSA: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; WAVE32-HSA: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5
; WAVE32-HSA: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32)
; WAVE32-HSA: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
; WAVE32-HSA: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
; WAVE32-HSA: S_ENDPGM 0, implicit [[PTR_ADD]](p5)
%0:_(s32) = COPY $sgpr0 %0:_(s32) = COPY $sgpr0
%1:_(p5) = G_DYN_STACKALLOC %0, 2 %1:_(p5) = G_DYN_STACKALLOC %0, 2
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
--- ---
name: test_dyn_stackalloc_sgpr_align4 name: test_dyn_stackalloc_sgpr_align4
legalized: true legalized: true
frameInfo: frameInfo:
maxAlignment: 4 maxAlignment: 4
stack: stack:
- { id: 0, type: variable-sized, alignment: 4 } - { id: 0, type: variable-sized, alignment: 4 }
body: | body: |
bb.0: bb.0:
liveins: $sgpr0 liveins: $sgpr0
; WAVE64-LABEL: name: test_dyn_stackalloc_sgpr_align4 ; WAVE64-NONHSA-LABEL: name: test_dyn_stackalloc_sgpr_align4
; WAVE64: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; WAVE64-NONHSA: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; WAVE64: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6 ; WAVE64-NONHSA: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6
; WAVE64: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32) ; WAVE64-NONHSA: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32)
; WAVE64: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg ; WAVE64-NONHSA: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
; WAVE64: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32) ; WAVE64-NONHSA: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
; WAVE64: S_ENDPGM 0, implicit [[PTR_ADD]](p5) ; WAVE64-NONHSA: S_ENDPGM 0, implicit [[PTR_ADD]](p5)
; WAVE32-LABEL: name: test_dyn_stackalloc_sgpr_align4 ; WAVE32-NONHSA-LABEL: name: test_dyn_stackalloc_sgpr_align4
; WAVE32: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; WAVE32-NONHSA: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; WAVE32: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5 ; WAVE32-NONHSA: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5
; WAVE32: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32) ; WAVE32-NONHSA: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32)
; WAVE32: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg ; WAVE32-NONHSA: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
; WAVE32: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32) ; WAVE32-NONHSA: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
; WAVE32: S_ENDPGM 0, implicit [[PTR_ADD]](p5) ; WAVE32-NONHSA: S_ENDPGM 0, implicit [[PTR_ADD]](p5)
; WAVE64-HSA-LABEL: name: test_dyn_stackalloc_sgpr_align4
; WAVE64-HSA: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; WAVE64-HSA: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6
; WAVE64-HSA: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32)
; WAVE64-HSA: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
; WAVE64-HSA: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
; WAVE64-HSA: S_ENDPGM 0, implicit [[PTR_ADD]](p5)
; WAVE32-HSA-LABEL: name: test_dyn_stackalloc_sgpr_align4
; WAVE32-HSA: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; WAVE32-HSA: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5
; WAVE32-HSA: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32)
; WAVE32-HSA: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
; WAVE32-HSA: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
; WAVE32-HSA: S_ENDPGM 0, implicit [[PTR_ADD]](p5)
%0:_(s32) = COPY $sgpr0 %0:_(s32) = COPY $sgpr0
%1:_(p5) = G_DYN_STACKALLOC %0, 4 %1:_(p5) = G_DYN_STACKALLOC %0, 4
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
--- ---
name: test_dyn_stackalloc_sgpr_align8 name: test_dyn_stackalloc_sgpr_align8
legalized: true legalized: true
frameInfo: frameInfo:
maxAlignment: 8 maxAlignment: 8
stack: stack:
- { id: 0, type: variable-sized, alignment: 8 } - { id: 0, type: variable-sized, alignment: 8 }
body: | body: |
bb.0: bb.0:
liveins: $sgpr0 liveins: $sgpr0
; WAVE64-LABEL: name: test_dyn_stackalloc_sgpr_align8 ; WAVE64-NONHSA-LABEL: name: test_dyn_stackalloc_sgpr_align8
; WAVE64: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; WAVE64-NONHSA: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; WAVE64: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6 ; WAVE64-NONHSA: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6
; WAVE64: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32) ; WAVE64-NONHSA: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32)
; WAVE64: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg ; WAVE64-NONHSA: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
; WAVE64: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32) ; WAVE64-NONHSA: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
; WAVE64: S_ENDPGM 0, implicit [[PTR_ADD]](p5) ; WAVE64-NONHSA: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -512
; WAVE32-LABEL: name: test_dyn_stackalloc_sgpr_align8 ; WAVE64-NONHSA: [[PTRMASK:%[0-9]+]]:sgpr(p5) = G_PTRMASK [[PTR_ADD]], [[C1]](s32)
; WAVE32: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; WAVE64-NONHSA: S_ENDPGM 0, implicit [[PTRMASK]](p5)
; WAVE32: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5 ; WAVE32-NONHSA-LABEL: name: test_dyn_stackalloc_sgpr_align8
; WAVE32: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32) ; WAVE32-NONHSA: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; WAVE32: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg ; WAVE32-NONHSA: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5
; WAVE32: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32) ; WAVE32-NONHSA: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32)
; WAVE32: S_ENDPGM 0, implicit [[PTR_ADD]](p5) ; WAVE32-NONHSA: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
; WAVE32-NONHSA: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
; WAVE32-NONHSA: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -256
; WAVE32-NONHSA: [[PTRMASK:%[0-9]+]]:sgpr(p5) = G_PTRMASK [[PTR_ADD]], [[C1]](s32)
; WAVE32-NONHSA: S_ENDPGM 0, implicit [[PTRMASK]](p5)
; WAVE64-HSA-LABEL: name: test_dyn_stackalloc_sgpr_align8
; WAVE64-HSA: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; WAVE64-HSA: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6
; WAVE64-HSA: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32)
; WAVE64-HSA: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
; WAVE64-HSA: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
; WAVE64-HSA: S_ENDPGM 0, implicit [[PTR_ADD]](p5)
; WAVE32-HSA-LABEL: name: test_dyn_stackalloc_sgpr_align8
; WAVE32-HSA: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; WAVE32-HSA: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5
; WAVE32-HSA: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32)
; WAVE32-HSA: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
; WAVE32-HSA: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
; WAVE32-HSA: S_ENDPGM 0, implicit [[PTR_ADD]](p5)
%0:_(s32) = COPY $sgpr0 %0:_(s32) = COPY $sgpr0
%1:_(p5) = G_DYN_STACKALLOC %0, 8 %1:_(p5) = G_DYN_STACKALLOC %0, 8
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
--- ---
name: test_dyn_stackalloc_sgpr_align16 name: test_dyn_stackalloc_sgpr_align16
legalized: true legalized: true
frameInfo: frameInfo:
maxAlignment: 16 maxAlignment: 16
stack: stack:
- { id: 0, type: variable-sized, alignment: 16 } - { id: 0, type: variable-sized, alignment: 16 }
body: | body: |
bb.0: bb.0:
liveins: $sgpr0 liveins: $sgpr0
; WAVE64-LABEL: name: test_dyn_stackalloc_sgpr_align16 ; WAVE64-NONHSA-LABEL: name: test_dyn_stackalloc_sgpr_align16
; WAVE64: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; WAVE64-NONHSA: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; WAVE64: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6 ; WAVE64-NONHSA: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6
; WAVE64: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32) ; WAVE64-NONHSA: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32)
; WAVE64: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg ; WAVE64-NONHSA: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
; WAVE64: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32) ; WAVE64-NONHSA: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
; WAVE64: S_ENDPGM 0, implicit [[PTR_ADD]](p5) ; WAVE64-NONHSA: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -1024
; WAVE32-LABEL: name: test_dyn_stackalloc_sgpr_align16 ; WAVE64-NONHSA: [[PTRMASK:%[0-9]+]]:sgpr(p5) = G_PTRMASK [[PTR_ADD]], [[C1]](s32)
; WAVE32: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; WAVE64-NONHSA: S_ENDPGM 0, implicit [[PTRMASK]](p5)
; WAVE32: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5 ; WAVE32-NONHSA-LABEL: name: test_dyn_stackalloc_sgpr_align16
; WAVE32: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32) ; WAVE32-NONHSA: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; WAVE32: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg ; WAVE32-NONHSA: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5
; WAVE32: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32) ; WAVE32-NONHSA: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32)
; WAVE32: S_ENDPGM 0, implicit [[PTR_ADD]](p5) ; WAVE32-NONHSA: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
; WAVE32-NONHSA: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
; WAVE32-NONHSA: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -512
; WAVE32-NONHSA: [[PTRMASK:%[0-9]+]]:sgpr(p5) = G_PTRMASK [[PTR_ADD]], [[C1]](s32)
; WAVE32-NONHSA: S_ENDPGM 0, implicit [[PTRMASK]](p5)
; WAVE64-HSA-LABEL: name: test_dyn_stackalloc_sgpr_align16
; WAVE64-HSA: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; WAVE64-HSA: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6
; WAVE64-HSA: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32)
; WAVE64-HSA: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
; WAVE64-HSA: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
; WAVE64-HSA: S_ENDPGM 0, implicit [[PTR_ADD]](p5)
; WAVE32-HSA-LABEL: name: test_dyn_stackalloc_sgpr_align16
; WAVE32-HSA: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; WAVE32-HSA: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5
; WAVE32-HSA: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32)
; WAVE32-HSA: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
; WAVE32-HSA: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
; WAVE32-HSA: S_ENDPGM 0, implicit [[PTR_ADD]](p5)
%0:_(s32) = COPY $sgpr0 %0:_(s32) = COPY $sgpr0
%1:_(p5) = G_DYN_STACKALLOC %0, 16 %1:_(p5) = G_DYN_STACKALLOC %0, 16
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
--- ---
name: test_dyn_stackalloc_sgpr_align32 name: test_dyn_stackalloc_sgpr_align32
legalized: true legalized: true
frameInfo: frameInfo:
maxAlignment: 32 maxAlignment: 32
stack: stack:
- { id: 0, type: variable-sized, alignment: 32 } - { id: 0, type: variable-sized, alignment: 32 }
body: | body: |
bb.0: bb.0:
liveins: $sgpr0 liveins: $sgpr0
; WAVE64-LABEL: name: test_dyn_stackalloc_sgpr_align32 ; WAVE64-NONHSA-LABEL: name: test_dyn_stackalloc_sgpr_align32
; WAVE64: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; WAVE64-NONHSA: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; WAVE64: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6 ; WAVE64-NONHSA: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6
; WAVE64: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32) ; WAVE64-NONHSA: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32)
; WAVE64: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg ; WAVE64-NONHSA: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
; WAVE64: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32) ; WAVE64-NONHSA: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
; WAVE64: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -2048 ; WAVE64-NONHSA: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -2048
; WAVE64: [[PTRMASK:%[0-9]+]]:sgpr(p5) = G_PTRMASK [[PTR_ADD]], [[C1]](s32) ; WAVE64-NONHSA: [[PTRMASK:%[0-9]+]]:sgpr(p5) = G_PTRMASK [[PTR_ADD]], [[C1]](s32)
; WAVE64: S_ENDPGM 0, implicit [[PTRMASK]](p5) ; WAVE64-NONHSA: S_ENDPGM 0, implicit [[PTRMASK]](p5)
; WAVE32-LABEL: name: test_dyn_stackalloc_sgpr_align32 ; WAVE32-NONHSA-LABEL: name: test_dyn_stackalloc_sgpr_align32
; WAVE32: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; WAVE32-NONHSA: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; WAVE32: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5 ; WAVE32-NONHSA: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5
; WAVE32: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32) ; WAVE32-NONHSA: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32)
; WAVE32: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg ; WAVE32-NONHSA: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
; WAVE32: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32) ; WAVE32-NONHSA: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
; WAVE32: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -1024 ; WAVE32-NONHSA: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -1024
; WAVE32: [[PTRMASK:%[0-9]+]]:sgpr(p5) = G_PTRMASK [[PTR_ADD]], [[C1]](s32) ; WAVE32-NONHSA: [[PTRMASK:%[0-9]+]]:sgpr(p5) = G_PTRMASK [[PTR_ADD]], [[C1]](s32)
; WAVE32: S_ENDPGM 0, implicit [[PTRMASK]](p5) ; WAVE32-NONHSA: S_ENDPGM 0, implicit [[PTRMASK]](p5)
; WAVE64-HSA-LABEL: name: test_dyn_stackalloc_sgpr_align32
; WAVE64-HSA: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; WAVE64-HSA: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6
; WAVE64-HSA: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32)
; WAVE64-HSA: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
; WAVE64-HSA: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
; WAVE64-HSA: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -2048
; WAVE64-HSA: [[PTRMASK:%[0-9]+]]:sgpr(p5) = G_PTRMASK [[PTR_ADD]], [[C1]](s32)
; WAVE64-HSA: S_ENDPGM 0, implicit [[PTRMASK]](p5)
; WAVE32-HSA-LABEL: name: test_dyn_stackalloc_sgpr_align32
; WAVE32-HSA: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; WAVE32-HSA: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5
; WAVE32-HSA: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32)
; WAVE32-HSA: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
; WAVE32-HSA: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
; WAVE32-HSA: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -1024
; WAVE32-HSA: [[PTRMASK:%[0-9]+]]:sgpr(p5) = G_PTRMASK [[PTR_ADD]], [[C1]](s32)
; WAVE32-HSA: S_ENDPGM 0, implicit [[PTRMASK]](p5)
%0:_(s32) = COPY $sgpr0 %0:_(s32) = COPY $sgpr0
%1:_(p5) = G_DYN_STACKALLOC %0, 32 %1:_(p5) = G_DYN_STACKALLOC %0, 32
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
--- ---
name: test_dyn_stackalloc_sgpr_align64 name: test_dyn_stackalloc_sgpr_align64
legalized: true legalized: true
frameInfo: frameInfo:
maxAlignment: 64 maxAlignment: 64
stack: stack:
- { id: 0, type: variable-sized, alignment: 64 } - { id: 0, type: variable-sized, alignment: 64 }
body: | body: |
bb.0: bb.0:
liveins: $sgpr0 liveins: $sgpr0
; WAVE64-LABEL: name: test_dyn_stackalloc_sgpr_align64 ; WAVE64-NONHSA-LABEL: name: test_dyn_stackalloc_sgpr_align64
; WAVE64: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; WAVE64-NONHSA: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; WAVE64: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6 ; WAVE64-NONHSA: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6
; WAVE64: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32) ; WAVE64-NONHSA: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32)
; WAVE64: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg ; WAVE64-NONHSA: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
; WAVE64: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32) ; WAVE64-NONHSA: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
; WAVE64: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -4096 ; WAVE64-NONHSA: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -4096
; WAVE64: [[PTRMASK:%[0-9]+]]:sgpr(p5) = G_PTRMASK [[PTR_ADD]], [[C1]](s32) ; WAVE64-NONHSA: [[PTRMASK:%[0-9]+]]:sgpr(p5) = G_PTRMASK [[PTR_ADD]], [[C1]](s32)
; WAVE64: S_ENDPGM 0, implicit [[PTRMASK]](p5) ; WAVE64-NONHSA: S_ENDPGM 0, implicit [[PTRMASK]](p5)
; WAVE32-LABEL: name: test_dyn_stackalloc_sgpr_align64 ; WAVE32-NONHSA-LABEL: name: test_dyn_stackalloc_sgpr_align64
; WAVE32: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; WAVE32-NONHSA: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; WAVE32: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5 ; WAVE32-NONHSA: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5
; WAVE32: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32) ; WAVE32-NONHSA: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32)
; WAVE32: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg ; WAVE32-NONHSA: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
; WAVE32: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32) ; WAVE32-NONHSA: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
; WAVE32: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -2048 ; WAVE32-NONHSA: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -2048
; WAVE32: [[PTRMASK:%[0-9]+]]:sgpr(p5) = G_PTRMASK [[PTR_ADD]], [[C1]](s32) ; WAVE32-NONHSA: [[PTRMASK:%[0-9]+]]:sgpr(p5) = G_PTRMASK [[PTR_ADD]], [[C1]](s32)
; WAVE32: S_ENDPGM 0, implicit [[PTRMASK]](p5) ; WAVE32-NONHSA: S_ENDPGM 0, implicit [[PTRMASK]](p5)
; WAVE64-HSA-LABEL: name: test_dyn_stackalloc_sgpr_align64
; WAVE64-HSA: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; WAVE64-HSA: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6
; WAVE64-HSA: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32)
; WAVE64-HSA: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
; WAVE64-HSA: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
; WAVE64-HSA: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -4096
; WAVE64-HSA: [[PTRMASK:%[0-9]+]]:sgpr(p5) = G_PTRMASK [[PTR_ADD]], [[C1]](s32)
; WAVE64-HSA: S_ENDPGM 0, implicit [[PTRMASK]](p5)
; WAVE32-HSA-LABEL: name: test_dyn_stackalloc_sgpr_align64
; WAVE32-HSA: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; WAVE32-HSA: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5
; WAVE32-HSA: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32)
; WAVE32-HSA: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
; WAVE32-HSA: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
; WAVE32-HSA: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -2048
; WAVE32-HSA: [[PTRMASK:%[0-9]+]]:sgpr(p5) = G_PTRMASK [[PTR_ADD]], [[C1]](s32)
; WAVE32-HSA: S_ENDPGM 0, implicit [[PTRMASK]](p5)
%0:_(s32) = COPY $sgpr0 %0:_(s32) = COPY $sgpr0
%1:_(p5) = G_DYN_STACKALLOC %0, 64 %1:_(p5) = G_DYN_STACKALLOC %0, 64
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
--- ---
name: test_dyn_stackalloc_sgpr_align128 name: test_dyn_stackalloc_sgpr_align128
legalized: true legalized: true
frameInfo: frameInfo:
maxAlignment: 64 maxAlignment: 64
stack: stack:
- { id: 0, type: variable-sized, alignment: 128 } - { id: 0, type: variable-sized, alignment: 128 }
body: | body: |
bb.0: bb.0:
liveins: $sgpr0 liveins: $sgpr0
; WAVE64-LABEL: name: test_dyn_stackalloc_sgpr_align128 ; WAVE64-NONHSA-LABEL: name: test_dyn_stackalloc_sgpr_align128
; WAVE64: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; WAVE64-NONHSA: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; WAVE64: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6 ; WAVE64-NONHSA: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6
; WAVE64: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32) ; WAVE64-NONHSA: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32)
; WAVE64: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg ; WAVE64-NONHSA: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
; WAVE64: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32) ; WAVE64-NONHSA: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
; WAVE64: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -8192 ; WAVE64-NONHSA: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -8192
; WAVE64: [[PTRMASK:%[0-9]+]]:sgpr(p5) = G_PTRMASK [[PTR_ADD]], [[C1]](s32) ; WAVE64-NONHSA: [[PTRMASK:%[0-9]+]]:sgpr(p5) = G_PTRMASK [[PTR_ADD]], [[C1]](s32)
; WAVE64: S_ENDPGM 0, implicit [[PTRMASK]](p5) ; WAVE64-NONHSA: S_ENDPGM 0, implicit [[PTRMASK]](p5)
; WAVE32-LABEL: name: test_dyn_stackalloc_sgpr_align128 ; WAVE32-NONHSA-LABEL: name: test_dyn_stackalloc_sgpr_align128
; WAVE32: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; WAVE32-NONHSA: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; WAVE32: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5 ; WAVE32-NONHSA: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5
; WAVE32: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32) ; WAVE32-NONHSA: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32)
; WAVE32: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg ; WAVE32-NONHSA: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
; WAVE32: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32) ; WAVE32-NONHSA: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
; WAVE32: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -4096 ; WAVE32-NONHSA: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -4096
; WAVE32: [[PTRMASK:%[0-9]+]]:sgpr(p5) = G_PTRMASK [[PTR_ADD]], [[C1]](s32) ; WAVE32-NONHSA: [[PTRMASK:%[0-9]+]]:sgpr(p5) = G_PTRMASK [[PTR_ADD]], [[C1]](s32)
; WAVE32: S_ENDPGM 0, implicit [[PTRMASK]](p5) ; WAVE32-NONHSA: S_ENDPGM 0, implicit [[PTRMASK]](p5)
; WAVE64-HSA-LABEL: name: test_dyn_stackalloc_sgpr_align128
; WAVE64-HSA: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; WAVE64-HSA: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6
; WAVE64-HSA: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32)
; WAVE64-HSA: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
; WAVE64-HSA: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
; WAVE64-HSA: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -8192
; WAVE64-HSA: [[PTRMASK:%[0-9]+]]:sgpr(p5) = G_PTRMASK [[PTR_ADD]], [[C1]](s32)
; WAVE64-HSA: S_ENDPGM 0, implicit [[PTRMASK]](p5)
; WAVE32-HSA-LABEL: name: test_dyn_stackalloc_sgpr_align128
; WAVE32-HSA: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; WAVE32-HSA: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5
; WAVE32-HSA: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY]], [[C]](s32)
; WAVE32-HSA: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
; WAVE32-HSA: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY1]], [[SHL]](s32)
; WAVE32-HSA: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -4096
; WAVE32-HSA: [[PTRMASK:%[0-9]+]]:sgpr(p5) = G_PTRMASK [[PTR_ADD]], [[C1]](s32)
; WAVE32-HSA: S_ENDPGM 0, implicit [[PTRMASK]](p5)
%0:_(s32) = COPY $sgpr0 %0:_(s32) = COPY $sgpr0
%1:_(p5) = G_DYN_STACKALLOC %0, 128 %1:_(p5) = G_DYN_STACKALLOC %0, 128
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
--- ---
name: test_dyn_stackalloc_sgpr_constant_align4 name: test_dyn_stackalloc_sgpr_constant_align4
legalized: true legalized: true
frameInfo: frameInfo:
maxAlignment: 4 maxAlignment: 4
stack: stack:
- { id: 0, type: variable-sized, alignment: 4 } - { id: 0, type: variable-sized, alignment: 4 }
body: | body: |
bb.0: bb.0:
; WAVE64-LABEL: name: test_dyn_stackalloc_sgpr_constant_align4 ; WAVE64-NONHSA-LABEL: name: test_dyn_stackalloc_sgpr_constant_align4
; WAVE64: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 32 ; WAVE64-NONHSA: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 32
; WAVE64: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6 ; WAVE64-NONHSA: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6
; WAVE64: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[C]], [[C1]](s32) ; WAVE64-NONHSA: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[C]], [[C1]](s32)
; WAVE64: [[COPY:%[0-9]+]]:sgpr(p5) = COPY $sp_reg ; WAVE64-NONHSA: [[COPY:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
; WAVE64: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY]], [[SHL]](s32) ; WAVE64-NONHSA: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY]], [[SHL]](s32)
; WAVE64: S_ENDPGM 0, implicit [[PTR_ADD]](p5) ; WAVE64-NONHSA: S_ENDPGM 0, implicit [[PTR_ADD]](p5)
; WAVE32-LABEL: name: test_dyn_stackalloc_sgpr_constant_align4 ; WAVE32-NONHSA-LABEL: name: test_dyn_stackalloc_sgpr_constant_align4
; WAVE32: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 32 ; WAVE32-NONHSA: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 32
; WAVE32: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5 ; WAVE32-NONHSA: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5
; WAVE32: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[C]], [[C1]](s32) ; WAVE32-NONHSA: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[C]], [[C1]](s32)
; WAVE32: [[COPY:%[0-9]+]]:sgpr(p5) = COPY $sp_reg ; WAVE32-NONHSA: [[COPY:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
; WAVE32: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY]], [[SHL]](s32) ; WAVE32-NONHSA: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY]], [[SHL]](s32)
; WAVE32: S_ENDPGM 0, implicit [[PTR_ADD]](p5) ; WAVE32-NONHSA: S_ENDPGM 0, implicit [[PTR_ADD]](p5)
; WAVE64-HSA-LABEL: name: test_dyn_stackalloc_sgpr_constant_align4
; WAVE64-HSA: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 32
; WAVE64-HSA: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6
; WAVE64-HSA: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[C]], [[C1]](s32)
; WAVE64-HSA: [[COPY:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
; WAVE64-HSA: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY]], [[SHL]](s32)
; WAVE64-HSA: S_ENDPGM 0, implicit [[PTR_ADD]](p5)
; WAVE32-HSA-LABEL: name: test_dyn_stackalloc_sgpr_constant_align4
; WAVE32-HSA: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 32
; WAVE32-HSA: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5
; WAVE32-HSA: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[C]], [[C1]](s32)
; WAVE32-HSA: [[COPY:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
; WAVE32-HSA: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY]], [[SHL]](s32)
; WAVE32-HSA: S_ENDPGM 0, implicit [[PTR_ADD]](p5)
%0:_(s32) = G_CONSTANT i32 32 %0:_(s32) = G_CONSTANT i32 32
%1:_(p5) = G_DYN_STACKALLOC %0, 4 %1:_(p5) = G_DYN_STACKALLOC %0, 4
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
--- ---
name: test_dyn_stackalloc_sgpr_constant_align8 name: test_dyn_stackalloc_sgpr_constant_align8
legalized: true legalized: true
frameInfo: frameInfo:
maxAlignment: 8 maxAlignment: 8
stack: stack:
- { id: 0, type: variable-sized, alignment: 8 } - { id: 0, type: variable-sized, alignment: 8 }
body: | body: |
bb.0: bb.0:
liveins: $sgpr0 liveins: $sgpr0
; WAVE64-LABEL: name: test_dyn_stackalloc_sgpr_constant_align8 ; WAVE64-NONHSA-LABEL: name: test_dyn_stackalloc_sgpr_constant_align8
; WAVE64: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 32 ; WAVE64-NONHSA: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 32
; WAVE64: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6 ; WAVE64-NONHSA: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6
; WAVE64: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[C]], [[C1]](s32) ; WAVE64-NONHSA: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[C]], [[C1]](s32)
; WAVE64: [[COPY:%[0-9]+]]:sgpr(p5) = COPY $sp_reg ; WAVE64-NONHSA: [[COPY:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
; WAVE64: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY]], [[SHL]](s32) ; WAVE64-NONHSA: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY]], [[SHL]](s32)
; WAVE64: S_ENDPGM 0, implicit [[PTR_ADD]](p5) ; WAVE64-NONHSA: [[C2:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -512
; WAVE32-LABEL: name: test_dyn_stackalloc_sgpr_constant_align8 ; WAVE64-NONHSA: [[PTRMASK:%[0-9]+]]:sgpr(p5) = G_PTRMASK [[PTR_ADD]], [[C2]](s32)
; WAVE32: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 32 ; WAVE64-NONHSA: S_ENDPGM 0, implicit [[PTRMASK]](p5)
; WAVE32: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5 ; WAVE32-NONHSA-LABEL: name: test_dyn_stackalloc_sgpr_constant_align8
; WAVE32: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[C]], [[C1]](s32) ; WAVE32-NONHSA: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 32
; WAVE32: [[COPY:%[0-9]+]]:sgpr(p5) = COPY $sp_reg ; WAVE32-NONHSA: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5
; WAVE32: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY]], [[SHL]](s32) ; WAVE32-NONHSA: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[C]], [[C1]](s32)
; WAVE32: S_ENDPGM 0, implicit [[PTR_ADD]](p5) ; WAVE32-NONHSA: [[COPY:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
; WAVE32-NONHSA: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY]], [[SHL]](s32)
; WAVE32-NONHSA: [[C2:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -256
; WAVE32-NONHSA: [[PTRMASK:%[0-9]+]]:sgpr(p5) = G_PTRMASK [[PTR_ADD]], [[C2]](s32)
; WAVE32-NONHSA: S_ENDPGM 0, implicit [[PTRMASK]](p5)
; WAVE64-HSA-LABEL: name: test_dyn_stackalloc_sgpr_constant_align8
; WAVE64-HSA: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 32
; WAVE64-HSA: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6
; WAVE64-HSA: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[C]], [[C1]](s32)
; WAVE64-HSA: [[COPY:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
; WAVE64-HSA: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY]], [[SHL]](s32)
; WAVE64-HSA: S_ENDPGM 0, implicit [[PTR_ADD]](p5)
; WAVE32-HSA-LABEL: name: test_dyn_stackalloc_sgpr_constant_align8
; WAVE32-HSA: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 32
; WAVE32-HSA: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5
; WAVE32-HSA: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[C]], [[C1]](s32)
; WAVE32-HSA: [[COPY:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
; WAVE32-HSA: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY]], [[SHL]](s32)
; WAVE32-HSA: S_ENDPGM 0, implicit [[PTR_ADD]](p5)
%0:_(s32) = G_CONSTANT i32 32 %0:_(s32) = G_CONSTANT i32 32
%1:_(p5) = G_DYN_STACKALLOC %0, 8 %1:_(p5) = G_DYN_STACKALLOC %0, 8
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
--- ---
name: test_dyn_stackalloc_sgpr_constant_align16 name: test_dyn_stackalloc_sgpr_constant_align16
legalized: true legalized: true
frameInfo: frameInfo:
maxAlignment: 16 maxAlignment: 16
stack: stack:
- { id: 0, type: variable-sized, alignment: 16 } - { id: 0, type: variable-sized, alignment: 16 }
body: | body: |
bb.0: bb.0:
liveins: $sgpr0 liveins: $sgpr0
; WAVE64-LABEL: name: test_dyn_stackalloc_sgpr_constant_align16 ; WAVE64-NONHSA-LABEL: name: test_dyn_stackalloc_sgpr_constant_align16
; WAVE64: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 32 ; WAVE64-NONHSA: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 32
; WAVE64: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6 ; WAVE64-NONHSA: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6
; WAVE64: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[C]], [[C1]](s32) ; WAVE64-NONHSA: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[C]], [[C1]](s32)
; WAVE64: [[COPY:%[0-9]+]]:sgpr(p5) = COPY $sp_reg ; WAVE64-NONHSA: [[COPY:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
; WAVE64: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY]], [[SHL]](s32) ; WAVE64-NONHSA: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY]], [[SHL]](s32)
; WAVE64: S_ENDPGM 0, implicit [[PTR_ADD]](p5) ; WAVE64-NONHSA: [[C2:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -1024
; WAVE32-LABEL: name: test_dyn_stackalloc_sgpr_constant_align16 ; WAVE64-NONHSA: [[PTRMASK:%[0-9]+]]:sgpr(p5) = G_PTRMASK [[PTR_ADD]], [[C2]](s32)
; WAVE32: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 32 ; WAVE64-NONHSA: S_ENDPGM 0, implicit [[PTRMASK]](p5)
; WAVE32: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5 ; WAVE32-NONHSA-LABEL: name: test_dyn_stackalloc_sgpr_constant_align16
; WAVE32: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[C]], [[C1]](s32) ; WAVE32-NONHSA: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 32
; WAVE32: [[COPY:%[0-9]+]]:sgpr(p5) = COPY $sp_reg ; WAVE32-NONHSA: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5
; WAVE32: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY]], [[SHL]](s32) ; WAVE32-NONHSA: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[C]], [[C1]](s32)
; WAVE32: S_ENDPGM 0, implicit [[PTR_ADD]](p5) ; WAVE32-NONHSA: [[COPY:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
; WAVE32-NONHSA: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY]], [[SHL]](s32)
; WAVE32-NONHSA: [[C2:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -512
; WAVE32-NONHSA: [[PTRMASK:%[0-9]+]]:sgpr(p5) = G_PTRMASK [[PTR_ADD]], [[C2]](s32)
; WAVE32-NONHSA: S_ENDPGM 0, implicit [[PTRMASK]](p5)
; WAVE64-HSA-LABEL: name: test_dyn_stackalloc_sgpr_constant_align16
; WAVE64-HSA: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 32
; WAVE64-HSA: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6
; WAVE64-HSA: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[C]], [[C1]](s32)
; WAVE64-HSA: [[COPY:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
; WAVE64-HSA: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY]], [[SHL]](s32)
; WAVE64-HSA: S_ENDPGM 0, implicit [[PTR_ADD]](p5)
; WAVE32-HSA-LABEL: name: test_dyn_stackalloc_sgpr_constant_align16
; WAVE32-HSA: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 32
; WAVE32-HSA: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5
; WAVE32-HSA: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[C]], [[C1]](s32)
; WAVE32-HSA: [[COPY:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
; WAVE32-HSA: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY]], [[SHL]](s32)
; WAVE32-HSA: S_ENDPGM 0, implicit [[PTR_ADD]](p5)
%0:_(s32) = G_CONSTANT i32 32 %0:_(s32) = G_CONSTANT i32 32
%1:_(p5) = G_DYN_STACKALLOC %0, 16 %1:_(p5) = G_DYN_STACKALLOC %0, 16
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...
--- ---
name: test_dyn_stackalloc_sgpr_constant_align32 name: test_dyn_stackalloc_sgpr_constant_align32
legalized: true legalized: true
frameInfo: frameInfo:
maxAlignment: 32 maxAlignment: 32
stack: stack:
- { id: 0, type: variable-sized, alignment: 32 } - { id: 0, type: variable-sized, alignment: 32 }
body: | body: |
bb.0: bb.0:
liveins: $sgpr0 liveins: $sgpr0
; WAVE64-LABEL: name: test_dyn_stackalloc_sgpr_constant_align32 ; WAVE64-NONHSA-LABEL: name: test_dyn_stackalloc_sgpr_constant_align32
; WAVE64: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 32 ; WAVE64-NONHSA: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 32
; WAVE64: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6 ; WAVE64-NONHSA: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6
; WAVE64: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[C]], [[C1]](s32) ; WAVE64-NONHSA: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[C]], [[C1]](s32)
; WAVE64: [[COPY:%[0-9]+]]:sgpr(p5) = COPY $sp_reg ; WAVE64-NONHSA: [[COPY:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
; WAVE64: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY]], [[SHL]](s32) ; WAVE64-NONHSA: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY]], [[SHL]](s32)
; WAVE64: [[C2:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -2048 ; WAVE64-NONHSA: [[C2:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -2048
; WAVE64: [[PTRMASK:%[0-9]+]]:sgpr(p5) = G_PTRMASK [[PTR_ADD]], [[C2]](s32) ; WAVE64-NONHSA: [[PTRMASK:%[0-9]+]]:sgpr(p5) = G_PTRMASK [[PTR_ADD]], [[C2]](s32)
; WAVE64: S_ENDPGM 0, implicit [[PTRMASK]](p5) ; WAVE64-NONHSA: S_ENDPGM 0, implicit [[PTRMASK]](p5)
; WAVE32-LABEL: name: test_dyn_stackalloc_sgpr_constant_align32 ; WAVE32-NONHSA-LABEL: name: test_dyn_stackalloc_sgpr_constant_align32
; WAVE32: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 32 ; WAVE32-NONHSA: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 32
; WAVE32: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5 ; WAVE32-NONHSA: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5
; WAVE32: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[C]], [[C1]](s32) ; WAVE32-NONHSA: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[C]], [[C1]](s32)
; WAVE32: [[COPY:%[0-9]+]]:sgpr(p5) = COPY $sp_reg ; WAVE32-NONHSA: [[COPY:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
; WAVE32: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY]], [[SHL]](s32) ; WAVE32-NONHSA: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY]], [[SHL]](s32)
; WAVE32: [[C2:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -1024 ; WAVE32-NONHSA: [[C2:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -1024
; WAVE32: [[PTRMASK:%[0-9]+]]:sgpr(p5) = G_PTRMASK [[PTR_ADD]], [[C2]](s32) ; WAVE32-NONHSA: [[PTRMASK:%[0-9]+]]:sgpr(p5) = G_PTRMASK [[PTR_ADD]], [[C2]](s32)
; WAVE32: S_ENDPGM 0, implicit [[PTRMASK]](p5) ; WAVE32-NONHSA: S_ENDPGM 0, implicit [[PTRMASK]](p5)
; WAVE64-HSA-LABEL: name: test_dyn_stackalloc_sgpr_constant_align32
; WAVE64-HSA: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 32
; WAVE64-HSA: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6
; WAVE64-HSA: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[C]], [[C1]](s32)
; WAVE64-HSA: [[COPY:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
; WAVE64-HSA: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY]], [[SHL]](s32)
; WAVE64-HSA: [[C2:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -2048
; WAVE64-HSA: [[PTRMASK:%[0-9]+]]:sgpr(p5) = G_PTRMASK [[PTR_ADD]], [[C2]](s32)
; WAVE64-HSA: S_ENDPGM 0, implicit [[PTRMASK]](p5)
; WAVE32-HSA-LABEL: name: test_dyn_stackalloc_sgpr_constant_align32
; WAVE32-HSA: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 32
; WAVE32-HSA: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 5
; WAVE32-HSA: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[C]], [[C1]](s32)
; WAVE32-HSA: [[COPY:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
; WAVE32-HSA: [[PTR_ADD:%[0-9]+]]:sgpr(p5) = G_PTR_ADD [[COPY]], [[SHL]](s32)
; WAVE32-HSA: [[C2:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -1024
; WAVE32-HSA: [[PTRMASK:%[0-9]+]]:sgpr(p5) = G_PTRMASK [[PTR_ADD]], [[C2]](s32)
; WAVE32-HSA: S_ENDPGM 0, implicit [[PTRMASK]](p5)
%0:_(s32) = G_CONSTANT i32 32 %0:_(s32) = G_CONSTANT i32 32
%1:_(p5) = G_DYN_STACKALLOC %0, 32 %1:_(p5) = G_DYN_STACKALLOC %0, 32
S_ENDPGM 0, implicit %1 S_ENDPGM 0, implicit %1
... ...

llvm/test/CodeGen/AMDGPU/call-argument-types.ll

Show First 20 Lines • Show All 647 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @test_call_external_void_func_struct_i8_i32() #0 {
%val = load { i8, i32 }, { i8, i32 } addrspace(1)* %ptr0 %val = load { i8, i32 }, { i8, i32 } addrspace(1)* %ptr0
call void @external_void_func_struct_i8_i32({ i8, i32 } %val) call void @external_void_func_struct_i8_i32({ i8, i32 } %val)
ret void ret void
} }
; GCN-LABEL: {{^}}test_call_external_void_func_byval_struct_i8_i32: ; GCN-LABEL: {{^}}test_call_external_void_func_byval_struct_i8_i32:
; GCN-DAG: v_mov_b32_e32 [[VAL0:v[0-9]+]], 3 ; GCN-DAG: v_mov_b32_e32 [[VAL0:v[0-9]+]], 3
; GCN-DAG: v_mov_b32_e32 [[VAL1:v[0-9]+]], 8 ; GCN-DAG: v_mov_b32_e32 [[VAL1:v[0-9]+]], 8
; MESA-DAG: buffer_store_byte [[VAL0]], off, s[36:39], 0 offset:8 ; MESA-DAG: buffer_store_byte [[VAL0]], off, s[36:39], 0 offset:4
; MESA-DAG: buffer_store_dword [[VAL1]], off, s[36:39], 0 offset:12 ; MESA-DAG: buffer_store_dword [[VAL1]], off, s[36:39], 0 offset:8
; HSA-DAG: buffer_store_byte [[VAL0]], off, s[0:3], 0 offset:8 ; HSA-DAG: buffer_store_byte [[VAL0]], off, s[0:3], 0 offset:8
; HSA-DAG: buffer_store_dword [[VAL1]], off, s[0:3], 0 offset:12 ; HSA-DAG: buffer_store_dword [[VAL1]], off, s[0:3], 0 offset:12
; HSA: buffer_load_dword [[RELOAD_VAL0:v[0-9]+]], off, s[0:3], 0 offset:8 ; HSA: buffer_load_dword [[RELOAD_VAL0:v[0-9]+]], off, s[0:3], 0 offset:8
; HSA: buffer_load_dword [[RELOAD_VAL1:v[0-9]+]], off, s[0:3], 0 offset:12 ; HSA: buffer_load_dword [[RELOAD_VAL1:v[0-9]+]], off, s[0:3], 0 offset:12
; MESA: buffer_load_dword [[RELOAD_VAL0:v[0-9]+]], off, s[36:39], 0 offset:8 ; MESA: buffer_load_dword [[RELOAD_VAL0:v[0-9]+]], off, s[36:39], 0 offset:4
; MESA: buffer_load_dword [[RELOAD_VAL1:v[0-9]+]], off, s[36:39], 0 offset:12 ; MESA: buffer_load_dword [[RELOAD_VAL1:v[0-9]+]], off, s[36:39], 0 offset:8
; GCN-DAG: s_movk_i32 [[SP:s[0-9]+]], 0x400{{$}} ; HSA-DAG: s_movk_i32 [[SP:s[0-9]+]], 0x400{{$}}
; MESA-DAG: s_movk_i32 [[SP:s[0-9]+]], 0x300{{$}}
; HSA-DAG: buffer_store_dword [[RELOAD_VAL0]], off, s[0:3], [[SP]]{{$}} ; HSA-DAG: buffer_store_dword [[RELOAD_VAL0]], off, s[0:3], [[SP]]{{$}}
; HSA-DAG: buffer_store_dword [[RELOAD_VAL1]], off, s[0:3], [[SP]] offset:4 ; HSA-DAG: buffer_store_dword [[RELOAD_VAL1]], off, s[0:3], [[SP]] offset:4
; MESA-DAG: buffer_store_dword [[RELOAD_VAL0]], off, s[36:39], [[SP]]{{$}} ; MESA-DAG: buffer_store_dword [[RELOAD_VAL0]], off, s[36:39], [[SP]]{{$}}
; MESA-DAG: buffer_store_dword [[RELOAD_VAL1]], off, s[36:39], [[SP]] offset:4 ; MESA-DAG: buffer_store_dword [[RELOAD_VAL1]], off, s[36:39], [[SP]] offset:4
; GCN-NEXT: s_swappc_b64 ; GCN-NEXT: s_swappc_b64
; GCN-NOT: [[SP]] ; GCN-NOT: [[SP]]
define amdgpu_kernel void @test_call_external_void_func_byval_struct_i8_i32() #0 { define amdgpu_kernel void @test_call_external_void_func_byval_struct_i8_i32() #0 {
%val = alloca { i8, i32 }, align 4, addrspace(5) %val = alloca { i8, i32 }, align 4, addrspace(5)
%gep0 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %val, i32 0, i32 0 %gep0 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %val, i32 0, i32 0
%gep1 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %val, i32 0, i32 1 %gep1 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %val, i32 0, i32 1
store i8 3, i8 addrspace(5)* %gep0 store i8 3, i8 addrspace(5)* %gep0
store i32 8, i32 addrspace(5)* %gep1 store i32 8, i32 addrspace(5)* %gep1
call void @external_void_func_byval_struct_i8_i32({ i8, i32 } addrspace(5)* %val) call void @external_void_func_byval_struct_i8_i32({ i8, i32 } addrspace(5)* %val)
ret void ret void
} }
; GCN-LABEL: {{^}}test_call_external_void_func_sret_struct_i8_i32_byval_struct_i8_i32: ; GCN-LABEL: {{^}}test_call_external_void_func_sret_struct_i8_i32_byval_struct_i8_i32:
; GCN-DAG: s_movk_i32 [[SP:s[0-9]+]], 0x800{{$}} ; HSA-DAG: s_movk_i32 [[SP:s[0-9]+]], 0x800{{$}}
; MESA-DAG: s_movk_i32 [[SP:s[0-9]+]], 0x500{{$}}
; GCN-DAG: v_mov_b32_e32 [[VAL0:v[0-9]+]], 3 ; GCN-DAG: v_mov_b32_e32 [[VAL0:v[0-9]+]], 3
; GCN-DAG: v_mov_b32_e32 [[VAL1:v[0-9]+]], 8 ; GCN-DAG: v_mov_b32_e32 [[VAL1:v[0-9]+]], 8
; GCN-DAG: buffer_store_byte [[VAL0]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:8 ; HSA-DAG: buffer_store_byte [[VAL0]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:8
; GCN-DAG: buffer_store_dword [[VAL1]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:12 ; HSA-DAG: buffer_store_dword [[VAL1]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:12
; MESA-DAG: buffer_store_byte [[VAL0]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:4
; GCN-DAG: buffer_load_dword [[RELOAD_VAL0:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:8 ; MESA-DAG: buffer_store_dword [[VAL1]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:8
; GCN-DAG: buffer_load_dword [[RELOAD_VAL1:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:12
; HSA-DAG: buffer_load_dword [[RELOAD_VAL0:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:8
; HSA-DAG: buffer_load_dword [[RELOAD_VAL1:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:12
; MESA-DAG: buffer_load_dword [[RELOAD_VAL0:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:4
; MESA-DAG: buffer_load_dword [[RELOAD_VAL1:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:8
; GCN-NOT: s_add_u32 [[SP]] ; GCN-NOT: s_add_u32 [[SP]]
; GCN-DAG: buffer_store_dword [[RELOAD_VAL0]], off, s{{\[[0-9]+:[0-9]+\]}}, [[SP]]{{$}} ; GCN-DAG: buffer_store_dword [[RELOAD_VAL0]], off, s{{\[[0-9]+:[0-9]+\]}}, [[SP]]{{$}}
; GCN-DAG: buffer_store_dword [[RELOAD_VAL1]], off, s{{\[[0-9]+:[0-9]+\]}}, [[SP]] offset:4 ; GCN-DAG: buffer_store_dword [[RELOAD_VAL1]], off, s{{\[[0-9]+:[0-9]+\]}}, [[SP]] offset:4
; GCN: s_swappc_b64 ; GCN: s_swappc_b64
; GCN-DAG: buffer_load_ubyte [[LOAD_OUT_VAL0:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:16 ; HSA-DAG: buffer_load_ubyte [[LOAD_OUT_VAL0:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:16
; GCN-DAG: buffer_load_dword [[LOAD_OUT_VAL1:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:20 ; HSA-DAG: buffer_load_dword [[LOAD_OUT_VAL1:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:20
; MESA-DAG: buffer_load_ubyte [[LOAD_OUT_VAL0:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:12
; MESA-DAG: buffer_load_dword [[LOAD_OUT_VAL1:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:16
; GCN-NOT: s_sub_u32 [[SP]] ; GCN-NOT: s_sub_u32 [[SP]]
; GCN: buffer_store_byte [[LOAD_OUT_VAL0]], off ; GCN: buffer_store_byte [[LOAD_OUT_VAL0]], off
; GCN: buffer_store_dword [[LOAD_OUT_VAL1]], off ; GCN: buffer_store_dword [[LOAD_OUT_VAL1]], off
define amdgpu_kernel void @test_call_external_void_func_sret_struct_i8_i32_byval_struct_i8_i32(i32) #0 { define amdgpu_kernel void @test_call_external_void_func_sret_struct_i8_i32_byval_struct_i8_i32(i32) #0 {
%in.val = alloca { i8, i32 }, align 4, addrspace(5) %in.val = alloca { i8, i32 }, align 4, addrspace(5)
%out.val = alloca { i8, i32 }, align 4, addrspace(5) %out.val = alloca { i8, i32 }, align 4, addrspace(5)
%in.gep0 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %in.val, i32 0, i32 0 %in.gep0 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %in.val, i32 0, i32 0
Show All 25 Lines
; GCN: s_swappc_b64 ; GCN: s_swappc_b64
define amdgpu_kernel void @stack_passed_arg_alignment_v32i32_f64(<32 x i32> %val, double %tmp) #0 { define amdgpu_kernel void @stack_passed_arg_alignment_v32i32_f64(<32 x i32> %val, double %tmp) #0 {
entry: entry:
call void @stack_passed_f64_arg(<32 x i32> %val, double %tmp) call void @stack_passed_f64_arg(<32 x i32> %val, double %tmp)
ret void ret void
} }
; GCN-LABEL: {{^}}tail_call_byval_align16: ; GCN-LABEL: {{^}}tail_call_byval_align16:
; GCN-NOT: s32 ; HSA-NOT: s32
; GCN: buffer_load_dword v32, off, s[0:3], s32 offset:12 ; HSA: buffer_load_dword v32, off, s[0:3], s32 offset:12
; GCN: buffer_load_dword v33, off, s[0:3], s32 offset:8 ; HSA: buffer_load_dword v33, off, s[0:3], s32 offset:8
; MESA: buffer_load_dword v32, off, s[0:3], s33 offset:12
; MESA: buffer_load_dword v33, off, s[0:3], s33 offset:8
; GCN: s_getpc_b64 ; GCN: s_getpc_b64
; GCN: buffer_store_dword v32, off, s[0:3], s32 offset:4 ; HSA: buffer_store_dword v32, off, s[0:3], s32 offset:4
; GCN: buffer_store_dword v33, off, s[0:3], s32{{$}} ; HSA: buffer_store_dword v33, off, s[0:3], s32{{$}}
; GCN-NOT: s32 ; MESA: buffer_store_dword v32, off, s[0:3], s34 offset:4
; MESA: buffer_store_dword v33, off, s[0:3], s34{{$}}
; HSA-NOT: s32
; GCN: s_setpc_b64 ; GCN: s_setpc_b64
define void @tail_call_byval_align16(<32 x i32> %val, double %tmp) #0 { define void @tail_call_byval_align16(<32 x i32> %val, double %tmp) #0 {
entry: entry:
%alloca = alloca double, align 8, addrspace(5) %alloca = alloca double, align 8, addrspace(5)
tail call void @byval_align16_f64_arg(<32 x i32> %val, double addrspace(5)* byval align 16 %alloca) tail call void @byval_align16_f64_arg(<32 x i32> %val, double addrspace(5)* byval align 16 %alloca)
ret void ret void
} }
▲ Show 20 Lines • Show All 155 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll

Show First 20 Lines • Show All 76 Lines • ▼ Show 20 Lines
; GCN-LABEL: {{^}}callee_with_stack_and_call: ; GCN-LABEL: {{^}}callee_with_stack_and_call:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt ; GCN-NEXT: s_waitcnt
; GCN: s_or_saveexec_b64 [[COPY_EXEC0:s\[[0-9]+:[0-9]+\]]], -1{{$}} ; GCN: s_or_saveexec_b64 [[COPY_EXEC0:s\[[0-9]+:[0-9]+\]]], -1{{$}}
; GCN-NEXT: buffer_store_dword [[CSR_VGPR:v[0-9]+]], off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword [[CSR_VGPR:v[0-9]+]], off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GCN-NEXT: s_mov_b64 exec, [[COPY_EXEC0]] ; GCN-NEXT: s_mov_b64 exec, [[COPY_EXEC0]]
; GCN: v_writelane_b32 [[CSR_VGPR]], s33, 2 ; GCN: v_writelane_b32 [[CSR_VGPR]], s33, 2
; GCN-DAG: s_mov_b32 s33, s32 ; GCN-DAG: s_mov_b32 s33, s32
; GCN-DAG: s_add_u32 s32, s32, 0x400{{$}} ; GCN-DAG: s_add_u32 s32, s32, 0x300{{$}}
; GCN-DAG: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0{{$}}
; GCN-DAG: v_writelane_b32 [[CSR_VGPR]], s30, ; GCN-DAG: v_writelane_b32 [[CSR_VGPR]], s30,
; GCN-DAG: v_writelane_b32 [[CSR_VGPR]], s31, ; GCN-DAG: v_writelane_b32 [[CSR_VGPR]], s31,
; GCN-DAG: buffer_store_dword [[ZERO]], off, s[0:3], s33{{$}} ; GCN-DAG: buffer_store_dword [[ZERO]], off, s[0:3], s33{{$}}
; GCN: s_swappc_b64 ; GCN: s_swappc_b64
; GCN-DAG: v_readlane_b32 s5, [[CSR_VGPR]] ; GCN-DAG: v_readlane_b32 s5, [[CSR_VGPR]]
; GCN-DAG: v_readlane_b32 s4, [[CSR_VGPR]] ; GCN-DAG: v_readlane_b32 s4, [[CSR_VGPR]]
; GCN: s_sub_u32 s32, s32, 0x400{{$}} ; GCN: s_sub_u32 s32, s32, 0x300{{$}}
; GCN-NEXT: v_readlane_b32 s33, [[CSR_VGPR]], 2 ; GCN-NEXT: v_readlane_b32 s33, [[CSR_VGPR]], 2
; GCN-NEXT: s_or_saveexec_b64 [[COPY_EXEC1:s\[[0-9]+:[0-9]+\]]], -1{{$}} ; GCN-NEXT: s_or_saveexec_b64 [[COPY_EXEC1:s\[[0-9]+:[0-9]+\]]], -1{{$}}
; GCN-NEXT: buffer_load_dword [[CSR_VGPR]], off, s[0:3], s32 offset:4 ; 4-byte Folded Reload ; GCN-NEXT: buffer_load_dword [[CSR_VGPR]], off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; GCN-NEXT: s_mov_b64 exec, [[COPY_EXEC1]] ; GCN-NEXT: s_mov_b64 exec, [[COPY_EXEC1]]
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: s_setpc_b64 ; GCN-NEXT: s_setpc_b64
define void @callee_with_stack_and_call() #0 { define void @callee_with_stack_and_call() #0 {
Show All 9 Lines
; There is stack usage only because of the need to evict a VGPR for ; There is stack usage only because of the need to evict a VGPR for
; spilling CSR SGPRs. ; spilling CSR SGPRs.
; GCN-LABEL: {{^}}callee_no_stack_with_call: ; GCN-LABEL: {{^}}callee_no_stack_with_call:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GCN-NEXT: s_or_saveexec_b64 [[COPY_EXEC0:s\[[0-9]+:[0-9]+\]]], -1{{$}} ; GCN-NEXT: s_or_saveexec_b64 [[COPY_EXEC0:s\[[0-9]+:[0-9]+\]]], -1{{$}}
; GCN-NEXT: buffer_store_dword [[CSR_VGPR:v[0-9]+]], off, s[0:3], s32 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword [[CSR_VGPR:v[0-9]+]], off, s[0:3], s32 ; 4-byte Folded Spill
; GCN-NEXT: s_mov_b64 exec, [[COPY_EXEC0]] ; GCN-NEXT: s_mov_b64 exec, [[COPY_EXEC0]]
; GCN-DAG: s_add_u32 s32, s32, 0x400 ; GCN-DAG: s_add_u32 s32, s32, 0x200
; GCN-DAG: v_writelane_b32 [[CSR_VGPR]], s33, [[FP_SPILL_LANE:[0-9]+]] ; GCN-DAG: v_writelane_b32 [[CSR_VGPR]], s33, [[FP_SPILL_LANE:[0-9]+]]
; GCN-DAG: v_writelane_b32 [[CSR_VGPR]], s30, 0 ; GCN-DAG: v_writelane_b32 [[CSR_VGPR]], s30, 0
; GCN-DAG: v_writelane_b32 [[CSR_VGPR]], s31, 1 ; GCN-DAG: v_writelane_b32 [[CSR_VGPR]], s31, 1
; GCN: s_swappc_b64 ; GCN: s_swappc_b64
; GCN-DAG: v_readlane_b32 s4, v40, 0 ; GCN-DAG: v_readlane_b32 s4, v40, 0
; GCN-DAG: v_readlane_b32 s5, v40, 1 ; GCN-DAG: v_readlane_b32 s5, v40, 1
; GCN: s_sub_u32 s32, s32, 0x400 ; GCN: s_sub_u32 s32, s32, 0x200
; GCN-NEXT: v_readlane_b32 s33, [[CSR_VGPR]], [[FP_SPILL_LANE]] ; GCN-NEXT: v_readlane_b32 s33, [[CSR_VGPR]], [[FP_SPILL_LANE]]
; GCN-NEXT: s_or_saveexec_b64 [[COPY_EXEC1:s\[[0-9]+:[0-9]+\]]], -1{{$}} ; GCN-NEXT: s_or_saveexec_b64 [[COPY_EXEC1:s\[[0-9]+:[0-9]+\]]], -1{{$}}
; GCN-NEXT: buffer_load_dword [[CSR_VGPR]], off, s[0:3], s32 ; 4-byte Folded Reload ; GCN-NEXT: buffer_load_dword [[CSR_VGPR]], off, s[0:3], s32 ; 4-byte Folded Reload
; GCN-NEXT: s_mov_b64 exec, [[COPY_EXEC1]] ; GCN-NEXT: s_mov_b64 exec, [[COPY_EXEC1]]
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: s_setpc_b64 ; GCN-NEXT: s_setpc_b64
define void @callee_no_stack_with_call() #0 { define void @callee_no_stack_with_call() #0 {
call void @external_void_func_void() call void @external_void_func_void()
▲ Show 20 Lines • Show All 300 Lines • ▼ Show 20 Linesdefine internal void @local_empty_func() #0 {
ret void ret void
} }
; An FP is needed, despite not needing any spills ; An FP is needed, despite not needing any spills
; TODO: Ccould see callee does not use stack and omit FP. ; TODO: Ccould see callee does not use stack and omit FP.
; GCN-LABEL: {{^}}ipra_call_with_stack: ; GCN-LABEL: {{^}}ipra_call_with_stack:
; GCN: s_mov_b32 [[FP_COPY:s[0-9]+]], s33 ; GCN: s_mov_b32 [[FP_COPY:s[0-9]+]], s33
; GCN: s_mov_b32 s33, s32 ; GCN: s_mov_b32 s33, s32
; GCN: s_add_u32 s32, s32, 0x400 ; GCN: s_add_u32 s32, s32, 0x200
; GCN: buffer_store_dword v{{[0-9]+}}, off, s[0:3], s33{{$}} ; GCN: buffer_store_dword v{{[0-9]+}}, off, s[0:3], s33{{$}}
; GCN: s_swappc_b64 ; GCN: s_swappc_b64
; GCN: s_sub_u32 s32, s32, 0x400 ; GCN: s_sub_u32 s32, s32, 0x200
; GCN: s_mov_b32 s33, [[FP_COPY:s[0-9]+]] ; GCN: s_mov_b32 s33, [[FP_COPY:s[0-9]+]]
define void @ipra_call_with_stack() #0 { define void @ipra_call_with_stack() #0 {
%alloca = alloca i32, addrspace(5) %alloca = alloca i32, addrspace(5)
store volatile i32 0, i32 addrspace(5)* %alloca store volatile i32 0, i32 addrspace(5)* %alloca
call void @local_empty_func() call void @local_empty_func()
ret void ret void
} }
▲ Show 20 Lines • Show All 102 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/function-args.ll

Show First 20 Lines • Show All 538 Lines • ▼ Show 20 Linesdefine void @void_func_byval_struct_i8_i32_x2({ i8, i32 } addrspace(5)* byval %arg0, { i8, i32 } addrspace(5)* byval %arg1, i32 %arg2) #0 {
%arg1.load = load volatile { i8, i32 }, { i8, i32 } addrspace(5)* %arg1 %arg1.load = load volatile { i8, i32 }, { i8, i32 } addrspace(5)* %arg1
store volatile { i8, i32 } %arg0.load, { i8, i32 } addrspace(1)* undef store volatile { i8, i32 } %arg0.load, { i8, i32 } addrspace(1)* undef
store volatile { i8, i32 } %arg1.load, { i8, i32 } addrspace(1)* undef store volatile { i8, i32 } %arg1.load, { i8, i32 } addrspace(1)* undef
store volatile i32 %arg2, i32 addrspace(3)* undef store volatile i32 %arg2, i32 addrspace(3)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}void_func_byval_i32_byval_i64: ; GCN-LABEL: {{^}}void_func_byval_i32_byval_i64:
; GCN-DAG: buffer_load_dword v[[ARG0_LOAD:[0-9]+]], off, s[0:3], s32{{$}} ; GCN: s_mov_b32 s34, s32
; GCN-DAG: buffer_load_dword v[[ARG1_LOAD0:[0-9]+]], off, s[0:3], s32 offset:8{{$}} ; GCN-DAG: buffer_load_dword v[[ARG0_LOAD:[0-9]+]], off, s[0:3], s34{{$}}
; GCN-DAG: buffer_load_dword v[[ARG1_LOAD1:[0-9]+]], off, s[0:3], s32 offset:12{{$}} ; GCN-DAG: buffer_load_dword v[[ARG1_LOAD0:[0-9]+]], off, s[0:3], s34 offset:8{{$}}
; GCN-DAG: buffer_load_dword v[[ARG1_LOAD1:[0-9]+]], off, s[0:3], s34 offset:12{{$}}
; GCN-DAG: buffer_store_dword v[[ARG0_LOAD]], off ; GCN-DAG: buffer_store_dword v[[ARG0_LOAD]], off
; GCN-DAG: buffer_store_dwordx2 v{{\[}}[[ARG1_LOAD0]]:[[ARG1_LOAD1]]{{\]}}, off ; GCN-DAG: buffer_store_dwordx2 v{{\[}}[[ARG1_LOAD0]]:[[ARG1_LOAD1]]{{\]}}, off
define void @void_func_byval_i32_byval_i64(i32 addrspace(5)* byval %arg0, i64 addrspace(5)* byval %arg1) #0 { define void @void_func_byval_i32_byval_i64(i32 addrspace(5)* byval %arg0, i64 addrspace(5)* byval %arg1) #0 {
%arg0.load = load i32, i32 addrspace(5)* %arg0 %arg0.load = load i32, i32 addrspace(5)* %arg0
%arg1.load = load i64, i64 addrspace(5)* %arg1 %arg1.load = load i64, i64 addrspace(5)* %arg1
store i32 %arg0.load, i32 addrspace(1)* undef store i32 %arg0.load, i32 addrspace(1)* undef
store i64 %arg1.load, i64 addrspace(1)* undef store i64 %arg1.load, i64 addrspace(1)* undef
ret void ret void
▲ Show 20 Lines • Show All 246 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/nested-calls.ll

Show All 10 Lines
; GCN: s_waitcnt ; GCN: s_waitcnt
; Spill CSR VGPR used for SGPR spilling ; Spill CSR VGPR used for SGPR spilling
; GCN: s_or_saveexec_b64 [[COPY_EXEC0:s\[[0-9]+:[0-9]+\]]], -1{{$}} ; GCN: s_or_saveexec_b64 [[COPY_EXEC0:s\[[0-9]+:[0-9]+\]]], -1{{$}}
; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill
; GCN-NEXT: s_mov_b64 exec, [[COPY_EXEC0]] ; GCN-NEXT: s_mov_b64 exec, [[COPY_EXEC0]]
; GCN-DAG: v_writelane_b32 v40, s33, 2 ; GCN-DAG: v_writelane_b32 v40, s33, 2
; GCN-DAG: s_mov_b32 s33, s32 ; GCN-DAG: s_mov_b32 s33, s32
; GCN-DAG: s_add_u32 s32, s32, 0x400 ; GCN-DAG: s_add_u32 s32, s32, 0x200
; GCN-DAG: v_writelane_b32 v40, s30, 0 ; GCN-DAG: v_writelane_b32 v40, s30, 0
; GCN-DAG: v_writelane_b32 v40, s31, 1 ; GCN-DAG: v_writelane_b32 v40, s31, 1
; GCN: s_swappc_b64 ; GCN: s_swappc_b64
; GCN: v_readlane_b32 s4, v40, 0 ; GCN: v_readlane_b32 s4, v40, 0
; GCN: v_readlane_b32 s5, v40, 1 ; GCN: v_readlane_b32 s5, v40, 1
; GCN-NEXT: s_sub_u32 s32, s32, 0x400 ; GCN-NEXT: s_sub_u32 s32, s32, 0x200
; GCN-NEXT: v_readlane_b32 s33, v40, 2 ; GCN-NEXT: v_readlane_b32 s33, v40, 2
; GCN: s_or_saveexec_b64 [[COPY_EXEC1:s\[[0-9]+:[0-9]+\]]], -1{{$}} ; GCN: s_or_saveexec_b64 [[COPY_EXEC1:s\[[0-9]+:[0-9]+\]]], -1{{$}}
; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s32 ; 4-byte Folded Reload ; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s32 ; 4-byte Folded Reload
; GCN-NEXT: s_mov_b64 exec, [[COPY_EXEC1]] ; GCN-NEXT: s_mov_b64 exec, [[COPY_EXEC1]]
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: s_setpc_b64 s[4:5] ; GCN-NEXT: s_setpc_b64 s[4:5]
define void @test_func_call_external_void_func_i32_imm() #0 { define void @test_func_call_external_void_func_i32_imm() #0 {
call void @external_void_func_i32(i32 42) call void @external_void_func_i32(i32 42)
ret void ret void
} }
; GCN-LABEL: {{^}}test_func_call_external_void_func_i32_imm_stack_use: ; GCN-LABEL: {{^}}test_func_call_external_void_func_i32_imm_stack_use:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GCN: s_mov_b32 s33, s32 ; GCN: s_mov_b32 s33, s32
; GCN-DAG: s_add_u32 s32, s32, 0x1400{{$}} ; GCN-DAG: s_add_u32 s32, s32, 0x1200{{$}}
; GCN-DAG: buffer_store_dword v{{[0-9]+}}, off, s[0:3], s33 offset: ; GCN-DAG: buffer_store_dword v{{[0-9]+}}, off, s[0:3], s33 offset:
; GCN: s_swappc_b64 ; GCN: s_swappc_b64
; GCN: s_sub_u32 s32, s32, 0x1400{{$}} ; GCN: s_sub_u32 s32, s32, 0x1200{{$}}
; GCN: s_setpc_b64 ; GCN: s_setpc_b64
define void @test_func_call_external_void_func_i32_imm_stack_use() #0 { define void @test_func_call_external_void_func_i32_imm_stack_use() #0 {
%alloca = alloca [16 x i32], align 4, addrspace(5) %alloca = alloca [16 x i32], align 4, addrspace(5)
%gep0 = getelementptr inbounds [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 0 %gep0 = getelementptr inbounds [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 0
%gep15 = getelementptr inbounds [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 16 %gep15 = getelementptr inbounds [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 16
store volatile i32 0, i32 addrspace(5)* %gep0 store volatile i32 0, i32 addrspace(5)* %gep0
store volatile i32 0, i32 addrspace(5)* %gep15 store volatile i32 0, i32 addrspace(5)* %gep15
call void @external_void_func_i32(i32 42) call void @external_void_func_i32(i32 42)
ret void ret void
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }
attributes #1 = { nounwind readnone } attributes #1 = { nounwind readnone }
attributes #2 = { nounwind noinline } attributes #2 = { nounwind noinline }

llvm/test/CodeGen/AMDGPU/promote-alloca-calling-conv.ll

Show First 20 Lines • Show All 74 Lines • ▼ Show 20 Lines
} }
declare i32 @foo(i32 addrspace(5)*) #0 declare i32 @foo(i32 addrspace(5)*) #0
; ASM-LABEL: {{^}}call_private: ; ASM-LABEL: {{^}}call_private:
; ASM: buffer_store_dword ; ASM: buffer_store_dword
; ASM: buffer_store_dword ; ASM: buffer_store_dword
; ASM: s_swappc_b64 ; ASM: s_swappc_b64
; ASM: ScratchSize: 16400 ; ASM: ScratchSize: 16396
define amdgpu_kernel void @call_private(i32 addrspace(1)* %out, i32 %in) #0 { define amdgpu_kernel void @call_private(i32 addrspace(1)* %out, i32 %in) #0 {
entry: entry:
%tmp = alloca [2 x i32], addrspace(5) %tmp = alloca [2 x i32], addrspace(5)
%tmp1 = getelementptr [2 x i32], [2 x i32] addrspace(5)* %tmp, i32 0, i32 0 %tmp1 = getelementptr [2 x i32], [2 x i32] addrspace(5)* %tmp, i32 0, i32 0
%tmp2 = getelementptr [2 x i32], [2 x i32] addrspace(5)* %tmp, i32 0, i32 1 %tmp2 = getelementptr [2 x i32], [2 x i32] addrspace(5)* %tmp, i32 0, i32 1
store i32 0, i32 addrspace(5)* %tmp1 store i32 0, i32 addrspace(5)* %tmp1
store i32 1, i32 addrspace(5)* %tmp2 store i32 1, i32 addrspace(5)* %tmp2
%tmp3 = getelementptr [2 x i32], [2 x i32] addrspace(5)* %tmp, i32 0, i32 %in %tmp3 = getelementptr [2 x i32], [2 x i32] addrspace(5)* %tmp, i32 0, i32 %in
Show All 9 Lines

llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll

Show All 33 Lines; mark most VGPR registers as used to increase register pressure
ret void ret void
} }
; CHECK-LABEL: test_limited_sgpr ; CHECK-LABEL: test_limited_sgpr
; GFX6: s_add_u32 s32, s32, 0x[[OFFSET:[0-9]+]] ; GFX6: s_add_u32 s32, s32, 0x[[OFFSET:[0-9]+]]
; GFX6-NEXT: buffer_load_dword v{{[0-9]+}}, off, s[{{[0-9:]+}}], s32 ; GFX6-NEXT: buffer_load_dword v{{[0-9]+}}, off, s[{{[0-9:]+}}], s32
; GFX6-NEXT: s_sub_u32 s32, s32, 0x[[OFFSET:[0-9]+]] ; GFX6-NEXT: s_sub_u32 s32, s32, 0x[[OFFSET:[0-9]+]]
; GFX6: NumSgprs: 48 ; GFX6: NumSgprs: 48
; GFX6: ScratchSize: 8624 ; GFX6: ScratchSize: 8608
define amdgpu_kernel void @test_limited_sgpr(<64 x i32> addrspace(1)* %out, <64 x i32> addrspace(1)* %in) #0 { define amdgpu_kernel void @test_limited_sgpr(<64 x i32> addrspace(1)* %out, <64 x i32> addrspace(1)* %in) #0 {
entry: entry:
%lo = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) %lo = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0)
%tid = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %lo) %tid = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %lo)
; allocate enough scratch to go beyond 2^12 addressing ; allocate enough scratch to go beyond 2^12 addressing
%scratch = alloca <1280 x i32>, align 8, addrspace(5) %scratch = alloca <1280 x i32>, align 8, addrspace(5)
▲ Show 20 Lines • Show All 48 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/stack-realign.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,HSA %s
; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,PAL %s
; Check that we properly realign the stack. While 4-byte access is all ; Check that we properly realign the stack. While 4-byte access is all
; that is ever needed, some transformations rely on the known bits from the alignment of the pointer (e.g. ; that is ever needed, some transformations rely on the known bits from the alignment of the pointer (e.g.
; 128 byte object ; 128 byte object
; 4 byte emergency stack slot ; 4 byte emergency stack slot
; = 144 bytes with padding between them ; = 144 bytes with padding between them
; GCN-LABEL: {{^}}needs_align16_default_stack_align: ; GCN-LABEL: {{^}}needs_align16_default_stack_align:
; PAL: s_and_b32 s33, s{{[0-9]+}}, 0xfffffc00
; GCN-DAG: v_lshlrev_b32_e32 [[SCALED_IDX:v[0-9]+]], 4, v0 ; GCN-DAG: v_lshlrev_b32_e32 [[SCALED_IDX:v[0-9]+]], 4, v0
; GCN-DAG: v_lshrrev_b32_e64 [[FRAMEDIFF:v[0-9]+]], 6, s32 ; PAL-DAG: v_lshrrev_b32_e64 [[FRAMEDIFF:v[0-9]+]], 6, s33
; HSA-DAG: v_lshrrev_b32_e64 [[FRAMEDIFF:v[0-9]+]], 6, s32
; GCN: v_add_u32_e32 [[FI:v[0-9]+]], vcc, [[FRAMEDIFF]], [[SCALED_IDX]] ; GCN: v_add_u32_e32 [[FI:v[0-9]+]], vcc, [[FRAMEDIFF]], [[SCALED_IDX]]
; GCN-NOT: s32 ; GCN-NOT: s32
; GCN: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[0:3], 0 offen ; GCN: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[0:3], 0 offen
; GCN: v_or_b32_e32 v{{[0-9]+}}, 12 ; GCN: v_or_b32_e32 v{{[0-9]+}}, 12
; GCN: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[0:3], 0 offen ; GCN: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[0:3], 0 offen
; GCN: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[0:3], 0 offen ; GCN: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[0:3], 0 offen
; GCN: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[0:3], 0 offen ; GCN: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[0:3], 0 offen
; GCN-NOT: s32 ; HSA-NOT: s32
; GCN: ; ScratchSize: 144 ; HSA: ; ScratchSize: 144
; PAl: ; ScratchSize: 160
define void @needs_align16_default_stack_align(i32 %idx) #0 { define void @needs_align16_default_stack_align(i32 %idx) #0 {
%alloca.align16 = alloca [8 x <4 x i32>], align 16, addrspace(5) %alloca.align16 = alloca [8 x <4 x i32>], align 16, addrspace(5)
%gep0 = getelementptr inbounds [8 x <4 x i32>], [8 x <4 x i32>] addrspace(5)* %alloca.align16, i32 0, i32 %idx %gep0 = getelementptr inbounds [8 x <4 x i32>], [8 x <4 x i32>] addrspace(5)* %alloca.align16, i32 0, i32 %idx
store volatile <4 x i32> <i32 1, i32 2, i32 3, i32 4>, <4 x i32> addrspace(5)* %gep0, align 16 store volatile <4 x i32> <i32 1, i32 2, i32 3, i32 4>, <4 x i32> addrspace(5)* %gep0, align 16
ret void ret void
} }
; GCN-LABEL: {{^}}needs_align16_stack_align4: ; GCN-LABEL: {{^}}needs_align16_stack_align4:
Show All 36 Linesdefine void @needs_align32(i32 %idx) #0 {
%gep0 = getelementptr inbounds [8 x <4 x i32>], [8 x <4 x i32>] addrspace(5)* %alloca.align16, i32 0, i32 %idx %gep0 = getelementptr inbounds [8 x <4 x i32>], [8 x <4 x i32>] addrspace(5)* %alloca.align16, i32 0, i32 %idx
store volatile <4 x i32> <i32 1, i32 2, i32 3, i32 4>, <4 x i32> addrspace(5)* %gep0, align 32 store volatile <4 x i32> <i32 1, i32 2, i32 3, i32 4>, <4 x i32> addrspace(5)* %gep0, align 32
ret void ret void
} }
; GCN-LABEL: {{^}}force_realign4: ; GCN-LABEL: {{^}}force_realign4:
; GCN: s_add_u32 [[SCRATCH_REG:s[0-9]+]], s32, 0xc0{{$}} ; GCN: s_add_u32 [[SCRATCH_REG:s[0-9]+]], s32, 0xc0{{$}}
; GCN: s_and_b32 s33, [[SCRATCH_REG]], 0xffffff00 ; GCN: s_and_b32 s33, [[SCRATCH_REG]], 0xffffff00
; GCN: s_add_u32 s32, s32, 0xd00{{$}} ; HSA: s_add_u32 s32, s32, 0xd00{{$}}
; PAL: s_add_u32 s32, s32, 0xa00{{$}}
; GCN: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[0:3], 0 offen ; GCN: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[0:3], 0 offen
; GCN: s_sub_u32 s32, s32, 0xd00 ; HSA: s_sub_u32 s32, s32, 0xd00
; PAL: s_sub_u32 s32, s32, 0xa00
; GCN: ; ScratchSize: 52 ; HSA: ; ScratchSize: 52
; PAL: ; ScratchSize: 40
define void @force_realign4(i32 %idx) #1 { define void @force_realign4(i32 %idx) #1 {
%alloca.align16 = alloca [8 x i32], align 4, addrspace(5) %alloca.align16 = alloca [8 x i32], align 4, addrspace(5)
%gep0 = getelementptr inbounds [8 x i32], [8 x i32] addrspace(5)* %alloca.align16, i32 0, i32 %idx %gep0 = getelementptr inbounds [8 x i32], [8 x i32] addrspace(5)* %alloca.align16, i32 0, i32 %idx
store volatile i32 3, i32 addrspace(5)* %gep0, align 4 store volatile i32 3, i32 addrspace(5)* %gep0, align 4
ret void ret void
} }
; GCN-LABEL: {{^}}kernel_call_align16_from_8: ; GCN-LABEL: {{^}}kernel_call_align16_from_8:
; GCN: s_movk_i32 s32, 0x400{{$}} ; HSA: s_movk_i32 s32, 0x400{{$}}
; PAL: s_movk_i32 s32, 0x200{{$}}
; GCN-NOT: s32 ; GCN-NOT: s32
; GCN: s_swappc_b64 ; GCN: s_swappc_b64
define amdgpu_kernel void @kernel_call_align16_from_8() #0 { define amdgpu_kernel void @kernel_call_align16_from_8() #0 {
%alloca = alloca i32, align 4, addrspace(5) %alloca = alloca i32, align 4, addrspace(5)
store volatile i32 2, i32 addrspace(5)* %alloca store volatile i32 2, i32 addrspace(5)* %alloca
call void @needs_align16_default_stack_align(i32 1) call void @needs_align16_default_stack_align(i32 1)
ret void ret void
} }
; The call sequence should keep the stack on call aligned to 4 ; The call sequence should keep the stack on call aligned to 4
; GCN-LABEL: {{^}}kernel_call_align16_from_5: ; GCN-LABEL: {{^}}kernel_call_align16_from_5:
; GCN: s_movk_i32 s32, 0x400 ; HSA: s_movk_i32 s32, 0x400
; PAL: s_movk_i32 s32, 0x200
; GCN: s_swappc_b64 ; GCN: s_swappc_b64
define amdgpu_kernel void @kernel_call_align16_from_5() { define amdgpu_kernel void @kernel_call_align16_from_5() {
%alloca0 = alloca i8, align 1, addrspace(5) %alloca0 = alloca i8, align 1, addrspace(5)
store volatile i8 2, i8 addrspace(5)* %alloca0 store volatile i8 2, i8 addrspace(5)* %alloca0
call void @needs_align16_default_stack_align(i32 1) call void @needs_align16_default_stack_align(i32 1)
ret void ret void
} }
; GCN-LABEL: {{^}}kernel_call_align4_from_5: ; GCN-LABEL: {{^}}kernel_call_align4_from_5:
; GCN: s_movk_i32 s32, 0x400 ; HSA: s_movk_i32 s32, 0x400
; PAL: s_movk_i32 s32, 0x200
; GCN: s_swappc_b64 ; GCN: s_swappc_b64
define amdgpu_kernel void @kernel_call_align4_from_5() { define amdgpu_kernel void @kernel_call_align4_from_5() {
%alloca0 = alloca i8, align 1, addrspace(5) %alloca0 = alloca i8, align 1, addrspace(5)
store volatile i8 2, i8 addrspace(5)* %alloca0 store volatile i8 2, i8 addrspace(5)* %alloca0
call void @needs_align16_stack_align4(i32 1) call void @needs_align16_stack_align4(i32 1)
ret void ret void
} }
▲ Show 20 Lines • Show All 205 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/wave32.ll

Show First 20 Lines • Show All 1,059 Lines • ▼ Show 20 Lines
; GFX1032-NEXT: s_or_saveexec_b32 [[COPY_EXEC0:s[0-9]]], -1{{$}} ; GFX1032-NEXT: s_or_saveexec_b32 [[COPY_EXEC0:s[0-9]]], -1{{$}}
; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill ; GCN-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill
; GCN-NEXT: s_waitcnt_depctr 0xffe3 ; GCN-NEXT: s_waitcnt_depctr 0xffe3
; GFX1064-NEXT: s_mov_b64 exec, [[COPY_EXEC0]] ; GFX1064-NEXT: s_mov_b64 exec, [[COPY_EXEC0]]
; GFX1032-NEXT: s_mov_b32 exec_lo, [[COPY_EXEC0]] ; GFX1032-NEXT: s_mov_b32 exec_lo, [[COPY_EXEC0]]
; GCN-NEXT: v_writelane_b32 v40, s33, 2 ; GCN-NEXT: v_writelane_b32 v40, s33, 2
; GCN: s_mov_b32 s33, s32 ; GCN: s_mov_b32 s33, s32
; GFX1064: s_add_u32 s32, s32, 0x400 ; GFX1064: s_add_u32 s32, s32, 0x200
; GFX1032: s_add_u32 s32, s32, 0x200 ; GFX1032: s_add_u32 s32, s32, 0x100
; GCN-DAG: v_writelane_b32 v40, s30, 0 ; GCN-DAG: v_writelane_b32 v40, s30, 0
; GCN-DAG: v_writelane_b32 v40, s31, 1 ; GCN-DAG: v_writelane_b32 v40, s31, 1
; GCN: s_swappc_b64 ; GCN: s_swappc_b64
; GCN-DAG: v_readlane_b32 s4, v40, 0 ; GCN-DAG: v_readlane_b32 s4, v40, 0
; GCN-DAG: v_readlane_b32 s5, v40, 1 ; GCN-DAG: v_readlane_b32 s5, v40, 1
; GFX1064: s_sub_u32 s32, s32, 0x400 ; GFX1064: s_sub_u32 s32, s32, 0x200
; GFX1032: s_sub_u32 s32, s32, 0x200 ; GFX1032: s_sub_u32 s32, s32, 0x100
; GCN: v_readlane_b32 s33, v40, 2 ; GCN: v_readlane_b32 s33, v40, 2
; GFX1064: s_or_saveexec_b64 [[COPY_EXEC1:s\[[0-9]+:[0-9]+\]]], -1{{$}} ; GFX1064: s_or_saveexec_b64 [[COPY_EXEC1:s\[[0-9]+:[0-9]+\]]], -1{{$}}
; GFX1032: s_or_saveexec_b32 [[COPY_EXEC1:s[0-9]]], -1{{$}} ; GFX1032: s_or_saveexec_b32 [[COPY_EXEC1:s[0-9]]], -1{{$}}
; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s32 ; 4-byte Folded Reload ; GCN-NEXT: buffer_load_dword v40, off, s[0:3], s32 ; 4-byte Folded Reload
; GCN-NEXT: s_waitcnt_depctr 0xffe3 ; GCN-NEXT: s_waitcnt_depctr 0xffe3
; GFX1064-NEXT: s_mov_b64 exec, [[COPY_EXEC1]] ; GFX1064-NEXT: s_mov_b64 exec, [[COPY_EXEC1]]
; GFX1032-NEXT: s_mov_b32 exec_lo, [[COPY_EXEC1]] ; GFX1032-NEXT: s_mov_b32 exec_lo, [[COPY_EXEC1]]
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
Show All 40 Lines