[Sparc] Remove cast that truncates immediate operands to 32 bits.

[brad]

Summary

Remove cast that truncates immediate operands to 32 bits.

[jrtc27]

Needs a test case; something like:

diff --git a/llvm/test/CodeGen/SPARC/inlineasm-v9.ll b/llvm/test/CodeGen/SPARC/inlineasm-v9.ll
index 53ab114dd8d5..1388c8655ace 100644
--- a/llvm/test/CodeGen/SPARC/inlineasm-v9.ll
+++ b/llvm/test/CodeGen/SPARC/inlineasm-v9.ll
@@ -39,3 +39,12 @@ entry:
   tail call void asm sideeffect "faddq $0,$1,$2", "{f40},{f40},{f40}"(fp128 0xL0, fp128 0xL0, fp128 0xL0)
   ret void
 }
+
+;; Ensure that 64-bit immediates aren't truncated
+; CHECK-LABEL: test_large_immediate
+; CHECK: or %o0, %lo(4294967296), %o0
+define i64 @test_large_immediate(i64) {
+entry:
+  %1 = tail call i64 asm "or $0, %lo($1), $0", "=r,i,r"(i64 4294967296, i64 %0)
+  ret i64 %1
+}

as I believe this only affects emitting inline assembly operands (normal and memory)? Round-tripping assembly through llvm-mc isn't enough to hit this path.

[brad]

Added provided test.

[brad]

Is this Ok or is any further testing necessary?

[brad]

Venkatraman?

[brad]

@jrtc27 ??

llvm/lib/Target/Sparc/SparcAsmPrinter.cpp

   bool CloseParen = SparcMCExpr::printVariantKind(O, TF);
 
   switch (MO.getType()) {
   case MachineOperand::MO_Register:
     O << "%" << StringRef(getRegisterName(MO.getReg())).lower();
     break;
 
   case MachineOperand::MO_Immediate:
-    O << (int)MO.getImm();
+    O << MO.getImm();
     break;
   case MachineOperand::MO_MachineBasicBlock:
     MO.getMBB()->getSymbol()->print(O, MAI);
     return;
   case MachineOperand::MO_GlobalAddress:
     PrintSymbolOperand(MO, O);
     break;
   case MachineOperand::MO_BlockAddress: