AMDGPU: Convert test to MIR

[arsenm]

Summary

Currently the dbg_value ends up in the relaxed branch block. A future
commit will push the dbg_value out of this block, and I'm not sure how
to coax the IR into producing the same MIR at the relevant point.

[arsenm]

4a9a4885aef9529788cc32999f998254a3730179

llvm/test/CodeGen/AMDGPU/branch-relaxation-debug-info.ll

-; RUN: llc -O0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -amdgpu-s-branch-bits=4 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
-
-; Make sure there is no assertion due to dbg_value instructions
-; present in the block used for the branch expansion.
-
-declare void @llvm.dbg.value(metadata, metadata, metadata) #0
-
-define amdgpu_kernel void @long_branch_dbg_value(float addrspace(1)* nocapture %arg, float %arg1) #1 !dbg !5 {
-; GCN-LABEL: long_branch_dbg_value:
-; GCN:  BB0_5: ; %bb
-; GCN-NEXT:    ;DEBUG_VALUE: test_debug_value:globalptr_arg <- [DW_OP_plus_uconst 12, DW_OP_stack_value]
-; GCN-NEXT:    .loc 1 0 42 is_stmt 0 ; /tmp/test_debug_value.cl:0:42
-; GCN-NEXT:    s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
-; GCN-NEXT:    s_add_u32 s[[PC_LO]], s[[PC_LO]], BB0_4-(BB0_5+4)
-; GCN-NEXT:    s_addc_u32 s[[PC_HI]], s[[PC_HI]], 0
-; GCN-NEXT:    s_setpc_b64
-bb:
-  %tmp = fmul float %arg1, %arg1
-  %tmp2 = getelementptr inbounds float, float addrspace(1)* %arg, i64 3
-  call void @llvm.dbg.value(metadata float addrspace(1)* %tmp2, metadata !11, metadata !DIExpression()) #2, !dbg !12
-  store float %tmp, float addrspace(1)* %tmp2, align 4, !dbg !12
-  %tmp3 = fcmp olt float %tmp, 0x3810000000000000
-  br i1 %tmp3, label %bb8, label %bb4
-
-bb4:                                              ; preds = %bb
-  %tmp5 = load volatile float, float addrspace(1)* undef
-  %tmp6 = fcmp oeq float %tmp5, 0x7FF0000000000000
-  br i1 %tmp6, label %bb7, label %bb8
-
-bb7:                                              ; preds = %bb4
-  br label %bb8
-
-bb8:                                              ; preds = %bb7, %bb4, %bb
-  ret void
-}
-
-attributes #0 = { nounwind readnone speculatable }
-attributes #1 = { nounwind writeonly }
-attributes #2 = { nounwind }
-
-!llvm.dbg.cu = !{!0}
-!llvm.module.flags = !{!3, !4}
-
-!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.8.0 (trunk 244715) (llvm/trunk 244718)", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2)
-!1 = !DIFile(filename: "/tmp/test_debug_value.cl", directory: "/Users/matt/src/llvm/build_debug")
-!2 = !{}
-!3 = !{i32 2, !"Dwarf Version", i32 4}
-!4 = !{i32 2, !"Debug Info Version", i32 3}
-!5 = distinct !DISubprogram(name: "test_debug_value", scope: !1, file: !1, line: 1, type: !6, scopeLine: 2, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !10)
-!6 = !DISubroutineType(types: !7)
-!7 = !{null, !8}
-!8 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !9, size: 64, align: 32)
-!9 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
-!10 = !{!11}
-!11 = !DILocalVariable(name: "globalptr_arg", arg: 1, scope: !5, file: !1, line: 1, type: !8)
-!12 = !DILocation(line: 1, column: 42, scope: !5)

llvm/test/CodeGen/AMDGPU/branch-relaxation-debug-info.mir

+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -start-before=branch-relaxation -amdgpu-s-branch-bits=4 -o - %s | FileCheck -check-prefix=GCN %s
+
+# Make sure there's no assert if the DBG_VALUE ends up in the same
+# block as the branch expansion.
+
+# GCN-LABEL: long_branch_dbg_value:
+# GCN:  BB0_5: ; %bb
+# GCN-NEXT:    ;DEBUG_VALUE: test_debug_value:globalptr_arg <- [DW_OP_plus_uconst 12, DW_OP_stack_value]
+# GCN-NEXT:    .loc 1 0 42 is_stmt 0 ; /tmp/test_debug_value.cl:0:42
+# GCN-NEXT:    s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
+# GCN-NEXT:    s_add_u32 s[[PC_LO]], s[[PC_LO]], BB0_4-(BB0_5+4)
+# GCN-NEXT:    s_addc_u32 s[[PC_HI]], s[[PC_HI]], 0
+# GCN-NEXT:    s_setpc_b64
+
+--- |
+
+  define amdgpu_kernel void @long_branch_dbg_value(float addrspace(1)* nocapture %arg, float %arg1) #1 !dbg !5 {
+  bb:
+    %long_branch_dbg_value.kernarg.segment = call nonnull align 16 dereferenceable(12) i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr()
+    %arg.kernarg.offset = getelementptr inbounds i8, i8 addrspace(4)* %long_branch_dbg_value.kernarg.segment, i64 0
+    %arg.kernarg.offset.cast = bitcast i8 addrspace(4)* %arg.kernarg.offset to float addrspace(1)* addrspace(4)*, !amdgpu.uniform !2, !amdgpu.noclobber !2
+    %arg.load = load float addrspace(1)*, float addrspace(1)* addrspace(4)* %arg.kernarg.offset.cast, align 16, !invariant.load !2
+    %arg1.kernarg.offset = getelementptr inbounds i8, i8 addrspace(4)* %long_branch_dbg_value.kernarg.segment, i64 8
+    %arg1.kernarg.offset.cast = bitcast i8 addrspace(4)* %arg1.kernarg.offset to float addrspace(4)*, !amdgpu.uniform !2, !amdgpu.noclobber !2
+    %arg1.load = load float, float addrspace(4)* %arg1.kernarg.offset.cast, align 8, !invariant.load !2
+    %tmp = fmul float %arg1.load, %arg1.load
+    %tmp2 = getelementptr inbounds float, float addrspace(1)* %arg.load, i64 3
+    call void @llvm.dbg.value(metadata float addrspace(1)* %tmp2, metadata !11, metadata !DIExpression()) #5, !dbg !12
+    store float %tmp, float addrspace(1)* %tmp2, align 4, !dbg !12
+    %tmp3 = fcmp olt float %tmp, 0x3810000000000000
+    %tmp3.inv = xor i1 %tmp3, true
+    br i1 %tmp3.inv, label %bb4, label %bb8, !amdgpu.uniform !2
+
+  bb4:                                              ; preds = %bb
+    %tmp5 = load volatile float, float addrspace(1)* undef, align 4
+    %tmp6 = fcmp oeq float %tmp5, 0x7FF0000000000000
+    br i1 %tmp6, label %bb7, label %Flow, !amdgpu.uniform !2
+
+  bb7:                                              ; preds = %bb4
+    br label %Flow, !amdgpu.uniform !2
+
+  Flow:                                             ; preds = %bb7, %bb4
+    br label %bb8, !amdgpu.uniform !2
+
+  bb8:                                              ; preds = %bb, %Flow
+    ret void
+  }
+
+  declare align 4 i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() #2
+  declare void @llvm.dbg.value(metadata, metadata, metadata) #0
+
+  attributes #0 = { nounwind readnone speculatable willreturn }
+  attributes #1 = { nounwind writeonly }
+  attributes #2 = { nounwind readnone speculatable willreturn }
+  attributes #3 = { convergent nounwind willreturn }
+  attributes #4 = { convergent nounwind readnone willreturn }
+  attributes #5 = { nounwind }
+
+  !llvm.dbg.cu = !{!0}
+  !llvm.module.flags = !{!3, !4}
+
+  !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.8.0 (trunk 244715) (llvm/trunk 244718)", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2)
+  !1 = !DIFile(filename: "/tmp/test_debug_value.cl", directory: "/Users/matt/src/llvm/build_debug")
+  !2 = !{}
+  !3 = !{i32 2, !"Dwarf Version", i32 4}
+  !4 = !{i32 2, !"Debug Info Version", i32 3}
+  !5 = distinct !DISubprogram(name: "test_debug_value", scope: !1, file: !1, line: 1, type: !6, scopeLine: 2, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !10)
+  !6 = !DISubroutineType(types: !7)
+  !7 = !{null, !8}
+  !8 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !9, size: 64, align: 32)
+  !9 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+  !10 = !{!11}
+  !11 = !DILocalVariable(name: "globalptr_arg", arg: 1, scope: !5, file: !1, line: 1, type: !8)
+  !12 = !DILocation(line: 1, column: 42, scope: !5)
+
+...
+---
+name:            long_branch_dbg_value
+tracksRegLiveness: true
+registers:       []
+body:             |
+  bb.0.bb:
+    successors: %bb.1(0x40000000), %bb.4(0x40000000)
+    liveins: $sgpr4_sgpr5
+
+    renamable $sgpr6_sgpr7 = S_LOAD_DWORDX2_IMM renamable $sgpr4_sgpr5, 0, 0, 0 :: (dereferenceable invariant load 8 from %ir.arg.kernarg.offset.cast, align 16, addrspace 4)
+    renamable $sgpr4 = S_LOAD_DWORD_IMM killed renamable $sgpr4_sgpr5, 8, 0, 0 :: (dereferenceable invariant load 4 from %ir.arg1.kernarg.offset.cast, align 8, addrspace 4)
+    S_WAITCNT 49279
+    renamable $vgpr0 = nofpexcept V_MUL_F32_e64 0, killed $sgpr4, 0, $sgpr4, 0, 0, implicit $mode, implicit $exec
+    DBG_VALUE renamable $sgpr6_sgpr7, $noreg, !11, !DIExpression(DW_OP_plus_uconst, 12, DW_OP_stack_value), debug-location !12
+    $vgpr1 = V_MOV_B32_e32 $sgpr6, implicit $exec, implicit-def $vgpr1_vgpr2, implicit $sgpr6_sgpr7
+    $vgpr2 = V_MOV_B32_e32 $sgpr7, implicit $exec, implicit killed $sgpr6_sgpr7, implicit $exec
+    GLOBAL_STORE_DWORD killed renamable $vgpr1_vgpr2, renamable $vgpr0, 12, 0, 0, 0, implicit $exec, debug-location !12 :: (store 4 into %ir.tmp2, addrspace 1)
+    renamable $sgpr4 = S_MOV_B32 8388608
+    renamable $sgpr4_sgpr5 = nofpexcept V_CMP_GT_F32_e64 0, killed $sgpr4, 0, killed $vgpr0, 0, implicit $mode, implicit $exec
+    renamable $vcc = S_AND_B64 $exec, killed renamable $sgpr4_sgpr5, implicit-def dead $scc
+    S_CBRANCH_VCCNZ %bb.4, implicit killed $vcc
+
+  bb.1.bb4:
+    successors: %bb.2(0x40000000), %bb.3(0x40000000)
+
+    renamable $sgpr4_sgpr5 = IMPLICIT_DEF
+    $vgpr0 = V_MOV_B32_e32 $sgpr4, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr4_sgpr5
+    $vgpr1 = V_MOV_B32_e32 $sgpr5, implicit $exec, implicit killed $sgpr4_sgpr5, implicit $exec
+    renamable $vgpr0 = GLOBAL_LOAD_DWORD killed renamable $vgpr0_vgpr1, 0, 0, 0, 0, implicit $exec :: (volatile load 4 from `float addrspace(1)* undef`, addrspace 1)
+    renamable $sgpr4 = S_MOV_B32 2139095040
+    S_WAITCNT 3952
+    renamable $sgpr4_sgpr5 = nofpexcept V_CMP_NEQ_F32_e64 0, killed $sgpr4, 0, killed $vgpr0, 0, implicit $mode, implicit $exec
+    renamable $vcc = S_AND_B64 $exec, killed renamable $sgpr4_sgpr5, implicit-def dead $scc
+    S_CBRANCH_VCCNZ %bb.3, implicit killed $vcc
+
+  bb.2.bb7:
+    successors: %bb.3(0x80000000)
+
+
+  bb.3.Flow:
+    successors: %bb.4(0x80000000)
+
+
+  bb.4.bb8:
+    S_ENDPGM 0
+
+...