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Differential D85895

[AMDGPU] Enable .rodata for amdpal os
ClosedPublic

Authored by Flakebi on Aug 13 2020, 5:28 AM.

Details

Reviewers
arsenm
nhaehnle
tpr
Commits
rG9aa0ff77bdc7: [AMDGPU] Enable .rodata for amdpal os
Summary

PAL recently got support for multiple ELF sections and relocations,
therefore we can now use .rodata sections instead of forcing constants
into .text.

Diff Detail

Event Timeline

Flakebi created this revision.Aug 13 2020, 5:28 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 13 2020, 5:28 AM
Herald added subscribers: llvm-commits, kerbowa, hiraditya and 5 others. · View Herald Transcript
Flakebi requested review of this revision.Aug 13 2020, 5:28 AM
Herald added a subscriber: wdng. · View Herald TranscriptAug 13 2020, 5:28 AM
arsenm accepted this revision.Aug 13 2020, 6:03 AM
This revision is now accepted and ready to land.Aug 13 2020, 6:03 AM
Harbormaster completed remote builds in B68245: Diff 285338.Aug 13 2020, 6:09 AM
Closed by commit rG9aa0ff77bdc7: [AMDGPU] Enable .rodata for amdpal os (authored by sebastian-ne). · Explain WhyAug 14 2020, 12:06 AM
This revision was automatically updated to reflect the committed changes.
sebastian-ne added a commit: rG9aa0ff77bdc7: [AMDGPU] Enable .rodata for amdpal os.

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
Utils/
2 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
248 lines
40 lines

Diff 285563

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

Show First 20 Lines • Show All 572 Lines • ▼ Show 20 Lines
bool isReadOnlySegment(const GlobalValue *GV) { bool isReadOnlySegment(const GlobalValue *GV) {
unsigned AS = GV->getAddressSpace(); unsigned AS = GV->getAddressSpace();
return AS == AMDGPUAS::CONSTANT_ADDRESS || return AS == AMDGPUAS::CONSTANT_ADDRESS ||
AS == AMDGPUAS::CONSTANT_ADDRESS_32BIT; AS == AMDGPUAS::CONSTANT_ADDRESS_32BIT;
} }
bool shouldEmitConstantsToTextSection(const Triple &TT) { bool shouldEmitConstantsToTextSection(const Triple &TT) {
return TT.getOS() == Triple::AMDPAL || TT.getArch() == Triple::r600; return TT.getArch() == Triple::r600;
} }
int getIntegerAttribute(const Function &F, StringRef Name, int Default) { int getIntegerAttribute(const Function &F, StringRef Name, int Default) {
Attribute A = F.getFnAttribute(Name); Attribute A = F.getFnAttribute(Name);
int Result = Default; int Result = Default;
if (A.isStringAttribute()) { if (A.isStringAttribute()) {
StringRef Str = A.getValueAsString(); StringRef Str = A.getValueAsString();
▲ Show 20 Lines • Show All 995 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/global-value.ll

; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -stop-after=legalizer < %s | FileCheck -check-prefix=HSA %s ; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -stop-after=legalizer < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=hawaii -stop-after=legalizer < %s | FileCheck -check-prefix=PAL %s ; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=hawaii -stop-after=legalizer < %s | FileCheck -check-prefix=GCN %s
@external_constant = external addrspace(4) constant i32, align 4 @external_constant = external addrspace(4) constant i32, align 4
@external_constant32 = external addrspace(6) constant i32, align 4 @external_constant32 = external addrspace(6) constant i32, align 4
@external_global = external addrspace(1) global i32, align 4 @external_global = external addrspace(1) global i32, align 4
@external_other = external addrspace(999) global i32, align 4 @external_other = external addrspace(999) global i32, align 4
@internal_constant = internal addrspace(4) constant i32 9, align 4 @internal_constant = internal addrspace(4) constant i32 9, align 4
@internal_constant32 = internal addrspace(6) constant i32 9, align 4 @internal_constant32 = internal addrspace(6) constant i32 9, align 4
@internal_global = internal addrspace(1) global i32 9, align 4 @internal_global = internal addrspace(1) global i32 9, align 4
@internal_other = internal addrspace(999) global i32 9, align 4 @internal_other = internal addrspace(999) global i32 9, align 4
define i32 addrspace(4)* @external_constant_got() { define i32 addrspace(4)* @external_constant_got() {
; HSA-LABEL: name: external_constant_got ; GCN-LABEL: name: external_constant_got
; HSA: bb.1 (%ir-block.0): ; GCN: bb.1 (%ir-block.0):
; HSA: liveins: $sgpr30_sgpr31 ; GCN: liveins: $sgpr30_sgpr31
; HSA: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 ; GCN: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; HSA: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p4) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @external_constant + 4, target-flags(amdgpu-gotprel32-hi) @external_constant + 4, implicit-def $scc ; GCN: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p4) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @external_constant + 4, target-flags(amdgpu-gotprel32-hi) @external_constant + 4, implicit-def $scc
; HSA: [[LOAD:%[0-9]+]]:_(p4) = G_LOAD [[SI_PC_ADD_REL_OFFSET]](p4) :: (dereferenceable invariant load 8 from got, addrspace 4) ; GCN: [[LOAD:%[0-9]+]]:_(p4) = G_LOAD [[SI_PC_ADD_REL_OFFSET]](p4) :: (dereferenceable invariant load 8 from got, addrspace 4)
; HSA: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](p4) ; GCN: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](p4)
; HSA: $vgpr0 = COPY [[UV]](s32) ; GCN: $vgpr0 = COPY [[UV]](s32)
; HSA: $vgpr1 = COPY [[UV1]](s32) ; GCN: $vgpr1 = COPY [[UV1]](s32)
; HSA: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]] ; GCN: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
; HSA: S_SETPC_B64_return [[COPY1]], implicit $vgpr0, implicit $vgpr1 ; GCN: S_SETPC_B64_return [[COPY1]], implicit $vgpr0, implicit $vgpr1
; PAL-LABEL: name: external_constant_got
; PAL: bb.1 (%ir-block.0):
; PAL: liveins: $sgpr30_sgpr31
; PAL: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; PAL: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p4) = SI_PC_ADD_REL_OFFSET @external_constant + 4, 0, implicit-def $scc
; PAL: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SI_PC_ADD_REL_OFFSET]](p4)
; PAL: $vgpr0 = COPY [[UV]](s32)
; PAL: $vgpr1 = COPY [[UV1]](s32)
; PAL: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
; PAL: S_SETPC_B64_return [[COPY1]], implicit $vgpr0, implicit $vgpr1
ret i32 addrspace(4)* @external_constant ret i32 addrspace(4)* @external_constant
} }
define i32 addrspace(1)* @external_global_got() { define i32 addrspace(1)* @external_global_got() {
; HSA-LABEL: name: external_global_got ; GCN-LABEL: name: external_global_got
; HSA: bb.1 (%ir-block.0): ; GCN: bb.1 (%ir-block.0):
; HSA: liveins: $sgpr30_sgpr31 ; GCN: liveins: $sgpr30_sgpr31
; HSA: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 ; GCN: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; HSA: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p4) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @external_global + 4, target-flags(amdgpu-gotprel32-hi) @external_global + 4, implicit-def $scc ; GCN: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p4) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @external_global + 4, target-flags(amdgpu-gotprel32-hi) @external_global + 4, implicit-def $scc
; HSA: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[SI_PC_ADD_REL_OFFSET]](p4) :: (dereferenceable invariant load 8 from got, addrspace 4) ; GCN: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[SI_PC_ADD_REL_OFFSET]](p4) :: (dereferenceable invariant load 8 from got, addrspace 4)
; HSA: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](p1) ; GCN: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](p1)
; HSA: $vgpr0 = COPY [[UV]](s32) ; GCN: $vgpr0 = COPY [[UV]](s32)
; HSA: $vgpr1 = COPY [[UV1]](s32) ; GCN: $vgpr1 = COPY [[UV1]](s32)
; HSA: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]] ; GCN: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
; HSA: S_SETPC_B64_return [[COPY1]], implicit $vgpr0, implicit $vgpr1 ; GCN: S_SETPC_B64_return [[COPY1]], implicit $vgpr0, implicit $vgpr1
; PAL-LABEL: name: external_global_got
; PAL: bb.1 (%ir-block.0):
; PAL: liveins: $sgpr30_sgpr31
; PAL: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; PAL: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p4) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @external_global + 4, target-flags(amdgpu-gotprel32-hi) @external_global + 4, implicit-def $scc
; PAL: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[SI_PC_ADD_REL_OFFSET]](p4) :: (dereferenceable invariant load 8 from got, addrspace 4)
; PAL: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](p1)
; PAL: $vgpr0 = COPY [[UV]](s32)
; PAL: $vgpr1 = COPY [[UV1]](s32)
; PAL: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
; PAL: S_SETPC_B64_return [[COPY1]], implicit $vgpr0, implicit $vgpr1
ret i32 addrspace(1)* @external_global ret i32 addrspace(1)* @external_global
} }
define i32 addrspace(999)* @external_other_got() { define i32 addrspace(999)* @external_other_got() {
; HSA-LABEL: name: external_other_got ; GCN-LABEL: name: external_other_got
; HSA: bb.1 (%ir-block.0): ; GCN: bb.1 (%ir-block.0):
; HSA: liveins: $sgpr30_sgpr31 ; GCN: liveins: $sgpr30_sgpr31
; HSA: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 ; GCN: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; HSA: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p4) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @external_other + 4, target-flags(amdgpu-gotprel32-hi) @external_other + 4, implicit-def $scc ; GCN: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p4) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @external_other + 4, target-flags(amdgpu-gotprel32-hi) @external_other + 4, implicit-def $scc
; HSA: [[LOAD:%[0-9]+]]:_(p999) = G_LOAD [[SI_PC_ADD_REL_OFFSET]](p4) :: (dereferenceable invariant load 8 from got, addrspace 4) ; GCN: [[LOAD:%[0-9]+]]:_(p999) = G_LOAD [[SI_PC_ADD_REL_OFFSET]](p4) :: (dereferenceable invariant load 8 from got, addrspace 4)
; HSA: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](p999) ; GCN: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](p999)
; HSA: $vgpr0 = COPY [[UV]](s32) ; GCN: $vgpr0 = COPY [[UV]](s32)
; HSA: $vgpr1 = COPY [[UV1]](s32) ; GCN: $vgpr1 = COPY [[UV1]](s32)
; HSA: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]] ; GCN: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
; HSA: S_SETPC_B64_return [[COPY1]], implicit $vgpr0, implicit $vgpr1 ; GCN: S_SETPC_B64_return [[COPY1]], implicit $vgpr0, implicit $vgpr1
; PAL-LABEL: name: external_other_got
; PAL: bb.1 (%ir-block.0):
; PAL: liveins: $sgpr30_sgpr31
; PAL: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; PAL: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p4) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @external_other + 4, target-flags(amdgpu-gotprel32-hi) @external_other + 4, implicit-def $scc
; PAL: [[LOAD:%[0-9]+]]:_(p999) = G_LOAD [[SI_PC_ADD_REL_OFFSET]](p4) :: (dereferenceable invariant load 8 from got, addrspace 4)
; PAL: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](p999)
; PAL: $vgpr0 = COPY [[UV]](s32)
; PAL: $vgpr1 = COPY [[UV1]](s32)
; PAL: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
; PAL: S_SETPC_B64_return [[COPY1]], implicit $vgpr0, implicit $vgpr1
ret i32 addrspace(999)* @external_other ret i32 addrspace(999)* @external_other
} }
define i32 addrspace(4)* @internal_constant_pcrel() { define i32 addrspace(4)* @internal_constant_pcrel() {
; HSA-LABEL: name: internal_constant_pcrel ; GCN-LABEL: name: internal_constant_pcrel
; HSA: bb.1 (%ir-block.0): ; GCN: bb.1 (%ir-block.0):
; HSA: liveins: $sgpr30_sgpr31 ; GCN: liveins: $sgpr30_sgpr31
; HSA: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 ; GCN: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; HSA: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p4) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @internal_constant + 4, target-flags(amdgpu-rel32-hi) @internal_constant + 4, implicit-def $scc ; GCN: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p4) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @internal_constant + 4, target-flags(amdgpu-rel32-hi) @internal_constant + 4, implicit-def $scc
; HSA: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SI_PC_ADD_REL_OFFSET]](p4) ; GCN: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SI_PC_ADD_REL_OFFSET]](p4)
; HSA: $vgpr0 = COPY [[UV]](s32) ; GCN: $vgpr0 = COPY [[UV]](s32)
; HSA: $vgpr1 = COPY [[UV1]](s32) ; GCN: $vgpr1 = COPY [[UV1]](s32)
; HSA: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]] ; GCN: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
; HSA: S_SETPC_B64_return [[COPY1]], implicit $vgpr0, implicit $vgpr1 ; GCN: S_SETPC_B64_return [[COPY1]], implicit $vgpr0, implicit $vgpr1
; PAL-LABEL: name: internal_constant_pcrel
; PAL: bb.1 (%ir-block.0):
; PAL: liveins: $sgpr30_sgpr31
; PAL: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; PAL: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p4) = SI_PC_ADD_REL_OFFSET @internal_constant + 4, 0, implicit-def $scc
; PAL: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SI_PC_ADD_REL_OFFSET]](p4)
; PAL: $vgpr0 = COPY [[UV]](s32)
; PAL: $vgpr1 = COPY [[UV1]](s32)
; PAL: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
; PAL: S_SETPC_B64_return [[COPY1]], implicit $vgpr0, implicit $vgpr1
ret i32 addrspace(4)* @internal_constant ret i32 addrspace(4)* @internal_constant
} }
define i32 addrspace(1)* @internal_global_pcrel() { define i32 addrspace(1)* @internal_global_pcrel() {
; HSA-LABEL: name: internal_global_pcrel ; GCN-LABEL: name: internal_global_pcrel
; HSA: bb.1 (%ir-block.0): ; GCN: bb.1 (%ir-block.0):
; HSA: liveins: $sgpr30_sgpr31 ; GCN: liveins: $sgpr30_sgpr31
; HSA: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 ; GCN: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; HSA: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p1) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @internal_global + 4, target-flags(amdgpu-rel32-hi) @internal_global + 4, implicit-def $scc ; GCN: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p1) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @internal_global + 4, target-flags(amdgpu-rel32-hi) @internal_global + 4, implicit-def $scc
; HSA: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SI_PC_ADD_REL_OFFSET]](p1) ; GCN: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SI_PC_ADD_REL_OFFSET]](p1)
; HSA: $vgpr0 = COPY [[UV]](s32) ; GCN: $vgpr0 = COPY [[UV]](s32)
; HSA: $vgpr1 = COPY [[UV1]](s32) ; GCN: $vgpr1 = COPY [[UV1]](s32)
; HSA: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]] ; GCN: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
; HSA: S_SETPC_B64_return [[COPY1]], implicit $vgpr0, implicit $vgpr1 ; GCN: S_SETPC_B64_return [[COPY1]], implicit $vgpr0, implicit $vgpr1
; PAL-LABEL: name: internal_global_pcrel
; PAL: bb.1 (%ir-block.0):
; PAL: liveins: $sgpr30_sgpr31
; PAL: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; PAL: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p1) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @internal_global + 4, target-flags(amdgpu-rel32-hi) @internal_global + 4, implicit-def $scc
; PAL: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SI_PC_ADD_REL_OFFSET]](p1)
; PAL: $vgpr0 = COPY [[UV]](s32)
; PAL: $vgpr1 = COPY [[UV1]](s32)
; PAL: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
; PAL: S_SETPC_B64_return [[COPY1]], implicit $vgpr0, implicit $vgpr1
ret i32 addrspace(1)* @internal_global ret i32 addrspace(1)* @internal_global
} }
define i32 addrspace(999)* @internal_other_pcrel() { define i32 addrspace(999)* @internal_other_pcrel() {
; HSA-LABEL: name: internal_other_pcrel ; GCN-LABEL: name: internal_other_pcrel
; HSA: bb.1 (%ir-block.0): ; GCN: bb.1 (%ir-block.0):
; HSA: liveins: $sgpr30_sgpr31 ; GCN: liveins: $sgpr30_sgpr31
; HSA: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 ; GCN: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; HSA: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p999) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @internal_other + 4, target-flags(amdgpu-rel32-hi) @internal_other + 4, implicit-def $scc ; GCN: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p999) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @internal_other + 4, target-flags(amdgpu-rel32-hi) @internal_other + 4, implicit-def $scc
; HSA: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SI_PC_ADD_REL_OFFSET]](p999) ; GCN: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SI_PC_ADD_REL_OFFSET]](p999)
; HSA: $vgpr0 = COPY [[UV]](s32) ; GCN: $vgpr0 = COPY [[UV]](s32)
; HSA: $vgpr1 = COPY [[UV1]](s32) ; GCN: $vgpr1 = COPY [[UV1]](s32)
; HSA: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]] ; GCN: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
; HSA: S_SETPC_B64_return [[COPY1]], implicit $vgpr0, implicit $vgpr1 ; GCN: S_SETPC_B64_return [[COPY1]], implicit $vgpr0, implicit $vgpr1
; PAL-LABEL: name: internal_other_pcrel
; PAL: bb.1 (%ir-block.0):
; PAL: liveins: $sgpr30_sgpr31
; PAL: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; PAL: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p999) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @internal_other + 4, target-flags(amdgpu-rel32-hi) @internal_other + 4, implicit-def $scc
; PAL: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SI_PC_ADD_REL_OFFSET]](p999)
; PAL: $vgpr0 = COPY [[UV]](s32)
; PAL: $vgpr1 = COPY [[UV1]](s32)
; PAL: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
; PAL: S_SETPC_B64_return [[COPY1]], implicit $vgpr0, implicit $vgpr1
ret i32 addrspace(999)* @internal_other ret i32 addrspace(999)* @internal_other
} }
define i32 addrspace(6)* @external_constant32_got() { define i32 addrspace(6)* @external_constant32_got() {
; HSA-LABEL: name: external_constant32_got ; GCN-LABEL: name: external_constant32_got
; HSA: bb.1 (%ir-block.0): ; GCN: bb.1 (%ir-block.0):
; HSA: liveins: $sgpr30_sgpr31 ; GCN: liveins: $sgpr30_sgpr31
; HSA: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 ; GCN: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; HSA: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p4) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @external_constant32 + 4, target-flags(amdgpu-gotprel32-hi) @external_constant32 + 4, implicit-def $scc ; GCN: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p4) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @external_constant32 + 4, target-flags(amdgpu-gotprel32-hi) @external_constant32 + 4, implicit-def $scc
; HSA: [[LOAD:%[0-9]+]]:_(p4) = G_LOAD [[SI_PC_ADD_REL_OFFSET]](p4) :: (dereferenceable invariant load 8 from got, addrspace 4) ; GCN: [[LOAD:%[0-9]+]]:_(p4) = G_LOAD [[SI_PC_ADD_REL_OFFSET]](p4) :: (dereferenceable invariant load 8 from got, addrspace 4)
; HSA: [[EXTRACT:%[0-9]+]]:_(p6) = G_EXTRACT [[LOAD]](p4), 0 ; GCN: [[EXTRACT:%[0-9]+]]:_(p6) = G_EXTRACT [[LOAD]](p4), 0
; HSA: $vgpr0 = COPY [[EXTRACT]](p6) ; GCN: $vgpr0 = COPY [[EXTRACT]](p6)
; HSA: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]] ; GCN: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
; HSA: S_SETPC_B64_return [[COPY1]], implicit $vgpr0 ; GCN: S_SETPC_B64_return [[COPY1]], implicit $vgpr0
; PAL-LABEL: name: external_constant32_got
; PAL: bb.1 (%ir-block.0):
; PAL: liveins: $sgpr30_sgpr31
; PAL: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; PAL: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p4) = SI_PC_ADD_REL_OFFSET @external_constant32 + 4, 0, implicit-def $scc
; PAL: [[EXTRACT:%[0-9]+]]:_(p6) = G_EXTRACT [[SI_PC_ADD_REL_OFFSET]](p4), 0
; PAL: $vgpr0 = COPY [[EXTRACT]](p6)
; PAL: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
; PAL: S_SETPC_B64_return [[COPY1]], implicit $vgpr0
ret i32 addrspace(6)* @external_constant32 ret i32 addrspace(6)* @external_constant32
} }
define i32 addrspace(6)* @internal_constant32_pcrel() { define i32 addrspace(6)* @internal_constant32_pcrel() {
; HSA-LABEL: name: internal_constant32_pcrel ; GCN-LABEL: name: internal_constant32_pcrel
; HSA: bb.1 (%ir-block.0): ; GCN: bb.1 (%ir-block.0):
; HSA: liveins: $sgpr30_sgpr31 ; GCN: liveins: $sgpr30_sgpr31
; HSA: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 ; GCN: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; HSA: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p4) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @internal_constant32 + 4, target-flags(amdgpu-rel32-hi) @internal_constant32 + 4, implicit-def $scc ; GCN: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p4) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @internal_constant32 + 4, target-flags(amdgpu-rel32-hi) @internal_constant32 + 4, implicit-def $scc
; HSA: [[EXTRACT:%[0-9]+]]:_(p6) = G_EXTRACT [[SI_PC_ADD_REL_OFFSET]](p4), 0 ; GCN: [[EXTRACT:%[0-9]+]]:_(p6) = G_EXTRACT [[SI_PC_ADD_REL_OFFSET]](p4), 0
; HSA: $vgpr0 = COPY [[EXTRACT]](p6) ; GCN: $vgpr0 = COPY [[EXTRACT]](p6)
; HSA: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]] ; GCN: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
; HSA: S_SETPC_B64_return [[COPY1]], implicit $vgpr0 ; GCN: S_SETPC_B64_return [[COPY1]], implicit $vgpr0
; PAL-LABEL: name: internal_constant32_pcrel
; PAL: bb.1 (%ir-block.0):
; PAL: liveins: $sgpr30_sgpr31
; PAL: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
; PAL: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p4) = SI_PC_ADD_REL_OFFSET @internal_constant32 + 4, 0, implicit-def $scc
; PAL: [[EXTRACT:%[0-9]+]]:_(p6) = G_EXTRACT [[SI_PC_ADD_REL_OFFSET]](p4), 0
; PAL: $vgpr0 = COPY [[EXTRACT]](p6)
; PAL: [[COPY1:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY]]
; PAL: S_SETPC_B64_return [[COPY1]], implicit $vgpr0
ret i32 addrspace(6)* @internal_constant32 ret i32 addrspace(6)* @internal_constant32
} }

llvm/test/CodeGen/AMDGPU/global-constant.ll

; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=PAL %s ; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn-- -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=NOPAL %s ; RUN: llc -mtriple=amdgcn-- -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=NOPAL %s ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=NOPAL %s ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -mtriple=r600-- -mcpu=cypress < %s | FileCheck -check-prefix=R600 %s ; RUN: llc -mtriple=r600-- -mcpu=cypress < %s | FileCheck -check-prefix=R600 %s
@private1 = private unnamed_addr addrspace(4) constant [4 x float] [float 0.0, float 1.0, float 2.0, float 3.0] @private1 = private unnamed_addr addrspace(4) constant [4 x float] [float 0.0, float 1.0, float 2.0, float 3.0]
@private2 = private unnamed_addr addrspace(4) constant [4 x float] [float 4.0, float 5.0, float 6.0, float 7.0] @private2 = private unnamed_addr addrspace(4) constant [4 x float] [float 4.0, float 5.0, float 6.0, float 7.0]
@available_externally = available_externally addrspace(4) global [256 x i32] zeroinitializer @available_externally = available_externally addrspace(4) global [256 x i32] zeroinitializer
; GCN-LABEL: {{^}}private_test: ; GCN-LABEL: {{^}}private_test:
; GCN: s_getpc_b64 s{{\[}}[[PC0_LO:[0-9]+]]:[[PC0_HI:[0-9]+]]{{\]}} ; GCN: s_getpc_b64 s{{\[}}[[PC0_LO:[0-9]+]]:[[PC0_HI:[0-9]+]]{{\]}}
; PAL OSes use fixup into .text section. ; Non-R600 OSes use relocations.
; PAL: s_add_u32 s{{[0-9]+}}, s[[PC0_LO]], private1 ; GCN: s_add_u32 s{{[0-9]+}}, s[[PC0_LO]], private1@rel32@lo+4
; PAL: s_addc_u32 s{{[0-9]+}}, s[[PC0_HI]], 0 ; GCN: s_addc_u32 s{{[0-9]+}}, s[[PC0_HI]], private1@rel32@hi+4
; Non-PAL OSes use relocations.
; NOPAL: s_add_u32 s{{[0-9]+}}, s[[PC0_LO]], private1@rel32@lo+4
; NOPAL: s_addc_u32 s{{[0-9]+}}, s[[PC0_HI]], private1@rel32@hi+4
; GCN: s_getpc_b64 s{{\[}}[[PC1_LO:[0-9]+]]:[[PC1_HI:[0-9]+]]{{\]}} ; GCN: s_getpc_b64 s{{\[}}[[PC1_LO:[0-9]+]]:[[PC1_HI:[0-9]+]]{{\]}}
; GCN: s_add_u32 s{{[0-9]+}}, s[[PC1_LO]], private2@rel32@lo+4
; PAL OSes use fixup into .text section. ; GCN: s_addc_u32 s{{[0-9]+}}, s[[PC1_HI]], private2@rel32@hi+4
; PAL: s_add_u32 s{{[0-9]+}}, s[[PC1_LO]], private2
; PAL: s_addc_u32 s{{[0-9]+}}, s[[PC1_HI]], 0
; Non-PAL OSes use relocations.
; NOPAL: s_add_u32 s{{[0-9]+}}, s[[PC1_LO]], private2@rel32@lo+4
; NOPAL: s_addc_u32 s{{[0-9]+}}, s[[PC1_HI]], private2@rel32@hi+4
; R600-LABEL: private_test ; R600-LABEL: private_test
define amdgpu_kernel void @private_test(i32 %index, float addrspace(1)* %out) { define amdgpu_kernel void @private_test(i32 %index, float addrspace(1)* %out) {
%ptr = getelementptr [4 x float], [4 x float] addrspace(4) * @private1, i32 0, i32 %index %ptr = getelementptr [4 x float], [4 x float] addrspace(4) * @private1, i32 0, i32 %index
%val = load float, float addrspace(4)* %ptr %val = load float, float addrspace(4)* %ptr
store volatile float %val, float addrspace(1)* %out store volatile float %val, float addrspace(1)* %out
%ptr2 = getelementptr [4 x float], [4 x float] addrspace(4) * @private2, i32 0, i32 %index %ptr2 = getelementptr [4 x float], [4 x float] addrspace(4) * @private2, i32 0, i32 %index
%val2 = load float, float addrspace(4)* %ptr2 %val2 = load float, float addrspace(4)* %ptr2
store volatile float %val2, float addrspace(1)* %out store volatile float %val2, float addrspace(1)* %out
ret void ret void
} }
; NOPAL-LABEL: {{^}}available_externally_test: ; GCN-LABEL: {{^}}available_externally_test:
; NOPAL: s_getpc_b64 s{{\[}}[[PC0_LO:[0-9]+]]:[[PC0_HI:[0-9]+]]{{\]}} ; GCN: s_getpc_b64 s{{\[}}[[PC0_LO:[0-9]+]]:[[PC0_HI:[0-9]+]]{{\]}}
; NOPAL: s_add_u32 s{{[0-9]+}}, s[[PC0_LO]], available_externally@gotpcrel32@lo+4 ; GCN: s_add_u32 s{{[0-9]+}}, s[[PC0_LO]], available_externally@gotpcrel32@lo+4
; NOPAL: s_addc_u32 s{{[0-9]+}}, s[[PC0_HI]], available_externally@gotpcrel32@hi+4 ; GCN: s_addc_u32 s{{[0-9]+}}, s[[PC0_HI]], available_externally@gotpcrel32@hi+4
; R600-LABEL: available_externally_test ; R600-LABEL: available_externally_test
define amdgpu_kernel void @available_externally_test(i32 addrspace(1)* %out) { define amdgpu_kernel void @available_externally_test(i32 addrspace(1)* %out) {
%ptr = getelementptr [256 x i32], [256 x i32] addrspace(4)* @available_externally, i32 0, i32 1 %ptr = getelementptr [256 x i32], [256 x i32] addrspace(4)* @available_externally, i32 0, i32 1
%val = load i32, i32 addrspace(4)* %ptr %val = load i32, i32 addrspace(4)* %ptr
store i32 %val, i32 addrspace(1)* %out store i32 %val, i32 addrspace(1)* %out
ret void ret void
} }
; PAL: .text ; GCN: .section .rodata
; NOPAL: .section .rodata
; R600: .text ; R600: .text
; GCN: private1: ; GCN: private1:
; GCN: private2: ; GCN: private2:
; R600: private1: ; R600: private1:
; R600: private2: ; R600: private2: