[PowerPC] Implement __int128 vector divide operations

[Conanap]

Summary

This patch implements __int128 vector divide operations for ISA3.1.

[amyk]

Overall LGTM.

llvm/test/CodeGen/PowerPC/p10-vector-divide.ll

53

nit: I think nounwind readnone can probably be omitted.

clang/lib/Headers/altivec.h

 }
 
 static __inline__ vector unsigned long long __ATTRS_o_ai
 vec_dive(vector unsigned long long __a, vector unsigned long long __b) {
   return __builtin_altivec_vdiveud(__a, __b);
 }
 #endif
 
+#ifdef __POWER10_VECTOR__
+static __inline__ vector unsigned __int128 __ATTRS_o_ai
+vec_div(vector unsigned __int128 __a, vector unsigned __int128 __b) {
+  return __a / __b;
+}
+
+static __inline__ vector signed __int128 __ATTRS_o_ai
+vec_div(vector signed __int128 __a, vector signed __int128 __b) {
+  return __a / __b;
+}
+#endif __POWER10_VECTOR__
+
 /* vec_dss */
 
 #define vec_dss __builtin_altivec_dss
 
 /* vec_dssall */
 
 static __inline__ void __attribute__((__always_inline__)) vec_dssall(void) {
   __builtin_altivec_dssall();

clang/test/CodeGen/builtins-ppc-p10vector.c

 vector signed char vsca, vscb;
 vector unsigned char vuca, vucb, vucc;
 vector signed short vssa, vssb;
 vector unsigned short vusa, vusb, vusc;
 vector signed int vsia, vsib;
 vector unsigned int vuia, vuib, vuic;
 vector signed long long vslla, vsllb;
 vector unsigned long long vulla, vullb, vullc;
+vector signed __int128 vsi128a, vsi128b;
 vector unsigned __int128 vui128a, vui128b, vui128c;
 vector float vfa, vfb;
 vector double vda, vdb;
 signed int *iap;
 unsigned int uia, uib, *uiap;
 signed char *cap;
 unsigned char uca;
 const unsigned char *ucap;

 }
 
 vector unsigned long long test_vec_div_ull(void) {
   // CHECK: udiv <2 x i64>
   // CHECK-NEXT: ret <2 x i64>
   return vec_div(vulla, vullb);
 }
 
+vector unsigned __int128 test_vec_div_u128(void) {
+  // CHECK: udiv <1 x i128>
+  // CHECK-NEXT: ret <1 x i128>
+  return vec_div(vui128a, vui128b);
+}
+
+vector signed __int128 test_vec_div_s128(void) {
+  // CHECK: sdiv <1 x i128>
+  // CHECK-NEXT: ret <1 x i128>
+  return vec_div(vsi128a, vsi128b);
+}
+
 vector signed int test_vec_dive_si(void) {
   // CHECK: @llvm.ppc.altivec.vdivesw(<4 x i32> %{{.+}}, <4 x i32> %{{.+}})
   // CHECK-NEXT: ret <4 x i32>
   return vec_dive(vsia, vsib);
 }
 
 vector unsigned int test_vec_dive_ui(void) {
   // CHECK: @llvm.ppc.altivec.vdiveuw(<4 x i32> %{{.+}}, <4 x i32> %{{.+}})

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

if (Subtarget.isISA3_1()) {
       setOperationAction(ISD::UDIV, MVT::v2i64, Legal);
       setOperationAction(ISD::SDIV, MVT::v2i64, Legal);
       setOperationAction(ISD::UDIV, MVT::v4i32, Legal);
       setOperationAction(ISD::SDIV, MVT::v4i32, Legal);
       setOperationAction(ISD::UREM, MVT::v2i64, Legal);
       setOperationAction(ISD::SREM, MVT::v2i64, Legal);
       setOperationAction(ISD::UREM, MVT::v4i32, Legal);
       setOperationAction(ISD::SREM, MVT::v4i32, Legal);
+      setOperationAction(ISD::UDIV, MVT::v1i128, Legal);
+      setOperationAction(ISD::SDIV, MVT::v1i128, Legal);
     }
 
     setOperationAction(ISD::MUL, MVT::v8i16, Legal);
     setOperationAction(ISD::MUL, MVT::v16i8, Custom);
 
     setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
     setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
 

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

def VMULOUD : VXForm_1<200, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
                          "vmuloud $vD, $vA, $vB", IIC_VecGeneral,
                          [(set v1i128:$vD, (int_ppc_altivec_vmuloud v2i64:$vA,
                                v2i64:$vB))]>;
   def VMSUMCUD : VAForm_1a<23, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC),
                            "vmsumcud $vD, $vA, $vB, $vC", IIC_VecGeneral,
                            [(set v1i128:$vD, (int_ppc_altivec_vmsumcud
                                  v2i64:$vA, v2i64:$vB, v1i128:$vC))]>;
   def VDIVSQ : VXForm_1<267, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
-                        "vdivsq $vD, $vA, $vB", IIC_VecGeneral, []>;
+                        "vdivsq $vD, $vA, $vB", IIC_VecGeneral,
+                        [(set v1i128:$vD, (sdiv v1i128:$vA, v1i128:$vB))]>;
   def VDIVUQ : VXForm_1<11, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
-                        "vdivuq $vD, $vA, $vB", IIC_VecGeneral, []>;
+                        "vdivuq $vD, $vA, $vB", IIC_VecGeneral,
+                        [(set v1i128:$vD, (udiv v1i128:$vA, v1i128:$vB))]>;
   def VDIVESQ : VXForm_1<779, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
                          "vdivesq $vD, $vA, $vB", IIC_VecGeneral, []>;
   def VDIVEUQ : VXForm_1<523, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
                          "vdiveuq $vD, $vA, $vB", IIC_VecGeneral, []>;
   def VCMPEQUQ : VCMP <455, "vcmpequq $vD, $vA, $vB" , v1i128>;
   def VCMPGTSQ : VCMP <903, "vcmpgtsq $vD, $vA, $vB" , v1i128>;
   def VCMPGTUQ : VCMP <647, "vcmpgtuq $vD, $vA, $vB" , v1i128>;
   def VCMPEQUQ_rec : VCMPo <455, "vcmpequq. $vD, $vA, $vB" , v1i128>;

llvm/test/CodeGen/PowerPC/p10-vector-divide.ll

 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vdivsw v2, v2, v3
 ; CHECK-NEXT:    blr
 entry:
   %div = sdiv <4 x i32> %a, %b
   ret <4 x i32> %div
 }
 
 ; Test the vector divide extended intrinsics.
 declare <4 x i32> @llvm.ppc.altivec.vdivesw(<4 x i32>, <4 x i32>)
 declare <4 x i32> @llvm.ppc.altivec.vdiveuw(<4 x i32>, <4 x i32>)
 declare <2 x i64> @llvm.ppc.altivec.vdivesd(<2 x i64>, <2 x i64>)
 declare <2 x i64> @llvm.ppc.altivec.vdiveud(<2 x i64>, <2 x i64>)
 
 define <4 x i32> @test_vdivesw(<4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LABEL: test_vdivesw:
 ; CHECK:       # %bb.0: # %entry

 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vdiveuw v2, v2, v3
 ; CHECK-NEXT:    blr
 entry:
   %div = tail call <4 x i32> @llvm.ppc.altivec.vdiveuw(<4 x i32> %a, <4 x i32> %b)
   ret <4 x i32> %div
 }
 
+define <1 x i128> @test_vdivsq(<1 x i128> %x, <1 x i128> %y) nounwind readnone {
+; CHECK-LABEL: test_vdivsq:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vdivsq v2, v2, v3
+; CHECK-NEXT:    blr
+  %tmp = sdiv <1 x i128> %x, %y
+  ret <1 x i128> %tmp
+}
+
+define <1 x i128> @test_vdivuq(<1 x i128> %x, <1 x i128> %y) nounwind readnone {
+; CHECK-LABEL: test_vdivuq:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vdivuq v2, v2, v3
+; CHECK-NEXT:    blr
+  %tmp = udiv <1 x i128> %x, %y
+  ret <1 x i128> %tmp
+}
+
 define <2 x i64> @test_vdivesd(<2 x i64> %a, <2 x i64> %b) {
 ; CHECK-LABEL: test_vdivesd:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vdivesd v2, v2, v3
 ; CHECK-NEXT:    blr
 entry:
   %div = tail call <2 x i64> @llvm.ppc.altivec.vdivesd(<2 x i64> %a, <2 x i64> %b)
   ret <2 x i64> %div