[ARM] Generated SSAT and USAT instructions with shift

[MeeraN]

Summary

Added patterns so that both SSAT and USAT instructions are generated with shifts. Added corresponding regression tests as well.

[dmgreen]

llvm/lib/Target/ARM/ARMInstrThumb2.td

88

Any chance we can combine asr_imm_XFORM/asr_imm and t2_asr_imm_XFORM / t2_asr_imm to use the same SDNodeXForm? I think asr_imm should be visible in both these files.

llvm/test/CodeGen/Thumb2/thumb2-usat-with-shift.ll

2

This can just be -mattr=+dsp I think. You could also just include this as a RUN line in the ARM/usat-with-shift.ll test if that's simpler. Up to you.

[MeeraN]

Removed t2_asr_imm and replaced with just asr_imm. Also deleted thumb2 tests and instead included Run command in arm tests to avoid having the same tests repeated.

[dmgreen]

LGTM. Thanks

[MeeraN]

Closed by revision https://reviews.llvm.org/rG20283ff491a4

llvm/lib/Target/ARM/ARMInstrInfo.td

def imm_neg_XFORM : SDNodeXForm<imm, [{
   return CurDAG->getTargetConstant(-(int)N->getZExtValue(), SDLoc(N), MVT::i32);
 }]>;
 
 // imm_not_XFORM - Return the complement of a i32 immediate value.
 def imm_not_XFORM : SDNodeXForm<imm, [{
   return CurDAG->getTargetConstant(~(int)N->getZExtValue(), SDLoc(N), MVT::i32);
 }]>;
 
+// asr_imm_XFORM - Returns a shift immediate with bit {5} set to 1
+def asr_imm_XFORM : SDNodeXForm<imm, [{
+  return CurDAG->getTargetConstant(0x20 | N->getZExtValue(), SDLoc(N), MVT:: i32);
+}]>;
+
 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
 def imm16_31 : ImmLeaf<i32, [{
   return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
 }]>;
 
 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
   return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;

 // An 'fsub' node which checks for single non-hazardous use.
 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
   return hasNoVMLxHazardUse(N);
 }]>;
 
 def imm_even : ImmLeaf<i32, [{ return (Imm & 1) == 0; }]>;
 def imm_odd : ImmLeaf<i32, [{ return (Imm & 1) == 1; }]>;
 
+def asr_imm : ImmLeaf<i32, [{ return Imm > 0 && Imm <= 32; }], asr_imm_XFORM>;
+
 //===----------------------------------------------------------------------===//
 // NEON/MVE pattern fragments
 //
 
 // Extract D sub-registers of Q registers.
 def DSubReg_i8_reg  : SDNodeXForm<imm, [{
   assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
   return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/8, SDLoc(N),

 def : ARMPat<(ARMssatnoshift GPRnopc:$Rn, imm0_31:$imm),
              (SSAT imm0_31:$imm, GPRnopc:$Rn, 0)>;
 def : ARMPat<(ARMusatnoshift GPRnopc:$Rn, imm0_31:$imm),
              (USAT imm0_31:$imm, GPRnopc:$Rn, 0)>;
 def : ARMV6Pat<(int_arm_ssat16 GPRnopc:$a, imm1_16:$pos),
                (SSAT16 imm1_16:$pos, GPRnopc:$a)>;
 def : ARMV6Pat<(int_arm_usat16 GPRnopc:$a, imm0_15:$pos),
                (USAT16 imm0_15:$pos, GPRnopc:$a)>;
+def : ARMV6Pat<(int_arm_ssat (shl GPRnopc:$a, imm0_31:$shft), imm1_32:$pos),
+               (SSAT imm1_32:$pos, GPRnopc:$a, imm0_31:$shft)>;
+def : ARMV6Pat<(int_arm_ssat (sra GPRnopc:$a, asr_imm:$shft), imm1_32:$pos),
+               (SSAT imm1_32:$pos, GPRnopc:$a, asr_imm:$shft)>;
+def : ARMV6Pat<(int_arm_usat (shl GPRnopc:$a, imm0_31:$shft), imm0_31:$pos),
+               (USAT imm0_31:$pos, GPRnopc:$a, imm0_31:$shft)>;
+def : ARMV6Pat<(int_arm_usat (sra GPRnopc:$a, asr_imm:$shft), imm0_31:$pos),
+               (USAT imm0_31:$pos, GPRnopc:$a, asr_imm:$shft)>;
+
 
 //===----------------------------------------------------------------------===//
 //  Bitwise Instructions.
 //
 
 defm AND   : AsI1_bin_irs<0b0000, "and",
                           IIC_iBITi, IIC_iBITr, IIC_iBITsr, and, 1>;
 defm ORR   : AsI1_bin_irs<0b1100, "orr",

llvm/lib/Target/ARM/ARMInstrThumb2.td

 // described for so_imm_notSext def below, with sign extension from 16
 // bits.
 def t2_so_imm_notSext16_XFORM : SDNodeXForm<imm, [{
   APInt apIntN = N->getAPIntValue();
   unsigned N16bitSignExt = apIntN.trunc(16).sext(32).getZExtValue();
   return CurDAG->getTargetConstant(~N16bitSignExt, SDLoc(N), MVT::i32);
 }]>;
 
+// t2_asr_imm - Returns immediate with bit {5} set to 1
+def t2_asr_imm_XFORM : SDNodeXForm<imm, [{
+  return CurDAG->getTargetConstant(0x20 | N->getZExtValue(), SDLoc(N),
+                                   MVT:: i32);
+}]>;
+
 // t2_so_imm - Match a 32-bit immediate operand, which is an
 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
 // immediate splatted into multiple bytes of the word.
 def t2_so_imm_asmoperand : AsmOperandClass {
   let Name = "T2SOImm";
   let RenderMethod = "addImmOperands";
 
 }

 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
 def t2_so_imm_neg_asmoperand : AsmOperandClass { let Name = "T2SOImmNeg"; }
 def t2_so_imm_neg : Operand<i32>, ImmLeaf<i32, [{
   return Imm && ARM_AM::getT2SOImmVal(-(uint32_t)Imm) != -1;
 }], t2_so_imm_neg_XFORM> {
   let ParserMatchClass = t2_so_imm_neg_asmoperand;
 }
 
+// t2_asr_imm - Match an immediate that has bit {5} set to 1
+def t2_asr_imm : ImmLeaf<i32, [{
+  return Imm > 0 && Imm < 32;
+}], t2_asr_imm_XFORM>;
+
 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0,4095].
 def imm0_4095_asmoperand: ImmAsmOperand<0,4095> { let Name = "Imm0_4095"; }
 def imm0_4095 : Operand<i32>, ImmLeaf<i32, [{
   return Imm >= 0 && Imm < 4096;
 }]> {
   let ParserMatchClass = imm0_4095_asmoperand;
 }
 

 def : T2Pat<(int_arm_ssat GPR:$a, imm1_32:$pos),
             (t2SSAT imm1_32:$pos, GPR:$a, 0)>;
 def : T2Pat<(int_arm_usat GPR:$a, imm0_31:$pos),
             (t2USAT imm0_31:$pos, GPR:$a, 0)>;
 def : T2Pat<(int_arm_ssat16 GPR:$a, imm1_16:$pos),
             (t2SSAT16 imm1_16:$pos, GPR:$a)>;
 def : T2Pat<(int_arm_usat16 GPR:$a, imm0_15:$pos),
             (t2USAT16 imm0_15:$pos, GPR:$a)>;
+def : T2Pat<(int_arm_ssat (shl GPRnopc:$a, imm0_31:$shft), imm1_32:$pos),
+            (t2SSAT imm1_32:$pos, GPRnopc:$a, imm0_31:$shft)>;
+def : T2Pat<(int_arm_ssat (sra GPRnopc:$a, t2_asr_imm:$shft), imm1_32:$pos),
+            (t2SSAT imm1_32:$pos, GPRnopc:$a, t2_asr_imm:$shft)>;
+def : T2Pat<(int_arm_usat (shl GPRnopc:$a, imm0_31:$shft), imm0_31:$pos),
+            (t2USAT imm0_31:$pos, GPRnopc:$a, imm0_31:$shft)>;
+def : T2Pat<(int_arm_usat (sra GPRnopc:$a, t2_asr_imm:$shft), imm0_31:$pos),
+            (t2USAT imm0_31:$pos, GPRnopc:$a, t2_asr_imm:$shft)>;
+
 
 //===----------------------------------------------------------------------===//
 //  Shift and rotate Instructions.
 //
 
 defm t2LSL  : T2I_sh_ir<0b00, "lsl", imm1_31, shl>;
 defm t2LSR  : T2I_sh_ir<0b01, "lsr", imm_sr,  srl>;
 defm t2ASR  : T2I_sh_ir<0b10, "asr", imm_sr,  sra>;

llvm/test/CodeGen/ARM/ssat-with-shift.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=armv6-eabi %s -o - | FileCheck %s
+
+define arm_aapcs_vfpcc i32 @ssat_lsl(i32 %num){
+; CHECK-LABEL:  ssat_lsl
+; CHECK:        @ %bb.0: @ %entry
+; CHECK-NEXT:   ssat  r0, #8, r0, lsl #7
+; CHECK-NEXT:   bx  lr
+entry:
+  %shl = shl i32 %num, 7
+  %0 = tail call i32 @llvm.arm.ssat(i32 %shl, i32 8)
+  ret i32 %0
+}
+
+define arm_aapcs_vfpcc i32 @ssat_asr(i32 %num){
+; CHECK-LABEL:  ssat_asr
+; CHECK:        @ %bb.0: @ %entry
+; CHECK-NEXT:   ssat  r0, #8, r0, asr #7
+; CHECK-NEXT:   bx  lr
+entry:
+  %shr = ashr i32 %num, 7
+  %0 = tail call i32 @llvm.arm.ssat(i32 %shr, i32 8)
+  ret i32 %0
+}
+
+declare i32 @llvm.arm.ssat(i32, i32)

llvm/test/CodeGen/ARM/usat-with-shift.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=armv6-eabi %s -o - | FileCheck %s
+
+define arm_aapcs_vfpcc i32 @usat_lsl(i32 %num){
+; CHECK-LABEL:  usat_lsl
+; CHECK:        @ %bb.0: @ %entry
+; CHECK-NEXT:   usat  r0, #7, r0, lsl #2
+; CHECK-NEXT:   bx  lr
+entry:
+  %shl = shl i32 %num, 2
+  %0 = tail call i32 @llvm.arm.usat(i32 %shl, i32 7)
+  ret i32 %0
+}
+
+define arm_aapcs_vfpcc i32 @usat_asr(i32 %num){
+; CHECK-LABEL:  usat_asr
+; CHECK:        @ %bb.0: @ %entry
+; CHECK-NEXT:   usat  r0, #7, r0, asr #2
+; CHECK-NEXT:   bx  lr
+entry:
+  %shr = ashr i32 %num, 2
+  %0 = tail call i32 @llvm.arm.usat(i32 %shr, i32 7)
+  ret i32 %0
+}
+
+declare i32 @llvm.arm.usat(i32, i32)

llvm/test/CodeGen/Thumb2/thumb2-ssat-with-shift.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp,+fp64 %s -o - | FileCheck %s
+
+define arm_aapcs_vfpcc i32 @ssat_lsl(i32 %num){
+; CHECK-LABEL:  ssat_lsl
+; CHECK:        @ %bb.0: @ %entry
+; CHECK-NEXT:   ssat  r0, #8, r0, lsl #7
+; CHECK-NEXT:   bx  lr
+entry:
+  %shl = shl i32 %num, 7
+  %0 = tail call i32 @llvm.arm.ssat(i32 %shl, i32 8)
+  ret i32 %0
+}
+
+define arm_aapcs_vfpcc i32 @ssat_asr(i32 %num){
+; CHECK-LABEL:  ssat_asr
+; CHECK:        @ %bb.0: @ %entry
+; CHECK-NEXT:   ssat  r0, #8, r0, asr #7
+; CHECK-NEXT:   bx  lr
+entry:
+  %shr = ashr i32 %num, 7
+  %0 = tail call i32 @llvm.arm.ssat(i32 %shr, i32 8)
+  ret i32 %0
+}
+
+declare i32 @llvm.arm.ssat(i32, i32)

llvm/test/CodeGen/Thumb2/thumb2-usat-with-shift.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp,+fp64 %s -o - | FileCheck %s
+
+define arm_aapcs_vfpcc i32 @usat_lsl(i32 %num){
+; CHECK-LABEL:  usat_lsl
+; CHECK:        @ %bb.0: @ %entry
+; CHECK-NEXT:   usat  r0, #7, r0, lsl #2
+; CHECK-NEXT:   bx  lr
+entry:
+  %shl = shl i32 %num, 2
+  %0 = tail call i32 @llvm.arm.usat(i32 %shl, i32 7)
+  ret i32 %0
+}
+
+define arm_aapcs_vfpcc i32 @usat_asr(i32 %num){
+; CHECK-LABEL:  usat_asr
+; CHECK:        @ %bb.0: @ %entry
+; CHECK-NEXT:   usat  r0, #7, r0, asr #2
+; CHECK-NEXT:   bx  lr
+entry:
+  %shr = ashr i32 %num, 2
+  %0 = tail call i32 @llvm.arm.usat(i32 %shr, i32 7)
+  ret i32 %0
+}
+
+declare i32 @llvm.arm.usat(i32, i32)