This is an archive of the discontinued LLVM Phabricator instance.

[Statepoint] When using the tied def lowering, unconditionally use vregs [almost NFC]
ClosedPublic

Authored by reames on Jul 27 2020, 12:08 PM.

Details

Summary

This builds on 3da1a96 on the path towards supporting invokes and cross block relocations. The actual change attempts to be NFC, but does fail in one corner-case explained below.

The change itself is fairly mechanical. Rather than remember SDValues - which are inherently block local - immediately produce a virtual register copy and remember that.

Once this lands, we'll update the FunctionLoweringInfo::StatepointSpillMap map to allow register based lowerings, delete VirtRegs from StatepointLowering, and drop the restriction against cross block relocations. I deliberately separate the semantic part into it's own change for easy of understanding and fault isolation.

The corner-case which isn't quite NFC is that the old implementation implicitly CSEd gc.relocates of the same SDValue regardless of type. The new implementation still only relocates once, but it produces distinct vregs for the bitcast and it's source, whereas SelectionDAG's generic CSE was able to remove the bitcast in the old implementation. Note that the final assembly doesn't change (at least in the test), as our MI level optimizations catch the duplication.

I assert that this is an uninteresting corner-case. It's functionally correct, and if we find a case where this influences performance, we should really be canonicalizing types to i8* at the IR level.

Diff Detail

Event Timeline

reames created this revision.Jul 27 2020, 12:08 PM
Herald added a project: Restricted Project. · View Herald TranscriptJul 27 2020, 12:08 PM
arsenm added a subscriber: arsenm.Jul 27 2020, 12:21 PM
arsenm added inline comments.
llvm/lib/CodeGen/SelectionDAG/StatepointLowering.cpp
878

Register

llvm/lib/CodeGen/SelectionDAG/StatepointLowering.h
108

Should use Register

reames updated this revision to Diff 281023.Jul 27 2020, 12:34 PM

Address Register related review comments

skatkov accepted this revision.Jul 28 2020, 11:01 PM

lgtm

llvm/lib/CodeGen/SelectionDAG/StatepointLowering.cpp
1120

do you really need these empty lines?

1122

redundant dot.

This revision is now accepted and ready to land.Jul 28 2020, 11:01 PM