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Differential D84384

[PowerPC][Power10] Add Vector Extract Double Instruction Definitions and MC tests
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Authored by biplmish on Jul 22 2020, 11:06 PM.

Details

Reviewers
nemanjai
amyk
steven.zhang
lei
Group Reviewers
Restricted Project
Commits
rG825ed2d43d6f: [PowerPC] Add Vector Extract Double Instruction Definitions and MC tests.
Summary

This patch adds the td definitions and asm/disasm tests for the following instructions:

Vector Extract Double Left Index - vextdubvlx, vextduhvlx, vextduwvlx, vextddvlx
Vector Extract Double Right Index - vextdubvrx, vextduhvrx, vextduwvrx, vextddvrx

Diff Detail

Event Timeline

biplmish created this revision.Jul 22 2020, 11:06 PM
Herald added a project: Restricted Project. · View Herald TranscriptJul 22 2020, 11:06 PM
Herald added subscribers: shchenz, • wuzish, kbarton, hiraditya. · View Herald Transcript
biplmish set the repository for this revision to rG LLVM Github Monorepo.Jul 23 2020, 4:44 AM
lei accepted this revision as: lei.Jul 23 2020, 5:31 AM

LGTM

This revision is now accepted and ready to land.Jul 23 2020, 5:31 AM
amyk accepted this revision as: amyk.Jul 23 2020, 6:57 AM

LGTM.

Closed by commit rG825ed2d43d6f: [PowerPC] Add Vector Extract Double Instruction Definitions and MC tests. (authored by biplmish). · Explain WhyJul 26 2020, 9:56 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
lib/
Target/
PowerPC/
32 lines
test/
MC/
Disassembler/
PowerPC/
24 lines
PowerPC/
24 lines

Diff 280031

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

Show First 20 Lines • Show All 899 Lines • ▼ Show 20 Lines VXForm_1<719, (outs vrrc:$vD), (ins vrrc:$vDi, g8rc:$rA, g8rc:$rB),
(int_ppc_altivec_vinsdlx v2i64:$vDi, i64:$rA, i64:$rB))]>, (int_ppc_altivec_vinsdlx v2i64:$vDi, i64:$rA, i64:$rB))]>,
RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
def VINSDRX : def VINSDRX :
VXForm_1<975, (outs vrrc:$vD), (ins vrrc:$vDi, g8rc:$rA, g8rc:$rB), VXForm_1<975, (outs vrrc:$vD), (ins vrrc:$vDi, g8rc:$rA, g8rc:$rB),
"vinsdrx $vD, $rA, $rB", IIC_VecGeneral, "vinsdrx $vD, $rA, $rB", IIC_VecGeneral,
[(set v2i64:$vD, [(set v2i64:$vD,
(int_ppc_altivec_vinsdrx v2i64:$vDi, i64:$rA, i64:$rB))]>, (int_ppc_altivec_vinsdrx v2i64:$vDi, i64:$rA, i64:$rB))]>,
RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
def VEXTDUBVLX : VAForm_1a<24, (outs vrrc:$vD),
(ins vrrc:$vA, vrrc:$vB, g8rc:$rC),
"vextdubvlx $vD, $vA, $vB, $rC",
IIC_VecGeneral, []>;
def VEXTDUBVRX : VAForm_1a<25, (outs vrrc:$vD),
(ins vrrc:$vA, vrrc:$vB, g8rc:$rC),
"vextdubvrx $vD, $vA, $vB, $rC",
IIC_VecGeneral, []>;
def VEXTDUHVLX : VAForm_1a<26, (outs vrrc:$vD),
(ins vrrc:$vA, vrrc:$vB, g8rc:$rC),
"vextduhvlx $vD, $vA, $vB, $rC",
IIC_VecGeneral, []>;
def VEXTDUHVRX : VAForm_1a<27, (outs vrrc:$vD),
(ins vrrc:$vA, vrrc:$vB, g8rc:$rC),
"vextduhvrx $vD, $vA, $vB, $rC",
IIC_VecGeneral, []>;
def VEXTDUWVLX : VAForm_1a<28, (outs vrrc:$vD),
(ins vrrc:$vA, vrrc:$vB, g8rc:$rC),
"vextduwvlx $vD, $vA, $vB, $rC",
IIC_VecGeneral, []>;
def VEXTDUWVRX : VAForm_1a<29, (outs vrrc:$vD),
(ins vrrc:$vA, vrrc:$vB, g8rc:$rC),
"vextduwvrx $vD, $vA, $vB, $rC",
IIC_VecGeneral, []>;
def VEXTDDVLX : VAForm_1a<30, (outs vrrc:$vD),
(ins vrrc:$vA, vrrc:$vB, g8rc:$rC),
"vextddvlx $vD, $vA, $vB, $rC",
IIC_VecGeneral, []>;
def VEXTDDVRX : VAForm_1a<31, (outs vrrc:$vD),
(ins vrrc:$vA, vrrc:$vB, g8rc:$rC),
"vextddvrx $vD, $vA, $vB, $rC",
IIC_VecGeneral, []>;
def VPDEPD : VXForm_1<1485, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VPDEPD : VXForm_1<1485, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
"vpdepd $vD, $vA, $vB", IIC_VecGeneral, "vpdepd $vD, $vA, $vB", IIC_VecGeneral,
[(set v2i64:$vD, [(set v2i64:$vD,
(int_ppc_altivec_vpdepd v2i64:$vA, v2i64:$vB))]>; (int_ppc_altivec_vpdepd v2i64:$vA, v2i64:$vB))]>;
def VPEXTD : VXForm_1<1421, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VPEXTD : VXForm_1<1421, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
"vpextd $vD, $vA, $vB", IIC_VecGeneral, "vpextd $vD, $vA, $vB", IIC_VecGeneral,
[(set v2i64:$vD, [(set v2i64:$vD,
(int_ppc_altivec_vpextd v2i64:$vA, v2i64:$vB))]>; (int_ppc_altivec_vpextd v2i64:$vA, v2i64:$vB))]>;
▲ Show 20 Lines • Show All 213 Lines • Show Last 20 Lines

llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt

Show First 20 Lines • Show All 324 Lines • ▼ Show 20 Lines
0x10 0x22 0x1b 0x8f 0x10 0x22 0x1b 0x8f
# CHECK: vinsdlx 1, 2, 3 # CHECK: vinsdlx 1, 2, 3
0x10 0x22 0x1a 0xcf 0x10 0x22 0x1a 0xcf
# CHECK: vinsdrx 1, 2, 3 # CHECK: vinsdrx 1, 2, 3
0x10 0x22 0x1b 0xcf 0x10 0x22 0x1b 0xcf
# CHECK: vextdubvlx 1, 2, 3, 3
0x10 0x22 0x18 0xd8
# CHECK: vextdubvrx 1, 2, 3, 3
0x10 0x22 0x18 0xd9
# CHECK: vextduhvlx 1, 2, 3, 3
0x10 0x22 0x18 0xda
# CHECK: vextduhvrx 1, 2, 3, 3
0x10 0x22 0x18 0xdb
# CHECK: vextduwvlx 1, 2, 3, 3
0x10 0x22 0x18 0xdc
# CHECK: vextduwvrx 1, 2, 3, 3
0x10 0x22 0x18 0xdd
# CHECK: vextddvlx 1, 2, 3, 3
0x10 0x22 0x18 0xde
# CHECK: vextddvrx 1, 2, 3, 3
0x10 0x22 0x18 0xdf
# CHECK: lxvrbx 32, 1, 2 # CHECK: lxvrbx 32, 1, 2
0x7c 0x01 0x10 0x1b 0x7c 0x01 0x10 0x1b
# CHECK: lxvrhx 33, 1, 2 # CHECK: lxvrhx 33, 1, 2
0x7c 0x21 0x10 0x5b 0x7c 0x21 0x10 0x5b
# CHECK: lxvrdx 34, 1, 2 # CHECK: lxvrdx 34, 1, 2
0x7c 0x41 0x10 0xdb 0x7c 0x41 0x10 0xdb
▲ Show 20 Lines • Show All 97 Lines • Show Last 20 Lines

llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s

Show First 20 Lines • Show All 450 Lines • ▼ Show 20 Lines
# CHECK-LE: vinswrx 1, 2, 3 # encoding: [0x8f,0x1b,0x22,0x10] # CHECK-LE: vinswrx 1, 2, 3 # encoding: [0x8f,0x1b,0x22,0x10]
vinswrx 1, 2, 3 vinswrx 1, 2, 3
# CHECK-BE: vinsdlx 1, 2, 3 # encoding: [0x10,0x22,0x1a,0xcf] # CHECK-BE: vinsdlx 1, 2, 3 # encoding: [0x10,0x22,0x1a,0xcf]
# CHECK-LE: vinsdlx 1, 2, 3 # encoding: [0xcf,0x1a,0x22,0x10] # CHECK-LE: vinsdlx 1, 2, 3 # encoding: [0xcf,0x1a,0x22,0x10]
vinsdlx 1, 2, 3 vinsdlx 1, 2, 3
# CHECK-BE: vinsdrx 1, 2, 3 # encoding: [0x10,0x22,0x1b,0xcf] # CHECK-BE: vinsdrx 1, 2, 3 # encoding: [0x10,0x22,0x1b,0xcf]
# CHECK-LE: vinsdrx 1, 2, 3 # encoding: [0xcf,0x1b,0x22,0x10] # CHECK-LE: vinsdrx 1, 2, 3 # encoding: [0xcf,0x1b,0x22,0x10]
vinsdrx 1, 2, 3 vinsdrx 1, 2, 3
# CHECK-BE: vextdubvlx 1, 2, 3, 3 # encoding: [0x10,0x22,0x18,0xd8]
# CHECK-LE: vextdubvlx 1, 2, 3, 3 # encoding: [0xd8,0x18,0x22,0x10]
vextdubvlx 1, 2, 3, 3
# CHECK-BE: vextdubvrx 1, 2, 3, 3 # encoding: [0x10,0x22,0x18,0xd9]
# CHECK-LE: vextdubvrx 1, 2, 3, 3 # encoding: [0xd9,0x18,0x22,0x10]
vextdubvrx 1, 2, 3, 3
# CHECK-BE: vextduhvlx 1, 2, 3, 3 # encoding: [0x10,0x22,0x18,0xda]
# CHECK-LE: vextduhvlx 1, 2, 3, 3 # encoding: [0xda,0x18,0x22,0x10]
vextduhvlx 1, 2, 3, 3
# CHECK-BE: vextduhvrx 1, 2, 3, 3 # encoding: [0x10,0x22,0x18,0xdb]
# CHECK-LE: vextduhvrx 1, 2, 3, 3 # encoding: [0xdb,0x18,0x22,0x10]
vextduhvrx 1, 2, 3, 3
# CHECK-BE: vextduwvlx 1, 2, 3, 3 # encoding: [0x10,0x22,0x18,0xdc]
# CHECK-LE: vextduwvlx 1, 2, 3, 3 # encoding: [0xdc,0x18,0x22,0x10]
vextduwvlx 1, 2, 3, 3
# CHECK-BE: vextduwvrx 1, 2, 3, 3 # encoding: [0x10,0x22,0x18,0xdd]
# CHECK-LE: vextduwvrx 1, 2, 3, 3 # encoding: [0xdd,0x18,0x22,0x10]
vextduwvrx 1, 2, 3, 3
# CHECK-BE: vextddvlx 1, 2, 3, 3 # encoding: [0x10,0x22,0x18,0xde]
# CHECK-LE: vextddvlx 1, 2, 3, 3 # encoding: [0xde,0x18,0x22,0x10]
vextddvlx 1, 2, 3, 3
# CHECK-BE: vextddvrx 1, 2, 3, 3 # encoding: [0x10,0x22,0x18,0xdf]
# CHECK-LE: vextddvrx 1, 2, 3, 3 # encoding: [0xdf,0x18,0x22,0x10]
vextddvrx 1, 2, 3, 3
# CHECK-BE: lxvrbx 32, 1, 2 # encoding: [0x7c,0x01,0x10,0x1b] # CHECK-BE: lxvrbx 32, 1, 2 # encoding: [0x7c,0x01,0x10,0x1b]
# CHECK-LE: lxvrbx 32, 1, 2 # encoding: [0x1b,0x10,0x01,0x7c] # CHECK-LE: lxvrbx 32, 1, 2 # encoding: [0x1b,0x10,0x01,0x7c]
lxvrbx 32, 1, 2 lxvrbx 32, 1, 2
# CHECK-BE: lxvrhx 33, 1, 2 # encoding: [0x7c,0x21,0x10,0x5b] # CHECK-BE: lxvrhx 33, 1, 2 # encoding: [0x7c,0x21,0x10,0x5b]
# CHECK-LE: lxvrhx 33, 1, 2 # encoding: [0x5b,0x10,0x21,0x7c] # CHECK-LE: lxvrhx 33, 1, 2 # encoding: [0x5b,0x10,0x21,0x7c]
lxvrhx 33, 1, 2 lxvrhx 33, 1, 2
# CHECK-BE: lxvrdx 34, 1, 2 # encoding: [0x7c,0x41,0x10,0xdb] # CHECK-BE: lxvrdx 34, 1, 2 # encoding: [0x7c,0x41,0x10,0xdb]
# CHECK-LE: lxvrdx 34, 1, 2 # encoding: [0xdb,0x10,0x41,0x7c] # CHECK-LE: lxvrdx 34, 1, 2 # encoding: [0xdb,0x10,0x41,0x7c]
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