[ARM] Fix Asm/Disasm of TBB/TBH instructions

[DavidSpickett]

Summary

This fixes Bugzilla #46616 in which it was reported
that "tbb [pc, r0]" was marked as SoftFail
(aka unpredictable) incorrectly.

Expected behaviour is:

• ARMv8 is required to use sp as rn or rm (tbb/tbh only have a Thumb encoding so using Arm mode is not an option)
• If rm is the pc then the instruction is always unpredictable

Some of this was implemented already and this fixes the
rest. Added tests cover the new and pre-existing handling.

[DavidSpickett]

llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

10601

There is a similar register class "rGPR" but this also removes the PC, which is allowed here. Everything else that had a register like this tells you to use arm mode when you need SP, but tbb/tbh don't have arm encodings.

Seems like it would be a common thing but I couldn't find any other instructions like this.

[ostannard]

LGTM

llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

 //===- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions -------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
   case ARM::VMSR_VPR:
   case ARM::VMSR_P0:
     // Use of SP for VMRS/VMSR is only allowed in ARM mode with the exception of
     // ARMv8-A.
     if (Inst.getOperand(0).isReg() && Inst.getOperand(0).getReg() == ARM::SP &&
         (isThumb() && !hasV8Ops()))
       return Match_InvalidOperand;
     break;
+  case ARM::t2TBB:
+  case ARM::t2TBH:
+    // Rn = sp is only allowed with ARMv8-A
+    if (!hasV8Ops() && (Inst.getOperand(0).getReg() == ARM::SP))
+      return Match_RequiresV8;
+    break;
   default:
     break;
   }
 
   for (unsigned I = 0; I < MCID.NumOperands; ++I)
     if (MCID.OpInfo[I].RegClass == ARM::rGPRRegClassID) {
       // rGPRRegClass excludes PC, and also excluded SP before ARMv8
       const auto &Op = Inst.getOperand(I);

llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
 
   Inst.addOperand(MCOperand::createImm(Val));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus
 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
                        uint64_t Address, const void *Decoder) {
+  const FeatureBitset &FeatureBits =
+    ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
 
-  if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
+  if (Rn == 13 && !FeatureBits[ARM::HasV8Ops]) S = MCDisassembler::SoftFail;
   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
     return MCDisassembler::Fail;
   return S;
 }
 
 static DecodeStatus

llvm/test/MC/ARM/thumb2-diagnostics.s

 @ CHECK-ERRORS-V7: operand must be a register in range [r0, r12] or r14
 
         teq sp, #5
         teq sp, r7
         teq sp, r9, lsl #2
 @ CHECK-ERRORS-V7: error: operand must be a register in range [r0, r12] or r14
 @ CHECK-ERRORS-V7: operand must be a register in range [r0, r12] or r14
 @ CHECK-ERRORS-V7: operand must be a register in range [r0, r12] or r14
+
+        tbb [r0, sp]
+        @ v8 allows rm = sp
+@ CHECK-ERRORS-V7: error: instruction variant requires ARMv8 or later
+        tbb [r0, pc]
+        @ rm = pc is always unpredictable
+@ CHECK-ERRORS: error: invalid operand for instruction
+        tbb [sp, r0]
+        @ v8 allows rn = sp
+@ CHECK-ERRORS-V7: error: instruction variant requires ARMv8 or later
+        @ rn = pc is allowed so not included here
+
+        tbh [r0, sp, lsl #1]
+        @ v8 allows rm = sp
+@ CHECK-ERRORS-V7: error: instruction variant requires ARMv8 or later
+        tbh [r0, pc, lsl #1]
+        @ rm = pc is always unpredictable
+@ CHECK-ERRORS: error: invalid operand for instruction
+        tbh [sp, r0, lsl #1]
+        @ v8 allows rn = sp
+@ CHECK-ERRORS-V7: error: instruction variant requires ARMv8 or later
+        @ rn=pc is allowed so not included here

llvm/test/MC/Disassembler/ARM/thumb2-diagnostic.txt

+# RUN: llvm-mc -triple=thumbv7 -disassemble %s 2>&1 | \
+# RUN: FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V7
+# RUN: llvm-mc -triple=thumbv8 -disassemble %s 2>&1 | \
+# RUN: FileCheck %s --check-prefix=CHECK
+
+# tbb [r0, sp]
+0xd0 0xe8 0x0d 0xf0
+#      CHECK-V7: warning: potentially undefined instruction encoding
+# CHECK-V7-NEXT: 0xd0 0xe8 0x0d 0xf0
+
+# tbb [r0, pc]
+0xd0 0xe8 0x0f 0xf0
+#      CHECK: warning: potentially undefined instruction encoding
+# CHECK-NEXT: 0xd0 0xe8 0x0f 0xf0
+
+# tbb [sp, r0]
+0xdd 0xe8 0x00 0xf0
+#      CHECK-V7: warning: potentially undefined instruction encoding
+# CHECK-V7-NEXT: 0xdd 0xe8 0x00 0xf0
+
+# tbb [pc, r0]
+0xdf 0xe8 0x00 0xf0
+
+# tbh [r0, sp, lsl #1]
+0xd0 0xe8 0x1d 0xf0
+#      CHECK-V7: warning: potentially undefined instruction encoding
+# CHECK-V7-NEXT: 0xd0 0xe8 0x1d 0xf0
+
+# tbh [r0, pc, lsl #1]
+0xd0 0xe8 0x1f 0xf0
+#      CHECK: warning: potentially undefined instruction encoding
+# CHECK-NEXT: 0xd0 0xe8 0x1f 0xf0
+
+# tbh [sp, r0, lsl #1]
+0xdd 0xe8 0x10 0xf0
+#      CHECK-V7: warning: potentially undefined instruction encoding
+# CHECK-V7-NEXT: 0xdd 0xe8 0x10 0xf0
+
+# tbh [pc, r0, lsl #1]
+0xdf 0xe8 0x10 0xf0
+
+# CHECK: tbb [r0, sp]
+# CHECK: tbb [r0, pc]
+# CHECK: tbb [sp, r0]
+# CHECK: tbb [pc, r0]
+# CHECK: tbh [r0, sp, lsl #1]
+# CHECK: tbh [r0, pc, lsl #1]
+# CHECK: tbh [sp, r0, lsl #1]
+# CHECK: tbh [pc, r0, lsl #1]