[PowerPC] Fix wrong codegen when stack pointer has to realign performing dynalloc

[lkail]

Summary

Current powerpc backend generates wrong code sequence if stack pointer has to realign if -fstack-clash-protection enabled. When probing dynamic stack allocation, current PREPARE_PROBED_ALLOCA takes NegSizeReg as input and returns FinalStackPtr. FinalStackPtr=StackPtr+ActualNegSize is calculated correctly, however code following PREPARE_PROBED_ALLOCA still uses value of NegSizeReg, which does not contain ActualNegSize if MaxAlign > TargetAlign, to calculate loop trip count and residual number of bytes.

This patch fixes https://bugs.llvm.org/show_bug.cgi?id=46759

[jsji]

@lkail Can we split HasBP && MaxAlign > 1 situation into another patch? Thanks.

[lkail]

Removed fix of wrong codegen in prologue, will post another patch to fix.

[jsji]

LGTM with some nits.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

11962

KillNegSizeReg only used once, I think we can inline it here. Also add some comments or move By introducing PREPARE_PROBED_ALLOCA_NEGSIZE_OPT... up here.

11975

Maybe rename PREPARE_PROBED_ALLOCA_NEGSIZE_OPT_64 to something like PREPARE_PROBED_ALLOCA_SAME_REG

11978

Maybe we can common up these .add..

[lkail]

This comment was removed by lkail.

[lkail]

Simplified code according to @jsji 's comments.

[hans]

Was I cc'd because you want this cherry-picked to the 11.x branch?

[lkail]

In D84152#2166787, @hans wrote:

Was I cc'd because you want this cherry-picked to the 11.x branch?

Yes. Together with https://reviews.llvm.org/D84218. Thanks, Hans.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

PPCTargetLowering::emitProbedAlloca(MachineInstr &MI,
   const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
   const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
 
   Register DstReg = MI.getOperand(0).getReg();
   Register NegSizeReg = MI.getOperand(1).getReg();
   Register SPReg = isPPC64 ? PPC::X1 : PPC::R1;
   Register FinalStackPtr = MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC);
   Register FramePointer = MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC);
+  Register ActualNegSizeReg = MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC);
 
-  // Get the canonical FinalStackPtr like what
-  // PPCRegisterInfo::lowerDynamicAlloc does.
-  BuildMI(*MBB, {MI}, DL,
-          TII->get(isPPC64 ? PPC::PREPARE_PROBED_ALLOCA_64
-                           : PPC::PREPARE_PROBED_ALLOCA_32),
-          FramePointer)
-      .addDef(FinalStackPtr)
+  // Since value of NegSizeReg might be realigned in prologepilog, insert a
+  // PREPARE_PROBED_ALLOCA pseudo instruction to get actual FramePointer and
+  // NegSize.
+  unsigned ProbeOpc;
+  if (!MRI.hasOneNonDBGUse(NegSizeReg))
+    ProbeOpc =
+        isPPC64 ? PPC::PREPARE_PROBED_ALLOCA_64 : PPC::PREPARE_PROBED_ALLOCA_32;
+  else
+    // By introducing PREPARE_PROBED_ALLOCA_NEGSIZE_OPT, ActualNegSizeReg
+    // and NegSizeReg will be allocated in the same phyreg to avoid
+    // redundant copy when NegSizeReg has only one use which is current MI and
+    // will be replaced by PREPARE_PROBED_ALLOCA then.
+    ProbeOpc = isPPC64 ? PPC::PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64
+                       : PPC::PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32;
+  BuildMI(*MBB, {MI}, DL, TII->get(ProbeOpc), FramePointer)
+      .addDef(ActualNegSizeReg)
       .addReg(NegSizeReg)
       .add(MI.getOperand(2))
       .add(MI.getOperand(3));
 
+  // Calculate final stack pointer, which equals to SP + ActualNegSize.
+  BuildMI(*MBB, {MI}, DL, TII->get(isPPC64 ? PPC::ADD8 : PPC::ADD4),
+          FinalStackPtr)
+      .addReg(SPReg)
+      .addReg(ActualNegSizeReg);
+
   // Materialize a scratch register for update.
   int64_t NegProbeSize = -(int64_t)ProbeSize;
   assert(isInt<32>(NegProbeSize) && "Unhandled probe size!");
   Register ScratchReg = MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC);
   if (!isInt<16>(NegProbeSize)) {
     Register TempReg = MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC);
     BuildMI(*MBB, {MI}, DL, TII->get(isPPC64 ? PPC::LIS8 : PPC::LIS), TempReg)
         .addImm(NegProbeSize >> 16);
     BuildMI(*MBB, {MI}, DL, TII->get(isPPC64 ? PPC::ORI8 : PPC::ORI),
             ScratchReg)
         .addReg(TempReg)
         .addImm(NegProbeSize & 0xFFFF);
   } else
     BuildMI(*MBB, {MI}, DL, TII->get(isPPC64 ? PPC::LI8 : PPC::LI), ScratchReg)
         .addImm(NegProbeSize);
 
   {
     // Probing leading residual part.
     Register Div = MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC);
     BuildMI(*MBB, {MI}, DL, TII->get(isPPC64 ? PPC::DIVD : PPC::DIVW), Div)
-        .addReg(NegSizeReg)
+        .addReg(ActualNegSizeReg)
         .addReg(ScratchReg);
     Register Mul = MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC);
     BuildMI(*MBB, {MI}, DL, TII->get(isPPC64 ? PPC::MULLD : PPC::MULLW), Mul)
         .addReg(Div)
         .addReg(ScratchReg);
     Register NegMod = MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC);
     BuildMI(*MBB, {MI}, DL, TII->get(isPPC64 ? PPC::SUBF8 : PPC::SUBF), NegMod)
         .addReg(Mul)
-        .addReg(NegSizeReg);
+        .addReg(ActualNegSizeReg);
     BuildMI(*MBB, {MI}, DL, TII->get(isPPC64 ? PPC::STDUX : PPC::STWUX), SPReg)
         .addReg(FramePointer)
         .addReg(SPReg)
         .addReg(NegMod);
   }
 
   {
     // Remaining part should be multiple of ProbeSize.

llvm/lib/Target/PowerPC/PPCInstr64Bit.td

 def DYNAREAOFFSET8 : PPCEmitTimePseudo<(outs i64imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET8",
                        [(set i64:$result, (PPCdynareaoffset iaddr:$fpsi))]>;
 // Probed alloca to support stack clash protection.
 let Defs = [X1], Uses = [X1], hasNoSchedulingInfo = 1 in {
 def PROBED_ALLOCA_64 : PPCCustomInserterPseudo<(outs g8rc:$result),
                          (ins g8rc:$negsize, memri:$fpsi), "#PROBED_ALLOCA_64",
                            [(set i64:$result,
                              (PPCprobedalloca i64:$negsize, iaddr:$fpsi))]>;
-def PREPARE_PROBED_ALLOCA_64 : PPCEmitTimePseudo<(outs g8rc:$fp,
-    g8rc:$sp),
+def PREPARE_PROBED_ALLOCA_64 : PPCEmitTimePseudo<(outs
+    g8rc:$fp, g8rc:$actual_negsize),
     (ins g8rc:$negsize, memri:$fpsi), "#PREPARE_PROBED_ALLOCA_64", []>;
+def PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64 : PPCEmitTimePseudo<(outs
+    g8rc:$fp, g8rc:$actual_negsize),
+    (ins g8rc:$negsize, memri:$fpsi),
+    "#PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64", []>,
+    RegConstraint<"$actual_negsize = $negsize">;
 def PROBED_STACKALLOC_64 : PPCEmitTimePseudo<(outs g8rc:$scratch, g8rc:$temp),
     (ins i64imm:$stacksize),
     "#PROBED_STACKALLOC_64", []>;
 }
 
 let hasSideEffects = 0 in {
 let Defs = [LR8] in {
 def MTLR8  : XFXForm_7_ext<31, 467, 8, (outs), (ins g8rc:$rS),

llvm/lib/Target/PowerPC/PPCInstrInfo.td

 def DYNAREAOFFSET : PPCEmitTimePseudo<(outs i32imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET",
                        [(set i32:$result, (PPCdynareaoffset iaddr:$fpsi))]>;
 // Probed alloca to support stack clash protection.
 let Defs = [R1], Uses = [R1], hasNoSchedulingInfo = 1 in {
 def PROBED_ALLOCA_32 : PPCCustomInserterPseudo<(outs gprc:$result),
                          (ins gprc:$negsize, memri:$fpsi), "#PROBED_ALLOCA_32",
                            [(set i32:$result,
                              (PPCprobedalloca i32:$negsize, iaddr:$fpsi))]>;
-def PREPARE_PROBED_ALLOCA_32 : PPCEmitTimePseudo<(outs gprc:$fp,
-    gprc:$sp),
+def PREPARE_PROBED_ALLOCA_32 : PPCEmitTimePseudo<(outs
+    gprc:$fp, gprc:$actual_negsize),
     (ins gprc:$negsize, memri:$fpsi), "#PREPARE_PROBED_ALLOCA_32", []>;
+def PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32 : PPCEmitTimePseudo<(outs
+    gprc:$fp, gprc:$actual_negsize),
+    (ins gprc:$negsize, memri:$fpsi),
+    "#PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32", []>,
+    RegConstraint<"$actual_negsize = $negsize">;
 def PROBED_STACKALLOC_32 : PPCEmitTimePseudo<(outs gprc:$scratch, gprc:$temp),
     (ins i64imm:$stacksize),
     "#PROBED_STACKALLOC_32", []>;
 }
 
 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation.  Expanded after
 // instruction selection into a branch sequence.
 let PPC970_Single = 1 in {

llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

void PPCRegisterInfo::lowerPrepareProbedAlloca(
   MachineFunction &MF = *MBB.getParent();
   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
   // Get the instruction info.
   const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
   // Determine whether 64-bit pointers are used.
   bool LP64 = TM.isPPC64();
   DebugLoc dl = MI.getDebugLoc();
   Register FramePointer = MI.getOperand(0).getReg();
-  Register FinalStackPtr = MI.getOperand(1).getReg();
+  const Register ActualNegSizeReg = MI.getOperand(1).getReg();
   bool KillNegSizeReg = MI.getOperand(2).isKill();
   Register NegSizeReg = MI.getOperand(2).getReg();
-  prepareDynamicAlloca(II, NegSizeReg, KillNegSizeReg, FramePointer);
-  if (LP64) {
-    BuildMI(MBB, II, dl, TII.get(PPC::ADD8), FinalStackPtr)
-        .addReg(PPC::X1)
-        .addReg(NegSizeReg, getKillRegState(KillNegSizeReg));
-
-  } else {
-    BuildMI(MBB, II, dl, TII.get(PPC::ADD4), FinalStackPtr)
-        .addReg(PPC::R1)
-        .addReg(NegSizeReg, getKillRegState(KillNegSizeReg));
+  const MCInstrDesc &CopyInst = TII.get(LP64 ? PPC::OR8 : PPC::OR);
+  // RegAllocator might allocate FramePointer and NegSizeReg in the same phyreg.
+  if (FramePointer == NegSizeReg) {
+    assert(KillNegSizeReg && "FramePointer is a def and NegSizeReg is an use, "
+                             "NegSizeReg should be killed");
+    // FramePointer is clobbered earlier than the use of NegSizeReg in
+    // prepareDynamicAlloca, save NegSizeReg in ActualNegSizeReg to avoid
+    // misuse.
+    BuildMI(MBB, II, dl, CopyInst, ActualNegSizeReg)
+        .addReg(NegSizeReg)
+        .addReg(NegSizeReg);
+    NegSizeReg = ActualNegSizeReg;
+    KillNegSizeReg = false;
   }
-
+  prepareDynamicAlloca(II, NegSizeReg, KillNegSizeReg, FramePointer);
+  // NegSizeReg might be updated in prepareDynamicAlloca if MaxAlign >
+  // TargetAlign.
+  if (NegSizeReg != ActualNegSizeReg)
+    BuildMI(MBB, II, dl, CopyInst, ActualNegSizeReg)
+        .addReg(NegSizeReg)
+        .addReg(NegSizeReg);
   MBB.erase(II);
 }
 
 void PPCRegisterInfo::lowerDynamicAreaOffset(
     MachineBasicBlock::iterator II) const {
   // Get the instruction.
   MachineInstr &MI = *II;
   // Get the instruction's basic block.
PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
   if (FPSI && FrameIndex == FPSI &&
       (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) {
     lowerDynamicAlloc(II);
     return;
   }
 
   if (FPSI && FrameIndex == FPSI &&
       (OpC == PPC::PREPARE_PROBED_ALLOCA_64 ||
-       OpC == PPC::PREPARE_PROBED_ALLOCA_32)) {
+       OpC == PPC::PREPARE_PROBED_ALLOCA_32 ||
+       OpC == PPC::PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64 ||
+       OpC == PPC::PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32)) {
     lowerPrepareProbedAlloca(II);
     return;
   }
 
   // Special case for pseudo-ops SPILL_CR and RESTORE_CR, etc.
   if (OpC == PPC::SPILL_CR) {
     lowerCRSpilling(II, FrameIndex);
     return;

llvm/test/CodeGen/PowerPC/pr46759.ll

 ; CHECK-LE-NEXT:    subc r1, r1, r0
 ; CHECK-LE-NEXT:    stdu r12, -2048(r1)
 ; CHECK-LE-NEXT:    stdu r12, -4096(r1)
 ; CHECK-LE-NEXT:    .cfi_def_cfa_register r1
 ; CHECK-LE-NEXT:    .cfi_def_cfa_register r30
 ; CHECK-LE-NEXT:    .cfi_offset r31, -8
 ; CHECK-LE-NEXT:    .cfi_offset r30, -16
 ; CHECK-LE-NEXT:    clrldi r3, r3, 32
-; CHECK-LE-NEXT:    li r6, -4096
-; CHECK-LE-NEXT:    ld r4, 0(r1)
+; CHECK-LE-NEXT:    li r5, -2048
 ; CHECK-LE-NEXT:    mr r31, r1
 ; CHECK-LE-NEXT:    addi r3, r3, 15
 ; CHECK-LE-NEXT:    rldicl r3, r3, 60, 4
 ; CHECK-LE-NEXT:    rldicl r3, r3, 4, 31
-; CHECK-LE-NEXT:    neg r5, r3
-; CHECK-LE-NEXT:    li r3, -2048
-; CHECK-LE-NEXT:    divd r7, r5, r6
-; CHECK-LE-NEXT:    and r3, r5, r3
-; CHECK-LE-NEXT:    add r3, r1, r3
-; CHECK-LE-NEXT:    mulld r6, r7, r6
-; CHECK-LE-NEXT:    sub r5, r5, r6
-; CHECK-LE-NEXT:    stdux r4, r1, r5
-; CHECK-LE-NEXT:    cmpd r1, r3
+; CHECK-LE-NEXT:    neg r4, r3
+; CHECK-LE-NEXT:    ld r3, 0(r1)
+; CHECK-LE-NEXT:    and r5, r4, r5
+; CHECK-LE-NEXT:    mr r4, r5
+; CHECK-LE-NEXT:    li r5, -4096
+; CHECK-LE-NEXT:    divd r6, r4, r5
+; CHECK-LE-NEXT:    mulld r5, r6, r5
+; CHECK-LE-NEXT:    sub r5, r4, r5
+; CHECK-LE-NEXT:    add r4, r1, r4
+; CHECK-LE-NEXT:    stdux r3, r1, r5
+; CHECK-LE-NEXT:    cmpd r1, r4
 ; CHECK-LE-NEXT:    beq cr0, .LBB0_2
 ; CHECK-LE-NEXT:  .LBB0_1: # %entry
 ; CHECK-LE-NEXT:    #
-; CHECK-LE-NEXT:    stdu r4, -4096(r1)
-; CHECK-LE-NEXT:    cmpd r1, r3
+; CHECK-LE-NEXT:    stdu r3, -4096(r1)
+; CHECK-LE-NEXT:    cmpd r1, r4
 ; CHECK-LE-NEXT:    bne cr0, .LBB0_1
 ; CHECK-LE-NEXT:  .LBB0_2: # %entry
 ; CHECK-LE-NEXT:    addi r3, r1, 2048
 ; CHECK-LE-NEXT:    lbz r3, 0(r3)
 ; CHECK-LE-NEXT:    ld r1, 0(r1)
 ; CHECK-LE-NEXT:    ld r31, -8(r1)
 ; CHECK-LE-NEXT:    ld r30, -16(r1)
 ; CHECK-LE-NEXT:    blr
 entry:
   %0 = zext i32 %vla_size to i64
   %vla = alloca i8, i64 %0, align 2048
   %1 = load volatile i8, i8* %vla, align 2048
   ret void
 }
 
 attributes #0 = { "probe-stack"="inline-asm" }

llvm/test/CodeGen/PowerPC/stack-clash-dynamic-alloca.ll

 ; RUN:   -check-prefix=CHECK-32 %s
 
 define i32 @foo(i32 %n) local_unnamed_addr #0 "stack-probe-size"="32768" nounwind {
 ; CHECK-LE-LABEL: foo:
 ; CHECK-LE:       # %bb.0:
 ; CHECK-LE-NEXT:    std r31, -8(r1)
 ; CHECK-LE-NEXT:    stdu r1, -48(r1)
 ; CHECK-LE-NEXT:    rldic r3, r3, 2, 30
-; CHECK-LE-NEXT:    li r6, -32768
+; CHECK-LE-NEXT:    li r5, -32768
 ; CHECK-LE-NEXT:    mr r31, r1
 ; CHECK-LE-NEXT:    addi r3, r3, 15
-; CHECK-LE-NEXT:    addi r4, r31, 48
 ; CHECK-LE-NEXT:    rldicl r3, r3, 60, 4
 ; CHECK-LE-NEXT:    rldicl r3, r3, 4, 29
-; CHECK-LE-NEXT:    neg r5, r3
-; CHECK-LE-NEXT:    divd r7, r5, r6
-; CHECK-LE-NEXT:    add r3, r1, r5
-; CHECK-LE-NEXT:    mulld r6, r7, r6
-; CHECK-LE-NEXT:    sub r5, r5, r6
-; CHECK-LE-NEXT:    stdux r4, r1, r5
-; CHECK-LE-NEXT:    cmpd r1, r3
+; CHECK-LE-NEXT:    neg r4, r3
+; CHECK-LE-NEXT:    addi r3, r31, 48
+; CHECK-LE-NEXT:    divd r6, r4, r5
+; CHECK-LE-NEXT:    mulld r5, r6, r5
+; CHECK-LE-NEXT:    sub r5, r4, r5
+; CHECK-LE-NEXT:    add r4, r1, r4
+; CHECK-LE-NEXT:    stdux r3, r1, r5
+; CHECK-LE-NEXT:    cmpd r1, r4
 ; CHECK-LE-NEXT:    beq cr0, .LBB0_2
 ; CHECK-LE-NEXT:  .LBB0_1:
-; CHECK-LE-NEXT:    stdu r4, -32768(r1)
-; CHECK-LE-NEXT:    cmpd r1, r3
+; CHECK-LE-NEXT:    stdu r3, -32768(r1)
+; CHECK-LE-NEXT:    cmpd r1, r4
 ; CHECK-LE-NEXT:    bne cr0, .LBB0_1
 ; CHECK-LE-NEXT:  .LBB0_2:
 ; CHECK-LE-NEXT:    li r4, 1
 ; CHECK-LE-NEXT:    addi r3, r1, 32
 ; CHECK-LE-NEXT:    stw r4, 4792(r3)
 ; CHECK-LE-NEXT:    lwz r3, 0(r3)
 ; CHECK-LE-NEXT:    ld r1, 0(r1)
 ; CHECK-LE-NEXT:    ld r31, -8(r1)
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-P9-LE-LABEL: foo:
 ; CHECK-P9-LE:       # %bb.0:
 ; CHECK-P9-LE-NEXT:    std r31, -8(r1)
 ; CHECK-P9-LE-NEXT:    stdu r1, -48(r1)
 ; CHECK-P9-LE-NEXT:    rldic r3, r3, 2, 30
 ; CHECK-P9-LE-NEXT:    addi r3, r3, 15
 ; CHECK-P9-LE-NEXT:    li r6, -32768
 ; CHECK-P9-LE-NEXT:    mr r31, r1
-; CHECK-P9-LE-NEXT:    addi r4, r31, 48
 ; CHECK-P9-LE-NEXT:    rldicl r3, r3, 60, 4
 ; CHECK-P9-LE-NEXT:    rldicl r3, r3, 4, 29
 ; CHECK-P9-LE-NEXT:    neg r5, r3
+; CHECK-P9-LE-NEXT:    addi r3, r31, 48
 ; CHECK-P9-LE-NEXT:    divd r7, r5, r6
-; CHECK-P9-LE-NEXT:    add r3, r1, r5
+; CHECK-P9-LE-NEXT:    add r4, r1, r5
 ; CHECK-P9-LE-NEXT:    mulld r6, r7, r6
 ; CHECK-P9-LE-NEXT:    sub r5, r5, r6
-; CHECK-P9-LE-NEXT:    stdux r4, r1, r5
-; CHECK-P9-LE-NEXT:    cmpd r1, r3
+; CHECK-P9-LE-NEXT:    stdux r3, r1, r5
+; CHECK-P9-LE-NEXT:    cmpd r1, r4
 ; CHECK-P9-LE-NEXT:    beq cr0, .LBB0_2
 ; CHECK-P9-LE-NEXT:  .LBB0_1:
-; CHECK-P9-LE-NEXT:    stdu r4, -32768(r1)
-; CHECK-P9-LE-NEXT:    cmpd r1, r3
+; CHECK-P9-LE-NEXT:    stdu r3, -32768(r1)
+; CHECK-P9-LE-NEXT:    cmpd r1, r4
 ; CHECK-P9-LE-NEXT:    bne cr0, .LBB0_1
 ; CHECK-P9-LE-NEXT:  .LBB0_2:
 ; CHECK-P9-LE-NEXT:    li r4, 1
 ; CHECK-P9-LE-NEXT:    addi r3, r1, 32
 ; CHECK-P9-LE-NEXT:    stw r4, 4792(r3)
 ; CHECK-P9-LE-NEXT:    lwz r3, 0(r3)
 ; CHECK-P9-LE-NEXT:    ld r1, 0(r1)
 ; CHECK-P9-LE-NEXT:    ld r31, -8(r1)
 ; CHECK-P9-LE-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: foo:
 ; CHECK-BE:       # %bb.0:
 ; CHECK-BE-NEXT:    std r31, -8(r1)
 ; CHECK-BE-NEXT:    stdu r1, -64(r1)
 ; CHECK-BE-NEXT:    rldic r3, r3, 2, 30
-; CHECK-BE-NEXT:    li r6, -32768
+; CHECK-BE-NEXT:    li r5, -32768
 ; CHECK-BE-NEXT:    addi r3, r3, 15
 ; CHECK-BE-NEXT:    rldicl r3, r3, 60, 4
 ; CHECK-BE-NEXT:    mr r31, r1
 ; CHECK-BE-NEXT:    rldicl r3, r3, 4, 29
-; CHECK-BE-NEXT:    addi r4, r31, 64
-; CHECK-BE-NEXT:    neg r5, r3
-; CHECK-BE-NEXT:    divd r7, r5, r6
-; CHECK-BE-NEXT:    add r3, r1, r5
-; CHECK-BE-NEXT:    mulld r6, r7, r6
-; CHECK-BE-NEXT:    sub r5, r5, r6
-; CHECK-BE-NEXT:    stdux r4, r1, r5
-; CHECK-BE-NEXT:    cmpd r1, r3
+; CHECK-BE-NEXT:    neg r4, r3
+; CHECK-BE-NEXT:    divd r6, r4, r5
+; CHECK-BE-NEXT:    addi r3, r31, 64
+; CHECK-BE-NEXT:    mulld r5, r6, r5
+; CHECK-BE-NEXT:    sub r5, r4, r5
+; CHECK-BE-NEXT:    add r4, r1, r4
+; CHECK-BE-NEXT:    stdux r3, r1, r5
+; CHECK-BE-NEXT:    cmpd r1, r4
 ; CHECK-BE-NEXT:    beq cr0, .LBB0_2
 ; CHECK-BE-NEXT:  .LBB0_1:
-; CHECK-BE-NEXT:    stdu r4, -32768(r1)
-; CHECK-BE-NEXT:    cmpd r1, r3
+; CHECK-BE-NEXT:    stdu r3, -32768(r1)
+; CHECK-BE-NEXT:    cmpd r1, r4
 ; CHECK-BE-NEXT:    bne cr0, .LBB0_1
 ; CHECK-BE-NEXT:  .LBB0_2:
 ; CHECK-BE-NEXT:    li r4, 1
 ; CHECK-BE-NEXT:    addi r3, r1, 48
 ; CHECK-BE-NEXT:    stw r4, 4792(r3)
 ; CHECK-BE-NEXT:    lwz r3, 0(r3)
 ; CHECK-BE-NEXT:    ld r1, 0(r1)
 ; CHECK-BE-NEXT:    ld r31, -8(r1)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-32-LABEL: foo:
 ; CHECK-32:       # %bb.0:
 ; CHECK-32-NEXT:    stwu r1, -32(r1)
 ; CHECK-32-NEXT:    slwi r3, r3, 2
 ; CHECK-32-NEXT:    addi r3, r3, 15
 ; CHECK-32-NEXT:    rlwinm r3, r3, 0, 0, 27
-; CHECK-32-NEXT:    neg r5, r3
-; CHECK-32-NEXT:    li r6, -32768
-; CHECK-32-NEXT:    divw r7, r5, r6
+; CHECK-32-NEXT:    neg r4, r3
+; CHECK-32-NEXT:    li r5, -32768
+; CHECK-32-NEXT:    divw r6, r4, r5
 ; CHECK-32-NEXT:    stw r31, 28(r1)
 ; CHECK-32-NEXT:    mr r31, r1
-; CHECK-32-NEXT:    addi r4, r31, 32
-; CHECK-32-NEXT:    add r3, r1, r5
-; CHECK-32-NEXT:    mullw r6, r7, r6
-; CHECK-32-NEXT:    sub r5, r5, r6
-; CHECK-32-NEXT:    stwux r4, r1, r5
-; CHECK-32-NEXT:    cmpw r1, r3
+; CHECK-32-NEXT:    addi r3, r31, 32
+; CHECK-32-NEXT:    mullw r5, r6, r5
+; CHECK-32-NEXT:    sub r5, r4, r5
+; CHECK-32-NEXT:    add r4, r1, r4
+; CHECK-32-NEXT:    stwux r3, r1, r5
+; CHECK-32-NEXT:    cmpw r1, r4
 ; CHECK-32-NEXT:    beq cr0, .LBB0_2
 ; CHECK-32-NEXT:  .LBB0_1:
-; CHECK-32-NEXT:    stwu r4, -32768(r1)
-; CHECK-32-NEXT:    cmpw r1, r3
+; CHECK-32-NEXT:    stwu r3, -32768(r1)
+; CHECK-32-NEXT:    cmpw r1, r4
 ; CHECK-32-NEXT:    bne cr0, .LBB0_1
 ; CHECK-32-NEXT:  .LBB0_2:
 ; CHECK-32-NEXT:    li r4, 1
 ; CHECK-32-NEXT:    addi r3, r1, 16
 ; CHECK-32-NEXT:    stw r4, 4792(r3)
 ; CHECK-32-NEXT:    lwz r3, 0(r3)
 ; CHECK-32-NEXT:    lwz r31, 0(r1)
 ; CHECK-32-NEXT:    lwz r0, -4(r31)
 ; CHECK-32-NEXT:    mr r1, r31
 ; CHECK-32-NEXT:    mr r31, r0
 ; CHECK-32-NEXT:    blr
   %a = alloca i32, i32 %n, align 16
   %b = getelementptr inbounds i32, i32* %a, i64 1198
   store volatile i32 1, i32* %b
   %c = load volatile i32, i32* %a
   ret i32 %c
 }
 
 define i32 @bar(i32 %n) local_unnamed_addr #0 nounwind {
 ; CHECK-LE-LABEL: bar:
 ; CHECK-LE:       # %bb.0:
 ; CHECK-LE-NEXT:    std r31, -8(r1)
 ; CHECK-LE-NEXT:    stdu r1, -48(r1)
 ; CHECK-LE-NEXT:    rldic r4, r3, 2, 30
-; CHECK-LE-NEXT:    li r7, -4096
+; CHECK-LE-NEXT:    li r6, -4096
 ; CHECK-LE-NEXT:    mr r31, r1
 ; CHECK-LE-NEXT:    addi r4, r4, 15
-; CHECK-LE-NEXT:    addi r5, r31, 48
 ; CHECK-LE-NEXT:    rldicl r4, r4, 60, 4
 ; CHECK-LE-NEXT:    rldicl r4, r4, 4, 29
-; CHECK-LE-NEXT:    neg r6, r4
-; CHECK-LE-NEXT:    divd r8, r6, r7
-; CHECK-LE-NEXT:    add r4, r1, r6
-; CHECK-LE-NEXT:    mulld r7, r8, r7
-; CHECK-LE-NEXT:    sub r6, r6, r7
-; CHECK-LE-NEXT:    stdux r5, r1, r6
-; CHECK-LE-NEXT:    cmpd r1, r4
+; CHECK-LE-NEXT:    neg r5, r4
+; CHECK-LE-NEXT:    addi r4, r31, 48
+; CHECK-LE-NEXT:    divd r7, r5, r6
+; CHECK-LE-NEXT:    mulld r6, r7, r6
+; CHECK-LE-NEXT:    sub r6, r5, r6
+; CHECK-LE-NEXT:    add r5, r1, r5
+; CHECK-LE-NEXT:    stdux r4, r1, r6
+; CHECK-LE-NEXT:    cmpd r1, r5
 ; CHECK-LE-NEXT:    beq cr0, .LBB1_2
 ; CHECK-LE-NEXT:  .LBB1_1:
-; CHECK-LE-NEXT:    stdu r5, -4096(r1)
-; CHECK-LE-NEXT:    cmpd r1, r4
+; CHECK-LE-NEXT:    stdu r4, -4096(r1)
+; CHECK-LE-NEXT:    cmpd r1, r5
 ; CHECK-LE-NEXT:    bne cr0, .LBB1_1
 ; CHECK-LE-NEXT:  .LBB1_2:
 ; CHECK-LE-NEXT:    extsw r3, r3
 ; CHECK-LE-NEXT:    li r5, 1
 ; CHECK-LE-NEXT:    addi r4, r1, 32
 ; CHECK-LE-NEXT:    sldi r3, r3, 2
 ; CHECK-LE-NEXT:    add r3, r4, r3
 ; CHECK-LE-NEXT:    stw r5, 4096(r3)
 ; CHECK-LE-NEXT:    lwz r3, 0(r4)
 ; CHECK-LE-NEXT:    ld r1, 0(r1)
 ; CHECK-LE-NEXT:    ld r31, -8(r1)
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-P9-LE-LABEL: bar:
 ; CHECK-P9-LE:       # %bb.0:
 ; CHECK-P9-LE-NEXT:    std r31, -8(r1)
 ; CHECK-P9-LE-NEXT:    stdu r1, -48(r1)
 ; CHECK-P9-LE-NEXT:    rldic r4, r3, 2, 30
 ; CHECK-P9-LE-NEXT:    addi r4, r4, 15
 ; CHECK-P9-LE-NEXT:    li r7, -4096
 ; CHECK-P9-LE-NEXT:    mr r31, r1
-; CHECK-P9-LE-NEXT:    addi r5, r31, 48
 ; CHECK-P9-LE-NEXT:    rldicl r4, r4, 60, 4
 ; CHECK-P9-LE-NEXT:    rldicl r4, r4, 4, 29
 ; CHECK-P9-LE-NEXT:    neg r6, r4
+; CHECK-P9-LE-NEXT:    addi r4, r31, 48
 ; CHECK-P9-LE-NEXT:    divd r8, r6, r7
-; CHECK-P9-LE-NEXT:    add r4, r1, r6
+; CHECK-P9-LE-NEXT:    add r5, r1, r6
 ; CHECK-P9-LE-NEXT:    mulld r7, r8, r7
 ; CHECK-P9-LE-NEXT:    sub r6, r6, r7
-; CHECK-P9-LE-NEXT:    stdux r5, r1, r6
-; CHECK-P9-LE-NEXT:    cmpd r1, r4
+; CHECK-P9-LE-NEXT:    stdux r4, r1, r6
+; CHECK-P9-LE-NEXT:    cmpd r1, r5
 ; CHECK-P9-LE-NEXT:    beq cr0, .LBB1_2
 ; CHECK-P9-LE-NEXT:  .LBB1_1:
-; CHECK-P9-LE-NEXT:    stdu r5, -4096(r1)
-; CHECK-P9-LE-NEXT:    cmpd r1, r4
+; CHECK-P9-LE-NEXT:    stdu r4, -4096(r1)
+; CHECK-P9-LE-NEXT:    cmpd r1, r5
 ; CHECK-P9-LE-NEXT:    bne cr0, .LBB1_1
 ; CHECK-P9-LE-NEXT:  .LBB1_2:
 ; CHECK-P9-LE-NEXT:    extswsli r3, r3, 2
 ; CHECK-P9-LE-NEXT:    li r5, 1
 ; CHECK-P9-LE-NEXT:    addi r4, r1, 32
 ; CHECK-P9-LE-NEXT:    add r3, r4, r3
 ; CHECK-P9-LE-NEXT:    stw r5, 4096(r3)
 ; CHECK-P9-LE-NEXT:    lwz r3, 0(r4)
 ; CHECK-P9-LE-NEXT:    ld r1, 0(r1)
 ; CHECK-P9-LE-NEXT:    ld r31, -8(r1)
 ; CHECK-P9-LE-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: bar:
 ; CHECK-BE:       # %bb.0:
 ; CHECK-BE-NEXT:    std r31, -8(r1)
 ; CHECK-BE-NEXT:    stdu r1, -64(r1)
 ; CHECK-BE-NEXT:    rldic r4, r3, 2, 30
-; CHECK-BE-NEXT:    li r7, -4096
+; CHECK-BE-NEXT:    li r6, -4096
 ; CHECK-BE-NEXT:    addi r4, r4, 15
 ; CHECK-BE-NEXT:    rldicl r4, r4, 60, 4
 ; CHECK-BE-NEXT:    mr r31, r1
 ; CHECK-BE-NEXT:    rldicl r4, r4, 4, 29
-; CHECK-BE-NEXT:    addi r5, r31, 64
-; CHECK-BE-NEXT:    neg r6, r4
-; CHECK-BE-NEXT:    divd r8, r6, r7
-; CHECK-BE-NEXT:    add r4, r1, r6
-; CHECK-BE-NEXT:    mulld r7, r8, r7
-; CHECK-BE-NEXT:    sub r6, r6, r7
-; CHECK-BE-NEXT:    stdux r5, r1, r6
-; CHECK-BE-NEXT:    cmpd r1, r4
+; CHECK-BE-NEXT:    neg r5, r4
+; CHECK-BE-NEXT:    divd r7, r5, r6
+; CHECK-BE-NEXT:    addi r4, r31, 64
+; CHECK-BE-NEXT:    mulld r6, r7, r6
+; CHECK-BE-NEXT:    sub r6, r5, r6
+; CHECK-BE-NEXT:    add r5, r1, r5
+; CHECK-BE-NEXT:    stdux r4, r1, r6
+; CHECK-BE-NEXT:    cmpd r1, r5
 ; CHECK-BE-NEXT:    beq cr0, .LBB1_2
 ; CHECK-BE-NEXT:  .LBB1_1:
-; CHECK-BE-NEXT:    stdu r5, -4096(r1)
-; CHECK-BE-NEXT:    cmpd r1, r4
+; CHECK-BE-NEXT:    stdu r4, -4096(r1)
+; CHECK-BE-NEXT:    cmpd r1, r5
 ; CHECK-BE-NEXT:    bne cr0, .LBB1_1
 ; CHECK-BE-NEXT:  .LBB1_2:
 ; CHECK-BE-NEXT:    extsw r3, r3
 ; CHECK-BE-NEXT:    addi r4, r1, 48
 ; CHECK-BE-NEXT:    sldi r3, r3, 2
 ; CHECK-BE-NEXT:    li r5, 1
 ; CHECK-BE-NEXT:    add r3, r4, r3
 ; CHECK-BE-NEXT:    stw r5, 4096(r3)
 ; CHECK-BE-NEXT:    lwz r3, 0(r4)
 ; CHECK-BE-NEXT:    ld r1, 0(r1)
 ; CHECK-BE-NEXT:    ld r31, -8(r1)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-32-LABEL: bar:
 ; CHECK-32:       # %bb.0:
 ; CHECK-32-NEXT:    stwu r1, -32(r1)
 ; CHECK-32-NEXT:    slwi r3, r3, 2
 ; CHECK-32-NEXT:    addi r4, r3, 15
 ; CHECK-32-NEXT:    rlwinm r4, r4, 0, 0, 27
-; CHECK-32-NEXT:    neg r6, r4
-; CHECK-32-NEXT:    li r7, -4096
-; CHECK-32-NEXT:    divw r8, r6, r7
+; CHECK-32-NEXT:    neg r5, r4
+; CHECK-32-NEXT:    li r6, -4096
+; CHECK-32-NEXT:    divw r7, r5, r6
 ; CHECK-32-NEXT:    stw r31, 28(r1)
 ; CHECK-32-NEXT:    mr r31, r1
-; CHECK-32-NEXT:    addi r5, r31, 32
-; CHECK-32-NEXT:    add r4, r1, r6
-; CHECK-32-NEXT:    mullw r7, r8, r7
-; CHECK-32-NEXT:    sub r6, r6, r7
-; CHECK-32-NEXT:    stwux r5, r1, r6
-; CHECK-32-NEXT:    cmpw r1, r4
+; CHECK-32-NEXT:    addi r4, r31, 32
+; CHECK-32-NEXT:    mullw r6, r7, r6
+; CHECK-32-NEXT:    sub r6, r5, r6
+; CHECK-32-NEXT:    add r5, r1, r5
+; CHECK-32-NEXT:    stwux r4, r1, r6
+; CHECK-32-NEXT:    cmpw r1, r5
 ; CHECK-32-NEXT:    beq cr0, .LBB1_2
 ; CHECK-32-NEXT:  .LBB1_1:
-; CHECK-32-NEXT:    stwu r5, -4096(r1)
-; CHECK-32-NEXT:    cmpw r1, r4
+; CHECK-32-NEXT:    stwu r4, -4096(r1)
+; CHECK-32-NEXT:    cmpw r1, r5
 ; CHECK-32-NEXT:    bne cr0, .LBB1_1
 ; CHECK-32-NEXT:  .LBB1_2:
 ; CHECK-32-NEXT:    addi r4, r1, 16
 ; CHECK-32-NEXT:    li r5, 1
 ; CHECK-32-NEXT:    add r3, r4, r3
 ; CHECK-32-NEXT:    stw r5, 4096(r3)
 ; CHECK-32-NEXT:    lwz r3, 0(r4)
 ; CHECK-32-NEXT:    lwz r31, 0(r1)

 }
 
 define i32 @f(i32 %n) local_unnamed_addr #0 "stack-probe-size"="65536" nounwind {
 ; CHECK-LE-LABEL: f:
 ; CHECK-LE:       # %bb.0:
 ; CHECK-LE-NEXT:    std r31, -8(r1)
 ; CHECK-LE-NEXT:    stdu r1, -48(r1)
 ; CHECK-LE-NEXT:    rldic r3, r3, 2, 30
-; CHECK-LE-NEXT:    lis r5, -1
+; CHECK-LE-NEXT:    lis r4, -1
 ; CHECK-LE-NEXT:    mr r31, r1
 ; CHECK-LE-NEXT:    addi r3, r3, 15
-; CHECK-LE-NEXT:    ori r5, r5, 0
-; CHECK-LE-NEXT:    addi r4, r31, 48
+; CHECK-LE-NEXT:    ori r4, r4, 0
 ; CHECK-LE-NEXT:    rldicl r3, r3, 60, 4
 ; CHECK-LE-NEXT:    rldicl r3, r3, 4, 29
-; CHECK-LE-NEXT:    neg r6, r3
-; CHECK-LE-NEXT:    divd r7, r6, r5
-; CHECK-LE-NEXT:    add r3, r1, r6
-; CHECK-LE-NEXT:    mulld r7, r7, r5
-; CHECK-LE-NEXT:    sub r6, r6, r7
-; CHECK-LE-NEXT:    stdux r4, r1, r6
-; CHECK-LE-NEXT:    cmpd r1, r3
+; CHECK-LE-NEXT:    neg r5, r3
+; CHECK-LE-NEXT:    addi r3, r31, 48
+; CHECK-LE-NEXT:    divd r6, r5, r4
+; CHECK-LE-NEXT:    mulld r6, r6, r4
+; CHECK-LE-NEXT:    sub r6, r5, r6
+; CHECK-LE-NEXT:    add r5, r1, r5
+; CHECK-LE-NEXT:    stdux r3, r1, r6
+; CHECK-LE-NEXT:    cmpd r1, r5
 ; CHECK-LE-NEXT:    beq cr0, .LBB2_2
 ; CHECK-LE-NEXT:  .LBB2_1:
-; CHECK-LE-NEXT:    stdux r4, r1, r5
-; CHECK-LE-NEXT:    cmpd r1, r3
+; CHECK-LE-NEXT:    stdux r3, r1, r4
+; CHECK-LE-NEXT:    cmpd r1, r5
 ; CHECK-LE-NEXT:    bne cr0, .LBB2_1
 ; CHECK-LE-NEXT:  .LBB2_2:
 ; CHECK-LE-NEXT:    li r4, 1
 ; CHECK-LE-NEXT:    addi r3, r1, 32
 ; CHECK-LE-NEXT:    stw r4, 4792(r3)
 ; CHECK-LE-NEXT:    lwz r3, 0(r3)
 ; CHECK-LE-NEXT:    ld r1, 0(r1)
 ; CHECK-LE-NEXT:    ld r31, -8(r1)
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-P9-LE-LABEL: f:
 ; CHECK-P9-LE:       # %bb.0:
 ; CHECK-P9-LE-NEXT:    std r31, -8(r1)
 ; CHECK-P9-LE-NEXT:    stdu r1, -48(r1)
 ; CHECK-P9-LE-NEXT:    rldic r3, r3, 2, 30
 ; CHECK-P9-LE-NEXT:    addi r3, r3, 15
 ; CHECK-P9-LE-NEXT:    lis r5, -1
 ; CHECK-P9-LE-NEXT:    ori r5, r5, 0
 ; CHECK-P9-LE-NEXT:    mr r31, r1
-; CHECK-P9-LE-NEXT:    addi r4, r31, 48
 ; CHECK-P9-LE-NEXT:    rldicl r3, r3, 60, 4
 ; CHECK-P9-LE-NEXT:    rldicl r3, r3, 4, 29
 ; CHECK-P9-LE-NEXT:    neg r6, r3
+; CHECK-P9-LE-NEXT:    addi r3, r31, 48
 ; CHECK-P9-LE-NEXT:    divd r7, r6, r5
-; CHECK-P9-LE-NEXT:    add r3, r1, r6
+; CHECK-P9-LE-NEXT:    add r4, r1, r6
 ; CHECK-P9-LE-NEXT:    mulld r7, r7, r5
 ; CHECK-P9-LE-NEXT:    sub r6, r6, r7
-; CHECK-P9-LE-NEXT:    stdux r4, r1, r6
-; CHECK-P9-LE-NEXT:    cmpd r1, r3
+; CHECK-P9-LE-NEXT:    stdux r3, r1, r6
+; CHECK-P9-LE-NEXT:    cmpd r1, r4
 ; CHECK-P9-LE-NEXT:    beq cr0, .LBB2_2
 ; CHECK-P9-LE-NEXT:  .LBB2_1:
-; CHECK-P9-LE-NEXT:    stdux r4, r1, r5
-; CHECK-P9-LE-NEXT:    cmpd r1, r3
+; CHECK-P9-LE-NEXT:    stdux r3, r1, r5
+; CHECK-P9-LE-NEXT:    cmpd r1, r4
 ; CHECK-P9-LE-NEXT:    bne cr0, .LBB2_1
 ; CHECK-P9-LE-NEXT:  .LBB2_2:
 ; CHECK-P9-LE-NEXT:    li r4, 1
 ; CHECK-P9-LE-NEXT:    addi r3, r1, 32
 ; CHECK-P9-LE-NEXT:    stw r4, 4792(r3)
 ; CHECK-P9-LE-NEXT:    lwz r3, 0(r3)
 ; CHECK-P9-LE-NEXT:    ld r1, 0(r1)
 ; CHECK-P9-LE-NEXT:    ld r31, -8(r1)
 ; CHECK-P9-LE-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: f:
 ; CHECK-BE:       # %bb.0:
 ; CHECK-BE-NEXT:    std r31, -8(r1)
 ; CHECK-BE-NEXT:    stdu r1, -64(r1)
 ; CHECK-BE-NEXT:    rldic r3, r3, 2, 30
-; CHECK-BE-NEXT:    lis r5, -1
+; CHECK-BE-NEXT:    lis r4, -1
 ; CHECK-BE-NEXT:    addi r3, r3, 15
 ; CHECK-BE-NEXT:    rldicl r3, r3, 60, 4
-; CHECK-BE-NEXT:    ori r5, r5, 0
+; CHECK-BE-NEXT:    ori r4, r4, 0
 ; CHECK-BE-NEXT:    rldicl r3, r3, 4, 29
 ; CHECK-BE-NEXT:    mr r31, r1
-; CHECK-BE-NEXT:    neg r6, r3
-; CHECK-BE-NEXT:    divd r7, r6, r5
-; CHECK-BE-NEXT:    addi r4, r31, 64
-; CHECK-BE-NEXT:    mulld r7, r7, r5
-; CHECK-BE-NEXT:    add r3, r1, r6
-; CHECK-BE-NEXT:    sub r6, r6, r7
-; CHECK-BE-NEXT:    stdux r4, r1, r6
-; CHECK-BE-NEXT:    cmpd r1, r3
+; CHECK-BE-NEXT:    neg r5, r3
+; CHECK-BE-NEXT:    divd r6, r5, r4
+; CHECK-BE-NEXT:    addi r3, r31, 64
+; CHECK-BE-NEXT:    mulld r6, r6, r4
+; CHECK-BE-NEXT:    sub r6, r5, r6
+; CHECK-BE-NEXT:    add r5, r1, r5
+; CHECK-BE-NEXT:    stdux r3, r1, r6
+; CHECK-BE-NEXT:    cmpd r1, r5
 ; CHECK-BE-NEXT:    beq cr0, .LBB2_2
 ; CHECK-BE-NEXT:  .LBB2_1:
-; CHECK-BE-NEXT:    stdux r4, r1, r5
-; CHECK-BE-NEXT:    cmpd r1, r3
+; CHECK-BE-NEXT:    stdux r3, r1, r4
+; CHECK-BE-NEXT:    cmpd r1, r5
 ; CHECK-BE-NEXT:    bne cr0, .LBB2_1
 ; CHECK-BE-NEXT:  .LBB2_2:
 ; CHECK-BE-NEXT:    li r4, 1
 ; CHECK-BE-NEXT:    addi r3, r1, 48
 ; CHECK-BE-NEXT:    stw r4, 4792(r3)
 ; CHECK-BE-NEXT:    lwz r3, 0(r3)
 ; CHECK-BE-NEXT:    ld r1, 0(r1)
 ; CHECK-BE-NEXT:    ld r31, -8(r1)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-32-LABEL: f:
 ; CHECK-32:       # %bb.0:
 ; CHECK-32-NEXT:    stwu r1, -32(r1)
 ; CHECK-32-NEXT:    slwi r3, r3, 2
 ; CHECK-32-NEXT:    addi r3, r3, 15
 ; CHECK-32-NEXT:    rlwinm r3, r3, 0, 0, 27
-; CHECK-32-NEXT:    lis r5, -1
-; CHECK-32-NEXT:    neg r6, r3
-; CHECK-32-NEXT:    ori r5, r5, 0
-; CHECK-32-NEXT:    divw r7, r6, r5
+; CHECK-32-NEXT:    lis r4, -1
+; CHECK-32-NEXT:    neg r5, r3
+; CHECK-32-NEXT:    ori r4, r4, 0
+; CHECK-32-NEXT:    divw r6, r5, r4
 ; CHECK-32-NEXT:    stw r31, 28(r1)
 ; CHECK-32-NEXT:    mr r31, r1
-; CHECK-32-NEXT:    addi r4, r31, 32
-; CHECK-32-NEXT:    add r3, r1, r6
-; CHECK-32-NEXT:    mullw r7, r7, r5
-; CHECK-32-NEXT:    sub r6, r6, r7
-; CHECK-32-NEXT:    stwux r4, r1, r6
-; CHECK-32-NEXT:    cmpw r1, r3
+; CHECK-32-NEXT:    addi r3, r31, 32
+; CHECK-32-NEXT:    mullw r6, r6, r4
+; CHECK-32-NEXT:    sub r6, r5, r6
+; CHECK-32-NEXT:    add r5, r1, r5
+; CHECK-32-NEXT:    stwux r3, r1, r6
+; CHECK-32-NEXT:    cmpw r1, r5
 ; CHECK-32-NEXT:    beq cr0, .LBB2_2
 ; CHECK-32-NEXT:  .LBB2_1:
-; CHECK-32-NEXT:    stwux r4, r1, r5
-; CHECK-32-NEXT:    cmpw r1, r3
+; CHECK-32-NEXT:    stwux r3, r1, r4
+; CHECK-32-NEXT:    cmpw r1, r5
 ; CHECK-32-NEXT:    bne cr0, .LBB2_1
 ; CHECK-32-NEXT:  .LBB2_2:
 ; CHECK-32-NEXT:    li r4, 1
 ; CHECK-32-NEXT:    addi r3, r1, 16
 ; CHECK-32-NEXT:    stw r4, 4792(r3)
 ; CHECK-32-NEXT:    lwz r3, 0(r3)
 ; CHECK-32-NEXT:    lwz r31, 0(r1)
 ; CHECK-32-NEXT:    lwz r0, -4(r31)