[GlobalISel][InlineAsm] Extend input operands when register class size does not match type

[gargaroff]

Summary

The InlineAsmLowering was blindly copying the input operands to the selected register class without checking if their sizes match. This resulted in illegal COPYs. Use G_ANYEXT to extend the input operand to fit the selected register class. G_ANYEXT ist used since the inline assembler is not allowed to assume anything about the upper bits of the input operands.

[gargaroff]

Forgot to commit final changes before diff

[arsenm]

llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp

537–539

Scratch reg and InputReg are the same thing. You can just use the type as the DstOp to buildAnyExt.

This may also be a problem for non-scalar sources. What if you have <2 x i4>?

[kschwarz]

A similar issue (for tied input operands) is handled in https://reviews.llvm.org/D83384
The function introduced there should be extended to handle the vector case.

[gargaroff]

In D83390#2140237, @kschwarz wrote:

A similar issue (for tied input operands) is handled in https://reviews.llvm.org/D83384
The function introduced there should be extended to handle the vector case.

In that case I'll hold off on this patch until the one you linked is landed. If that one will introduce the extension handling already, I'll abandon this patch.

[gargaroff]

I'll abandon this patch since this was committed in https://reviews.llvm.org/rGfd85b40aee4aa4cfcecaf2bfaf86e1de4c78ab0c

llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp

case InlineAsm::isInput: {
       if (NumRegs > 1) {
         LLVM_DEBUG(dbgs() << "Input operands with multiple input registers are "
                              "not supported yet\n");
         return false;
       }
 
       unsigned Flag = InlineAsm::getFlagWord(InlineAsm::Kind_RegUse, NumRegs);
       Inst.addImm(Flag);
-      MIRBuilder.buildCopy(OpInfo.Regs[0], SourceRegs[0]);
-      Inst.addReg(OpInfo.Regs[0]);
+
+      // We might need to extend the input registers to fit the register class
+      Register TargetReg = OpInfo.Regs[0];
+      Register InputReg = SourceRegs[0];
+
+      unsigned TargetSize = TRI->getRegSizeInBits(TargetReg, *MRI);
+      unsigned InputSize = MRI->getType(InputReg).getSizeInBits();
+
+      if (InputSize < TargetSize) {
+        Register ScratchReg =
+            MRI->createGenericVirtualRegister(LLT::scalar(TargetSize));
+        InputReg = MIRBuilder.buildAnyExt(ScratchReg, InputReg).getReg(0);
+      }
+
+      MIRBuilder.buildCopy(TargetReg, InputReg);
+      Inst.addReg(TargetReg);
       break;
     }
 
     case InlineAsm::isClobber: {
 
       unsigned NumRegs = OpInfo.Regs.size();
       if (NumRegs > 0) {
         unsigned Flag =

llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll

define zeroext i8 @test_input_register(i8* %src) nounwind {
   ; CHECK:   [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s8)
   ; CHECK:   $w0 = COPY [[ZEXT]](s32)
   ; CHECK:   RET_ReallyLR implicit $w0
 entry:
   %0 = tail call i8 asm "ldtrb ${0:w}, [$1]", "=r,r"(i8* %src) nounwind
   ret i8 %0
 }
 
+define void @test_input_register_extend() {
+  ; CHECK-LABEL: name: test_input_register_extend
+  ; CHECK: bb.1 (%ir-block.0):
+  ; CHECK:   [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 42
+  ; CHECK:   [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[C]](s8)
+  ; CHECK:   [[COPY:%[0-9]+]]:gpr32common = COPY [[ANYEXT]](s32)
+  ; CHECK:   INLINEASM &"mov x0, $0", 1 /* sideeffect attdialect */, 9 /* reguse */, [[COPY]]
+  ; CHECK:   RET_ReallyLR
+  call void asm sideeffect "mov x0, $0", "r"(i8 42)
+  ret void
+}
+
 define i32 @test_memory_constraint(i32* %a) nounwind {
   ; CHECK-LABEL: name: test_memory_constraint
   ; CHECK: bb.1 (%ir-block.0):
   ; CHECK:   liveins: $x0
   ; CHECK:   [[COPY:%[0-9]+]]:_(p0) = COPY $x0
   ; CHECK:   INLINEASM &"ldr $0, $1", 8 /* mayload attdialect */, 655370 /* regdef:GPR32common */, def %1, 196622 /* mem:m */, [[COPY]](p0)
   ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY %1
   ; CHECK:   $w0 = COPY [[COPY1]](s32)
   ; CHECK:   RET_ReallyLR implicit $w0
   %1 = tail call i32 asm "ldr $0, $1", "=r,*m"(i32* %a)
   ret i32 %1
 }