[ms] [llvm-ml] Add support for MASM STRUCT casting field accessors: (<TYPE> PTR <value>).<field>

[epastor]

Summary

Add support for MASM STRUCT casting field accessors: (<TYPE> PTR <value>).<field>

Since these are operands, we add them to X86AsmParser. If/when we extend MASM support to other architectures (e.g., ARM), we will need similar changes there as well.

[epastor]

Rebase on parent

[thakis]

llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp

1660

sentence case

llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp

enum IntelExprState {
     IES_OR,
     IES_XOR,
     IES_AND,
     IES_LSHIFT,
     IES_RSHIFT,
     IES_PLUS,
     IES_MINUS,
     IES_OFFSET,
+    IES_CAST,
     IES_NOT,
     IES_MULTIPLY,
     IES_DIVIDE,
     IES_MOD,
     IES_LBRAC,
     IES_RBRAC,
     IES_LPAREN,
     IES_RPAREN,
bool onIdentifierExpr(const MCExpr *SymRef, StringRef SymRefName,
       // Treat a symbolic constant like an integer
       if (auto *CE = dyn_cast<MCConstantExpr>(SymRef))
         return onInteger(CE->getValue(), ErrMsg);
       PrevState = State;
       switch (State) {
       default:
         State = IES_ERROR;
         break;
+      case IES_CAST:
       case IES_PLUS:
       case IES_MINUS:
       case IES_NOT:
       case IES_INIT:
       case IES_LBRAC:
         if (setSymRef(SymRef, SymRefName, ErrMsg))
           return true;
         MemExpr = true;
bool onLBrac() {
         break;
       case IES_RBRAC:
       case IES_INTEGER:
       case IES_RPAREN:
         State = IES_PLUS;
         IC.pushOperator(IC_PLUS);
         break;
       case IES_INIT:
+      case IES_CAST:
         assert(!BracCount && "BracCount should be zero on parsing's start");
         State = IES_LBRAC;
         break;
       }
       MemExpr = true;
       BracCount++;
       return false;
     }
void onRParen() {
       PrevState = State;
       switch (State) {
       default:
         State = IES_ERROR;
         break;
       case IES_INTEGER:
       case IES_OFFSET:
       case IES_REGISTER:
+      case IES_RBRAC:
       case IES_RPAREN:
         State = IES_RPAREN;
         IC.pushOperator(IC_RPAREN);
         break;
       }
     }
     bool onOffset(const MCExpr *Val, SMLoc OffsetLoc, StringRef ID,
                   const InlineAsmIdentifierInfo &IDInfo, bool ParsingMSInlineAsm,
bool onOffset(const MCExpr *Val, SMLoc OffsetLoc, StringRef ID,
         IC.pushOperand(IC_IMM);
         if (ParsingMSInlineAsm) {
           Info = IDInfo;
         }
         break;
       }
       return false;
     }
+    void onCast(StringRef Type) {
+      PrevState = State;
+      switch (State) {
+      default:
+        State = IES_ERROR;
+        break;
+      case IES_LPAREN:
+        setType(Type);
+        State = IES_CAST;
+        break;
+      }
+    }
     void setType(StringRef Type) { CurType = Type; }
   };
 
   bool Error(SMLoc L, const Twine &Msg, SMRange Range = None,
              bool MatchingInlineAsm = false) {
     MCAsmParser &Parser = getParser();
     if (MatchingInlineAsm) {
       if (!getLexer().isAtStartOfStatement())
case AsmToken::Real:
         return true;
       break;
     case AsmToken::At:
     case AsmToken::String:
     case AsmToken::Identifier: {
       SMLoc IdentLoc = Tok.getLoc();
       StringRef Identifier = Tok.getString();
       UpdateLocLex = false;
+      // (MASM only) <TYPE> PTR operator
+      if (Parser.isParsingMasm()) {
+        const AsmToken &NextTok = getLexer().peekTok();
+        if (NextTok.is(AsmToken::Identifier) &&
+            NextTok.getIdentifier().equals_lower("ptr")) {
+          SM.onCast(Identifier);
+          // eat type and ptr
+          consumeToken();
+          End = consumeToken();
+          break;
+        }
+      }
       // Register, or (MASM only) <register>.<field>
       unsigned Reg;
       if (Tok.is(AsmToken::Identifier)) {
         if (!ParseRegister(Reg, IdentLoc, End, /*RestoreOnFailure=*/true)) {
           if (SM.onRegister(Reg, ErrMsg))
             return Error(IdentLoc, ErrMsg);
           break;
         }
case AsmToken::Identifier: {
           return true;
         break;
       }
       // Symbol reference, when parsing assembly content
       InlineAsmIdentifierInfo Info;
       const MCExpr *Val;
       if (isParsingMSInlineAsm() || Parser.isParsingMasm()) {
         // MS Dot Operator expression
-        if (Identifier.count('.') && PrevTK == AsmToken::RBrac) {
+        if (Identifier.count('.') &&
+            (PrevTK == AsmToken::RBrac || PrevTK == AsmToken::RParen)) {
           if (ParseIntelDotOperator(SM, End))
             return true;
           break;
         }
       }
       if (isParsingMSInlineAsm()) {
         // MS InlineAsm operators (TYPE/LENGTH/SIZE)
         if (unsigned OpKind = IdentifyIntelInlineAsmOperator(Identifier)) {

llvm/test/tools/llvm-ml/struct.test

 ; CHECK: t9:
 ; CHECK-NEXT: mov eax, dword ptr [ebx]
 ; CHECK-NEXT: mov eax, dword ptr [ebx + 4]
 ; CHECK-NEXT: mov eax, dword ptr [ebx + 4]
 ; CHECK-NEXT: mov eax, dword ptr [ebx + 4]
 ; CHECK-NEXT: mov eax, dword ptr [ebx + 5]
 ; CHECK-NEXT: mov eax, dword ptr [ebx + 8]
 
+t10:
+mov eax, FOOBAR.f
+mov eax, FOOBAR.f.h
+
+; CHECK: t10:
+; CHECK-NEXT: mov eax, 10
+; CHECK-NEXT: mov eax, 12
+
+t11:
+mov eax, (FOOBAR PTR [ebx]).f
+mov eax, (FOOBAR PTR t1).f
+
+; CHECK: t11:
+; CHECK-NEXT: mov eax, dword ptr [ebx + 10]
+; CHECK-NEXT: mov eax, dword ptr [rip + t1+10]
+
 END