[GlobalISel][InlineAsm] Fix matching input constraints to mem operand

[Petar.Avramovic]

Summary

Mark matching input constraint to mem operand as not supported.

[Petar.Avramovic]

This fixes assert and makes this test mentioned in D82651 to fallback for aarch64.
This seem to have different handling on different targets. I don't know what is the best way to handle this since it looks to me that custom handling has to be done in different places
Just adding same flag and register as MatchedOperand works for this example but from this comment

// We need to make sure that this one operand does not end up in XZR, thus
// require the address to be in a PointerRegClass register.

in AArch64DAGToDAGISel::SelectInlineAsmMemoryOperand an extra copy to a register with PointerRegClass needs to be done. Something like:

--- a/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
@@ -356,7 +356,11 @@ bool InlineAsmLowering::lowerInlineAsm(
         assert(
             SourceRegs.size() == 1 &&
             "Expected the memory output to fit into a single virtual register");
-        Inst.addReg(SourceRegs[0]);
+        const TargetRegisterClass *TRC =
+            MF.getSubtarget().getRegisterInfo()->getPointerRegClass(MF);
+        Register Tmp = MRI->createVirtualRegister(TRC);
+        MIRBuilder.buildCopy(Tmp, SourceRegs[0]);
+        Inst.addReg(Tmp);
       } else {
         // Otherwise, this outputs to a register (directly for C_Register /
         // C_RegisterClass. Find a register that we can use.
@@ -406,6 +410,19 @@ bool InlineAsmLowering::lowerInlineAsm(
           InstFlagIdx += getNumOpRegs(*Inst, InstFlagIdx) + 1;
         assert(getNumOpRegs(*Inst, InstFlagIdx) == 1 && "Wrong flag");
 
+        unsigned MatchedOperandFlag = Inst->getOperand(InstFlagIdx).getImm();
+        if (InlineAsm::isMemKind(MatchedOperandFlag)) {
+          Inst.addImm(MatchedOperandFlag);
+          Inst.addReg(Inst->getOperand(InstFlagIdx + 1).getReg());
+          break;
+        }
+
+        if (!InlineAsm::isRegDefKind(MatchedOperandFlag) &&
+            !InlineAsm::isRegDefEarlyClobberKind(MatchedOperandFlag)) {
+          LLVM_DEBUG(dbgs() << "Unknown matching constraint\n");
+          return false;
+        }
+
         // We want to tie input to register in next operand.
         unsigned DefRegIdx = InstFlagIdx + 1;
         Register Def = Inst->getOperand(DefRegIdx).getReg();

but target should create copy / add immediate and register to Inst.

[arsenm]

getPointerRegClass is terrible, but also shouldn't be necessary in GlobalISel since pointer types aren't lost

llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp

417

I don't think this case is covered in the test?

[Petar.Avramovic]

llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp

417

That was covered in D82651 but I didn't check the flag and missed to report that isMemKind() was unsupported .

llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp

case InlineAsm::isInput: {
       if (OpInfo.isMatchingInputConstraint()) {
         unsigned DefIdx = OpInfo.getMatchedOperand();
         // Find operand with register def that corresponds to DefIdx.
         unsigned InstFlagIdx = StartIdx;
         for (unsigned i = 0; i < DefIdx; ++i)
           InstFlagIdx += getNumOpRegs(*Inst, InstFlagIdx) + 1;
         assert(getNumOpRegs(*Inst, InstFlagIdx) == 1 && "Wrong flag");
 
+        unsigned MatchedOperandFlag = Inst->getOperand(InstFlagIdx).getImm();
+        if (InlineAsm::isMemKind(MatchedOperandFlag)) {
+          LLVM_DEBUG(dbgs() << "Matching input constraint to mem operand not "
+                               "supported. This should be target specific.\n");
+          return false;
+        }
+        if (!InlineAsm::isRegDefKind(MatchedOperandFlag) &&
+            !InlineAsm::isRegDefEarlyClobberKind(MatchedOperandFlag)) {
+          LLVM_DEBUG(dbgs() << "Unknown matching constraint\n");
+          return false;
+        }
+
         // We want to tie input to register in next operand.
         unsigned DefRegIdx = InstFlagIdx + 1;
         Register Def = Inst->getOperand(DefRegIdx).getReg();
 
         // Copy input to new vreg with same reg class as Def
         const TargetRegisterClass *RC = MRI->getRegClass(Def);
         ArrayRef<Register> SrcRegs = GetOrCreateVRegs(*OpInfo.CallOperandVal);
         assert(SrcRegs.size() == 1 && "Single register is expected here");

llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll

 ; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to translate instruction{{.*}}scalable_call
 ; FALLBACK-WITH-REPORT-OUT-LABEL: scalable_call
 define <vscale x 16 x i8> @scalable_call(i8* %addr) #1 {
   %pred = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 0)
   %res = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1.nxv16i8(<vscale x 16 x i1> %pred, i8* %addr)
   ret <vscale x 16 x i8> %res
 }
 
+; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to translate instruction{{.*}}asm_indirect_output
+; FALLBACK-WITH-REPORT-OUT-LABEL: asm_indirect_output
+define void @asm_indirect_output() {
+entry:
+  %ap = alloca i8*, align 8
+  %0 = load i8*, i8** %ap, align 8
+  call void asm sideeffect "", "=*r|m,0,~{memory}"(i8** %ap, i8* %0)
+  ret void
+}
+
 attributes #1 = { "target-features"="+sve" }
 
 declare <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 %pattern)
 declare <vscale x 16 x i8> @llvm.aarch64.sve.ld1.nxv16i8(<vscale x 16 x i1>, i8*)