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Differential D83052

[PowerPC][Power10] Add Vector Insert Instruction Definitions and MC Tests
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Authored by amyk on Jul 2 2020, 7:32 AM.

Details

Reviewers
power-llvm-team
nemanjai
lei
biplmish
Group Reviewers
Restricted Project
Commits
rG6076fc698df4: [PowerPC]Add Vector Insert Instruction Definitions and MC Test
Summary

This patch adds the td definitions and asm/disasm tests for the following instructions:

VINSBVLX
VINSBVRX
VINSHVLX
VINSHVRX
VINSWVLX
VINSWVRX
VINSBLX
VINSBRX
VINSHLX
VINSHRX
VINSWLX
VINSWRX
VINSDLX
VINSDRX

VINSW
VINSD

Diff Detail

Event Timeline

amyk created this revision.Jul 2 2020, 7:32 AM
Herald added subscribers: llvm-commits, shchenz, hiraditya. · View Herald TranscriptJul 2 2020, 7:32 AM
lei requested changes to this revision.Jul 2 2020, 8:16 AM
lei added inline comments.
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
231

Was this meant to be VXForm_VRT5_UIM5_RB5?

780

Why not define a class similar to VX_VRT5_UIM5_RB5 to be used for the instruction def below?

This revision now requires changes to proceed.Jul 2 2020, 8:16 AM
amyk marked 2 inline comments as done.Jul 2 2020, 8:25 AM
amyk added inline comments.
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
231

I'll need to fix that, thanks.

780

Sorry, I originally intended to do that since we have vinsw and vinsd defined with a multiclass, but not sure why I didn't... Will fix.

Harbormaster failed remote builds in B62685: Diff 275110!Jul 2 2020, 9:10 AM
amyk updated this revision to Diff 275144.Jul 2 2020, 9:17 AM

Refactor the patch to use multiclass.

lei accepted this revision.Jul 2 2020, 10:24 AM

LGTM

This revision is now accepted and ready to land.Jul 2 2020, 10:24 AM
nemanjai accepted this revision.Jul 2 2020, 10:35 AM

LGTM other than the naming nit.

llvm/lib/Target/PowerPC/PPCInstrPrefix.td
231

Since we are making the register constraints part of the instruction format, I think the name should reflect that.
Perhaps suffix these with _ins so that if we end up getting a non-destructive VXForm that takes a 5-bit unsigned immediate and a GPR and produces a VR, we won't use this form erroneously.

Harbormaster failed remote builds in B62701: Diff 275144!Jul 2 2020, 10:47 AM
Closed by commit rG6076fc698df4: [PowerPC]Add Vector Insert Instruction Definitions and MC Test (authored by amyk, committed by lei). · Explain WhyJul 2 2020, 2:04 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
lib/
Target/
PowerPC/
40 lines
test/
MC/
Disassembler/
PowerPC/
48 lines
PowerPC/
48 lines

Diff 275223

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

Show First 20 Lines • Show All 219 Lines • ▼ Show 20 Linesclass VXForm_RD5_N3_VB5<bits<11> xo, dag OOL, dag IOL, string asmstr,
let Inst{6-10} = RD; let Inst{6-10} = RD;
let Inst{11-12} = 0; let Inst{11-12} = 0;
let Inst{13-15} = N; let Inst{13-15} = N;
let Inst{16-20} = VB; let Inst{16-20} = VB;
let Inst{21-31} = xo; let Inst{21-31} = xo;
} }
// VX-Form: [PO VRT / UIM RB XO].
// We use VXForm_1 to implement it, that is, we use "VRA" (5 bit) to represent
// "/ UIM" (unused bit followed by a 4-bit immediate)
leiUnsubmitted
Not Done
ReplyInline Actions

Was this meant to be VXForm_VRT5_UIM5_RB5?

lei: Was this meant to be `VXForm_VRT5_UIM5_RB5`?
amykAuthorUnsubmitted
Done
ReplyInline Actions

I'll need to fix that, thanks.

amyk: I'll need to fix that, thanks.
nemanjaiUnsubmitted
Not Done
ReplyInline Actions

Since we are making the register constraints part of the instruction format, I think the name should reflect that.
Perhaps suffix these with _ins so that if we end up getting a non-destructive VXForm that takes a 5-bit unsigned immediate and a GPR and produces a VR, we won't use this form erroneously.

nemanjai: Since we are making the register constraints part of the instruction format, I think the name…
// Destructive (insert) forms are suffixed with _ins.
class VXForm_VRT5_UIM5_RB5_ins<bits<11> xo, string opc, list<dag> pattern>
: VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vDi, u4imm:$UIM, g8rc:$rB),
!strconcat(opc, " $vD, $rB, $UIM"), IIC_VecGeneral, pattern>,
RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
// VX-Form: [PO VRT RA VRB XO].
// Destructive (insert) forms are suffixed with _ins.
class VXForm_VTB5_RA5_ins<bits<11> xo, string opc, list<dag> pattern>
: VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vDi, g8rc:$rA, vrrc:$vB),
!strconcat(opc, " $vD, $rA, $vB"), IIC_VecGeneral, pattern>,
RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
// VX-Form: [PO VRT RA RB XO].
// Destructive (insert) forms are suffixed with _ins.
class VXForm_VRT5_RAB5_ins<bits<11> xo, string opc, list<dag> pattern>
: VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vDi, g8rc:$rA, g8rc:$rB),
!strconcat(opc, " $vD, $rA, $rB"), IIC_VecGeneral, pattern>,
RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
// VN-Form: [PO VRT VRA VRB PS SD XO] // VN-Form: [PO VRT VRA VRB PS SD XO]
// SD is "Shift Direction" // SD is "Shift Direction"
class VNForm_VTAB5_SD3<bits<6> xo, bits<2> ps, dag OOL, dag IOL, string asmstr, class VNForm_VTAB5_SD3<bits<6> xo, bits<2> ps, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern> InstrItinClass itin, list<dag> pattern>
: I<4, OOL, IOL, asmstr, itin> { : I<4, OOL, IOL, asmstr, itin> {
bits<5> VRT; bits<5> VRT;
bits<5> VRA; bits<5> VRA;
bits<5> VRB; bits<5> VRB;
▲ Show 20 Lines • Show All 510 Lines • ▼ Show 20 Lineslet Predicates = [IsISA3_1] in {
def VSRDBI : VNForm_VTAB5_SD3<22, 1, (outs vrrc:$VRT), def VSRDBI : VNForm_VTAB5_SD3<22, 1, (outs vrrc:$VRT),
(ins vrrc:$VRA, vrrc:$VRB, u3imm:$SH), (ins vrrc:$VRA, vrrc:$VRB, u3imm:$SH),
"vsrdbi $VRT, $VRA, $VRB, $SH", "vsrdbi $VRT, $VRA, $VRB, $SH",
IIC_VecGeneral, IIC_VecGeneral,
[(set v16i8:$VRT, [(set v16i8:$VRT,
(int_ppc_altivec_vsrdbi v16i8:$VRA, (int_ppc_altivec_vsrdbi v16i8:$VRA,
v16i8:$VRB, v16i8:$VRB,
i32:$SH))]>; i32:$SH))]>;
def VINSW : VXForm_VRT5_UIM5_RB5_ins<207, "vinsw", []>;
def VINSD : VXForm_VRT5_UIM5_RB5_ins<463, "vinsd", []>;
def VINSBVLX : VXForm_VTB5_RA5_ins<15, "vinsbvlx", []>;
leiUnsubmitted
Not Done
ReplyInline Actions

Why not define a class similar to VX_VRT5_UIM5_RB5 to be used for the instruction def below?

lei: Why not define a class similar to `VX_VRT5_UIM5_RB5` to be used for the instruction def below?
amykAuthorUnsubmitted
Done
ReplyInline Actions

Sorry, I originally intended to do that since we have vinsw and vinsd defined with a multiclass, but not sure why I didn't... Will fix.

amyk: Sorry, I originally intended to do that since we have `vinsw` and `vinsd` defined with a…
def VINSBVRX : VXForm_VTB5_RA5_ins<271, "vinsbvrx", []>;
def VINSHVLX : VXForm_VTB5_RA5_ins<79, "vinshvlx", []>;
def VINSHVRX : VXForm_VTB5_RA5_ins<335, "vinshvrx", []>;
def VINSWVLX : VXForm_VTB5_RA5_ins<143, "vinswvlx", []>;
def VINSWVRX : VXForm_VTB5_RA5_ins<399, "vinswvrx", []>;
def VINSBLX : VXForm_VRT5_RAB5_ins<527, "vinsblx", []>;
def VINSBRX : VXForm_VRT5_RAB5_ins<783, "vinsbrx", []>;
def VINSHLX : VXForm_VRT5_RAB5_ins<591, "vinshlx", []>;
def VINSHRX : VXForm_VRT5_RAB5_ins<847, "vinshrx", []>;
def VINSWLX : VXForm_VRT5_RAB5_ins<655, "vinswlx", []>;
def VINSWRX : VXForm_VRT5_RAB5_ins<911, "vinswrx", []>;
def VINSDLX : VXForm_VRT5_RAB5_ins<719, "vinsdlx", []>;
def VINSDRX : VXForm_VRT5_RAB5_ins<975, "vinsdrx", []>;
def VPDEPD : VXForm_1<1485, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VPDEPD : VXForm_1<1485, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
"vpdepd $vD, $vA, $vB", IIC_VecGeneral, "vpdepd $vD, $vA, $vB", IIC_VecGeneral,
[(set v2i64:$vD, [(set v2i64:$vD,
(int_ppc_altivec_vpdepd v2i64:$vA, v2i64:$vB))]>; (int_ppc_altivec_vpdepd v2i64:$vA, v2i64:$vB))]>;
def VPEXTD : VXForm_1<1421, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VPEXTD : VXForm_1<1421, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
"vpextd $vD, $vA, $vB", IIC_VecGeneral, "vpextd $vD, $vA, $vB", IIC_VecGeneral,
[(set v2i64:$vD, [(set v2i64:$vD,
(int_ppc_altivec_vpextd v2i64:$vA, v2i64:$vB))]>; (int_ppc_altivec_vpextd v2i64:$vA, v2i64:$vB))]>;
▲ Show 20 Lines • Show All 94 Lines • Show Last 20 Lines

llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt

Show First 20 Lines • Show All 224 Lines • ▼ Show 20 Lines
# CHECK: xxblendvd 6, 63, 21, 34 # CHECK: xxblendvd 6, 63, 21, 34
0x05 0x00 0x00 0x00 0x84 0xdf 0xa8 0xbc 0x05 0x00 0x00 0x00 0x84 0xdf 0xa8 0xbc
# CHECK: vsldbi 2, 3, 4, 5 # CHECK: vsldbi 2, 3, 4, 5
0x10 0x43 0x21 0x56 0x10 0x43 0x21 0x56
# CHECK: vsrdbi 2, 3, 4, 5 # CHECK: vsrdbi 2, 3, 4, 5
0x10 0x43 0x23 0x56 0x10 0x43 0x23 0x56
# CHECK: vinsw 2, 3, 12
0x10 0x4c 0x18 0xcf
# CHECK: vinsd 2, 3, 12
0x10 0x4c 0x19 0xcf
# CHECK: vinsbvlx 1, 3, 5
0x10 0x23 0x28 0x0f
# CHECK: vinsbvrx 1, 3, 5
0x10 0x23 0x29 0x0f
# CHECK: vinshvlx 1, 3, 5
0x10 0x23 0x28 0x4f
# CHECK: vinshvrx 1, 3, 5
0x10 0x23 0x29 0x4f
# CHECK: vinswvlx 1, 3, 5
0x10 0x23 0x28 0x8f
# CHECK: vinswvrx 1, 3, 5
0x10 0x23 0x29 0x8f
# CHECK: vinsblx 1, 2, 3
0x10 0x22 0x1a 0x0f
# CHECK: vinsbrx 1, 2, 3
0x10 0x22 0x1b 0x0f
# CHECK: vinshlx 1, 2, 3
0x10 0x22 0x1a 0x4f
# CHECK: vinshrx 1, 2, 3
0x10 0x22 0x1b 0x4f
# CHECK: vinswlx 1, 2, 3
0x10 0x22 0x1a 0x8f
# CHECK: vinswrx 1, 2, 3
0x10 0x22 0x1b 0x8f
# CHECK: vinsdlx 1, 2, 3
0x10 0x22 0x1a 0xcf
# CHECK: vinsdrx 1, 2, 3
0x10 0x22 0x1b 0xcf

llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s

Show First 20 Lines • Show All 351 Lines • ▼ Show 20 Lines
# CHECK-LE-SAME: 0xbc,0xa8,0xdf,0x84] # CHECK-LE-SAME: 0xbc,0xa8,0xdf,0x84]
xxblendvd 6, 63, 21, 34 xxblendvd 6, 63, 21, 34
# CHECK-BE: vsldbi 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x56] # CHECK-BE: vsldbi 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x56]
# CHECK-LE: vsldbi 2, 3, 4, 5 # encoding: [0x56,0x21,0x43,0x10] # CHECK-LE: vsldbi 2, 3, 4, 5 # encoding: [0x56,0x21,0x43,0x10]
vsldbi 2, 3, 4, 5 vsldbi 2, 3, 4, 5
# CHECK-BE: vsrdbi 2, 3, 4, 5 # encoding: [0x10,0x43,0x23,0x56] # CHECK-BE: vsrdbi 2, 3, 4, 5 # encoding: [0x10,0x43,0x23,0x56]
# CHECK-LE: vsrdbi 2, 3, 4, 5 # encoding: [0x56,0x23,0x43,0x10] # CHECK-LE: vsrdbi 2, 3, 4, 5 # encoding: [0x56,0x23,0x43,0x10]
vsrdbi 2, 3, 4, 5 vsrdbi 2, 3, 4, 5
# CHECK-BE: vinsw 2, 3, 12 # encoding: [0x10,0x4c,0x18,0xcf]
# CHECK-LE: vinsw 2, 3, 12 # encoding: [0xcf,0x18,0x4c,0x10]
vinsw 2, 3, 12
# CHECK-BE: vinsd 2, 3, 12 # encoding: [0x10,0x4c,0x19,0xcf]
# CHECK-LE: vinsd 2, 3, 12 # encoding: [0xcf,0x19,0x4c,0x10]
vinsd 2, 3, 12
# CHECK-BE: vinsbvlx 1, 3, 5 # encoding: [0x10,0x23,0x28,0x0f]
# CHECK-LE: vinsbvlx 1, 3, 5 # encoding: [0x0f,0x28,0x23,0x10]
vinsbvlx 1, 3, 5
# CHECK-BE: vinsbvrx 1, 3, 5 # encoding: [0x10,0x23,0x29,0x0f]
# CHECK-LE: vinsbvrx 1, 3, 5 # encoding: [0x0f,0x29,0x23,0x10]
vinsbvrx 1, 3, 5
# CHECK-BE: vinshvlx 1, 3, 5 # encoding: [0x10,0x23,0x28,0x4f]
# CHECK-LE: vinshvlx 1, 3, 5 # encoding: [0x4f,0x28,0x23,0x10]
vinshvlx 1, 3, 5
# CHECK-BE: vinshvrx 1, 3, 5 # encoding: [0x10,0x23,0x29,0x4f]
# CHECK-LE: vinshvrx 1, 3, 5 # encoding: [0x4f,0x29,0x23,0x10]
vinshvrx 1, 3, 5
# CHECK-BE: vinswvlx 1, 3, 5 # encoding: [0x10,0x23,0x28,0x8f]
# CHECK-LE: vinswvlx 1, 3, 5 # encoding: [0x8f,0x28,0x23,0x10]
vinswvlx 1, 3, 5
# CHECK-BE: vinswvrx 1, 3, 5 # encoding: [0x10,0x23,0x29,0x8f]
# CHECK-LE: vinswvrx 1, 3, 5 # encoding: [0x8f,0x29,0x23,0x10]
vinswvrx 1, 3, 5
# CHECK-BE: vinsblx 1, 2, 3 # encoding: [0x10,0x22,0x1a,0x0f]
# CHECK-LE: vinsblx 1, 2, 3 # encoding: [0x0f,0x1a,0x22,0x10]
vinsblx 1, 2, 3
# CHECK-BE: vinsbrx 1, 2, 3 # encoding: [0x10,0x22,0x1b,0x0f]
# CHECK-LE: vinsbrx 1, 2, 3 # encoding: [0x0f,0x1b,0x22,0x10]
vinsbrx 1, 2, 3
# CHECK-BE: vinshlx 1, 2, 3 # encoding: [0x10,0x22,0x1a,0x4f]
# CHECK-LE: vinshlx 1, 2, 3 # encoding: [0x4f,0x1a,0x22,0x10]
vinshlx 1, 2, 3
# CHECK-BE: vinshrx 1, 2, 3 # encoding: [0x10,0x22,0x1b,0x4f]
# CHECK-LE: vinshrx 1, 2, 3 # encoding: [0x4f,0x1b,0x22,0x10]
vinshrx 1, 2, 3
# CHECK-BE: vinswlx 1, 2, 3 # encoding: [0x10,0x22,0x1a,0x8f]
# CHECK-LE: vinswlx 1, 2, 3 # encoding: [0x8f,0x1a,0x22,0x10]
vinswlx 1, 2, 3
# CHECK-BE: vinswrx 1, 2, 3 # encoding: [0x10,0x22,0x1b,0x8f]
# CHECK-LE: vinswrx 1, 2, 3 # encoding: [0x8f,0x1b,0x22,0x10]
vinswrx 1, 2, 3
# CHECK-BE: vinsdlx 1, 2, 3 # encoding: [0x10,0x22,0x1a,0xcf]
# CHECK-LE: vinsdlx 1, 2, 3 # encoding: [0xcf,0x1a,0x22,0x10]
vinsdlx 1, 2, 3
# CHECK-BE: vinsdrx 1, 2, 3 # encoding: [0x10,0x22,0x1b,0xcf]
# CHECK-LE: vinsdrx 1, 2, 3 # encoding: [0xcf,0x1b,0x22,0x10]
vinsdrx 1, 2, 3