Page MenuHomePhabricator

[PowerPC][Power10] Add Vector Insert Instruction Definitions and MC Tests
ClosedPublic

Authored by amyk on Jul 2 2020, 7:32 AM.

Details

Summary

This patch adds the td definitions and asm/disasm tests for the following instructions:

VINSBVLX
VINSBVRX
VINSHVLX
VINSHVRX
VINSWVLX
VINSWVRX
VINSBLX
VINSBRX
VINSHLX
VINSHRX
VINSWLX
VINSWRX
VINSDLX
VINSDRX

VINSW
VINSD

Diff Detail

Event Timeline

amyk created this revision.Jul 2 2020, 7:32 AM
lei requested changes to this revision.Jul 2 2020, 8:16 AM
lei added inline comments.
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
231

Was this meant to be VXForm_VRT5_UIM5_RB5?

780

Why not define a class similar to VX_VRT5_UIM5_RB5 to be used for the instruction def below?

This revision now requires changes to proceed.Jul 2 2020, 8:16 AM
amyk marked 2 inline comments as done.Jul 2 2020, 8:25 AM
amyk added inline comments.
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
231

I'll need to fix that, thanks.

780

Sorry, I originally intended to do that since we have vinsw and vinsd defined with a multiclass, but not sure why I didn't... Will fix.

amyk updated this revision to Diff 275144.Jul 2 2020, 9:17 AM

Refactor the patch to use multiclass.

lei accepted this revision.Jul 2 2020, 10:24 AM

LGTM

This revision is now accepted and ready to land.Jul 2 2020, 10:24 AM
nemanjai accepted this revision.Jul 2 2020, 10:35 AM

LGTM other than the naming nit.

llvm/lib/Target/PowerPC/PPCInstrPrefix.td
231

Since we are making the register constraints part of the instruction format, I think the name should reflect that.
Perhaps suffix these with _ins so that if we end up getting a non-destructive VXForm that takes a 5-bit unsigned immediate and a GPR and produces a VR, we won't use this form erroneously.

This revision was automatically updated to reflect the committed changes.