[AArch64] Emit warning when disassembling unpredictable LDRAA and LDRAB

[vhscampos]

Summary

LDRAA and LDRAB in their writeback variant should softfail when the same
register is used as result and base.

This patch adds a custom decoder that catches such case and emits a
warning when it occurs.

[DavidSpickett]

llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp

1511

This should be 5, 9. I presume the tests pass because they all use x0.

1521

What does this first decode do, is it not enough to Decode it below?

[vhscampos]

llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp

1511

Are you sure? The third argument is the number of bits to be read.

1521

The writeback variants have an additional operand: the writeback register. Therefore when decoding those variants, it is necessary to perform one additional operand decoding.

[DavidSpickett]

LGTM

llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp

1511

Yes you're right, just happened that the numbers lined up.

llvm/lib/Target/AArch64/AArch64InstrFormats.td

class BaseAuthLoad<bit M, bit W, dag oops, dag iops, string asm,
   let Inst{23} = M;
   let Inst{22} = offset{9};
   let Inst{21} = 1;
   let Inst{20-12} = offset{8-0};
   let Inst{11} = W;
   let Inst{10} = 1;
   let Inst{9-5} = Rn;
   let Inst{4-0} = Rt;
+
+  let DecoderMethod = "DecodeAuthLoadInstruction";
 }
 
 multiclass AuthLoad<bit M, string asm, Operand opr> {
   def indexed   : BaseAuthLoad<M, 0, (outs GPR64:$Rt),
                                (ins GPR64sp:$Rn, opr:$offset),
                                asm, "\t$Rt, [$Rn, $offset]", "", opr>;
   def writeback : BaseAuthLoad<M, 1, (outs GPR64sp:$wback, GPR64:$Rt),
                                (ins GPR64sp:$Rn, opr:$offset),

llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp

static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn,
                                                 uint64_t Address,
                                                 const void *Decoder);
 static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn,
                                                    uint64_t Address,
                                                    const void *Decoder);
 static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn,
                                               uint64_t Address,
                                               const void *Decoder);
+static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn,
+                                              uint64_t Address,
+                                              const void *Decoder);
 static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn,
                                                 uint64_t Address,
                                                 const void *Decoder);
 static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn,
                                                 uint64_t Address,
                                                 const void *Decoder);
 static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn,
                                             uint64_t Address,
static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn,
   // ... or do any operation that writes-back to a transfer register. But note
   // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different.
   if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn))
     return SoftFail;
 
   return Success;
 }
 
+static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn,
+                                              uint64_t Addr,
+                                              const void *Decoder) {
+  unsigned Rt = fieldFromInstruction(insn, 0, 5);
+  unsigned Rn = fieldFromInstruction(insn, 5, 5);
+  uint64_t offset = fieldFromInstruction(insn, 22, 1) << 9 |
+                    fieldFromInstruction(insn, 12, 9);
+  unsigned writeback = fieldFromInstruction(insn, 11, 1);
+
+  switch (Inst.getOpcode()) {
+  default:
+    return Fail;
+  case AArch64::LDRAAwriteback:
+  case AArch64::LDRABwriteback:
+    DecodeGPR64spRegisterClass(Inst, Rn /* writeback register */, Addr,
+                               Decoder);
+    break;
+  case AArch64::LDRAAindexed:
+  case AArch64::LDRABindexed:
+    break;
+  }
+
+  DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
+  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
+  DecodeSImm<10>(Inst, offset, Addr, Decoder);
+
+  if (writeback && Rt == Rn && Rn != 31) {
+    return SoftFail;
+  }
+
+  return Success;
+}
+
 static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn,
                                                 uint64_t Addr,
                                                 const void *Decoder) {
   unsigned Rd = fieldFromInstruction(insn, 0, 5);
   unsigned Rn = fieldFromInstruction(insn, 5, 5);
   unsigned Rm = fieldFromInstruction(insn, 16, 5);
   unsigned extend = fieldFromInstruction(insn, 10, 6);
 

llvm/test/MC/Disassembler/AArch64/armv8.3a-signed-pointer.txt

-# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.3a --disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.3a --disassemble < %s 2>&1 | FileCheck %s
+
+# CHECK: warning: potentially undefined instruction encoding
+# CHECK-NEXT: [0x00,0x0c,0x20,0xf8]
+# CHECK: warning: potentially undefined instruction encoding
+# CHECK-NEXT: [0x00,0x0c,0xa0,0xf8]
+# CHECK: ldraa x0, [x0, #0]!
+# CHECK: ldrab x0, [x0, #0]!
+[0x00,0x0c,0x20,0xf8]
+[0x00,0x0c,0xa0,0xf8]
 
 # CHECK: paciasp
 # CHECK: autiasp
 # CHECK: paciaz
 # CHECK: autiaz
 # CHECK: pacia1716
 # CHECK: autia1716
 # CHECK: pacibsp