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Differential D82472

[X86] Fix a typo error.
ClosedPublic

Authored by pengfei on Jun 24 2020, 8:41 AM.

Details

Reviewers
craig.topper
LuoYuanke
Commits
rGb2eb1c5793d7: [X86] Fix a typo error.
Summary

This will result opcode MULX32Hrm been emitted to MULX32Hrr.

Diff Detail

Event Timeline

pengfei created this revision.Jun 24 2020, 8:41 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 24 2020, 8:41 AM
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craig.topper added a comment.Jun 24 2020, 9:22 AM

Thanks. Are you able to provide a test case?

Harbormaster failed remote builds in B61561: Diff 273050!Jun 24 2020, 10:48 AM
pengfei updated this revision to Diff 273214.Jun 24 2020, 6:45 PM

Add a test case. Thanks Craig.

craig.topper accepted this revision.Jun 24 2020, 7:04 PM

LGTM

This revision is now accepted and ready to land.Jun 24 2020, 7:04 PM
Closed by commit rGb2eb1c5793d7: [X86] Fix a typo error. (authored by Wang, Pengfei <pengfei.wang@intel.com>). · Explain WhyJun 24 2020, 7:33 PM
This revision was automatically updated to reflect the committed changes.
Harbormaster failed remote builds in B61658: Diff 273214!Jun 24 2020, 8:05 PM

Revision Contents

PathSize
llvm/
lib/
Target/
X86/
2 lines

Diff 273050

llvm/lib/Target/X86/X86MCInstLower.cpp

//===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===// //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
Lint: Lint
Inline Actions

clang-format suggested style edits found:

Lint: Lint: clang-format suggested style edits found:
// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// This file contains code to lower X86 MachineInstrs to their corresponding // This file contains code to lower X86 MachineInstrs to their corresponding
▲ Show 20 Lines • Show All 503 Lines • ▼ Show 20 Linesvoid X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
case X86::MULX32Hrm: case X86::MULX32Hrm:
case X86::MULX64Hrr: case X86::MULX64Hrr:
case X86::MULX64Hrm: { case X86::MULX64Hrm: {
// Turn into regular MULX by duplicating the destination. // Turn into regular MULX by duplicating the destination.
unsigned NewOpc; unsigned NewOpc;
switch (OutMI.getOpcode()) { switch (OutMI.getOpcode()) {
default: llvm_unreachable("Invalid opcode"); default: llvm_unreachable("Invalid opcode");
case X86::MULX32Hrr: NewOpc = X86::MULX32rr; break; case X86::MULX32Hrr: NewOpc = X86::MULX32rr; break;
case X86::MULX32Hrm: NewOpc = X86::MULX32rr; break; case X86::MULX32Hrm: NewOpc = X86::MULX32rm; break;
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    case X86::MULX32Hrm: NewOpc = X86::MULX32rm; break;
+    case X86::MULX32Hrm:
+      NewOpc = X86::MULX32rm;
+      break;
Lint: Pre-merge checks: clang-format: please reformat the code ``` - case X86::MULX32Hrm: NewOpc = X86::MULX32rm…
case X86::MULX64Hrr: NewOpc = X86::MULX64rr; break; case X86::MULX64Hrr: NewOpc = X86::MULX64rr; break;
case X86::MULX64Hrm: NewOpc = X86::MULX64rm; break; case X86::MULX64Hrm: NewOpc = X86::MULX64rm; break;
} }
OutMI.setOpcode(NewOpc); OutMI.setOpcode(NewOpc);
// Duplicate the destination. // Duplicate the destination.
unsigned DestReg = OutMI.getOperand(0).getReg(); unsigned DestReg = OutMI.getOperand(0).getReg();
OutMI.insert(OutMI.begin(), MCOperand::createReg(DestReg)); OutMI.insert(OutMI.begin(), MCOperand::createReg(DestReg));
break; break;
▲ Show 20 Lines • Show All 2,089 Lines • Show Last 20 Lines