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Differential D82472

[X86] Fix a typo error.
ClosedPublic

Authored by pengfei on Jun 24 2020, 8:41 AM.

Details

Reviewers
craig.topper
LuoYuanke
Commits
rGb2eb1c5793d7: [X86] Fix a typo error.
Summary

This will result opcode MULX32Hrm been emitted to MULX32Hrr.

Diff Detail

Event Timeline

pengfei created this revision.Jun 24 2020, 8:41 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 24 2020, 8:41 AM
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craig.topper added a comment.Jun 24 2020, 9:22 AM

Thanks. Are you able to provide a test case?

Harbormaster failed remote builds in B61561: Diff 273050!Jun 24 2020, 10:48 AM
pengfei updated this revision to Diff 273214.Jun 24 2020, 6:45 PM

Add a test case. Thanks Craig.

craig.topper accepted this revision.Jun 24 2020, 7:04 PM

LGTM

This revision is now accepted and ready to land.Jun 24 2020, 7:04 PM
Closed by commit rGb2eb1c5793d7: [X86] Fix a typo error. (authored by Wang, Pengfei <pengfei.wang@intel.com>). · Explain WhyJun 24 2020, 7:33 PM
This revision was automatically updated to reflect the committed changes.
Harbormaster failed remote builds in B61658: Diff 273214!Jun 24 2020, 8:05 PM

Revision Contents

PathSize
llvm/
lib/
Target/
X86/
2 lines
test/
CodeGen/
X86/
2 lines

Diff 273217

llvm/lib/Target/X86/X86MCInstLower.cpp

Show First 20 Lines • Show All 512 Lines • ▼ Show 20 Linesvoid X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
case X86::MULX32Hrm: case X86::MULX32Hrm:
case X86::MULX64Hrr: case X86::MULX64Hrr:
case X86::MULX64Hrm: { case X86::MULX64Hrm: {
// Turn into regular MULX by duplicating the destination. // Turn into regular MULX by duplicating the destination.
unsigned NewOpc; unsigned NewOpc;
switch (OutMI.getOpcode()) { switch (OutMI.getOpcode()) {
default: llvm_unreachable("Invalid opcode"); default: llvm_unreachable("Invalid opcode");
case X86::MULX32Hrr: NewOpc = X86::MULX32rr; break; case X86::MULX32Hrr: NewOpc = X86::MULX32rr; break;
case X86::MULX32Hrm: NewOpc = X86::MULX32rr; break; case X86::MULX32Hrm: NewOpc = X86::MULX32rm; break;
case X86::MULX64Hrr: NewOpc = X86::MULX64rr; break; case X86::MULX64Hrr: NewOpc = X86::MULX64rr; break;
case X86::MULX64Hrm: NewOpc = X86::MULX64rm; break; case X86::MULX64Hrm: NewOpc = X86::MULX64rm; break;
} }
OutMI.setOpcode(NewOpc); OutMI.setOpcode(NewOpc);
// Duplicate the destination. // Duplicate the destination.
unsigned DestReg = OutMI.getOperand(0).getReg(); unsigned DestReg = OutMI.getOperand(0).getReg();
OutMI.insert(OutMI.begin(), MCOperand::createReg(DestReg)); OutMI.insert(OutMI.begin(), MCOperand::createReg(DestReg));
break; break;
▲ Show 20 Lines • Show All 2,089 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/bug80500.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686 -mcpu=skylake | FileCheck %s ; RUN: llc < %s -mtriple=i686 -mcpu=skylake | FileCheck %s
; Fix for a typo introduced by D80500 ; Fix for a typo introduced by D80500
define i32 @load_fold_udiv1(i32* %p) { define i32 @load_fold_udiv1(i32* %p) {
; CHECK-LABEL: load_fold_udiv1: ; CHECK-LABEL: load_fold_udiv1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl $-2004318071, %edx # imm = 0x88888889 ; CHECK-NEXT: movl $-2004318071, %edx # imm = 0x88888889
; CHECK-NEXT: mulxl %eax, %eax, %eax ; CHECK-NEXT: mulxl (%eax), %eax, %eax
; CHECK-NEXT: shrl $3, %eax ; CHECK-NEXT: shrl $3, %eax
; CHECK-NEXT: retl ; CHECK-NEXT: retl
%v = load i32, i32* %p, align 4 %v = load i32, i32* %p, align 4
%ret = udiv i32 %v, 15 %ret = udiv i32 %v, 15
ret i32 %ret ret i32 %ret
} }