In the file PPCInstrInfo.cpp:
1449 bool PPCInstrInfo::PredicateInstruction(MachineInstr &MI, 1450 ArrayRef<MachineOperand> Pred) const { 1451 unsigned OpC = MI.getOpcode(); 1452 if (OpC == PPC::BLR || OpC == PPC::BLR8) { 1453 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) { 1454 bool isPPC64 = Subtarget.isPPC64(); 1455 MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZLR8 : PPC::BDNZLR) 1456 : (isPPC64 ? PPC::BDZLR8 : PPC::BDZLR))); 1457 } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) { ... }
Above code only modify the opcode, but doesn't consider the implicit register for the new opcode.
For example, if MI is BLR implicit $lr, implicit $rm, in the line 1455. We use MI.setDesc() to convert the BLR to BDZLR.
We will get:
BDZLR implicit $lr, implicit $rm
But we don't realize BLR and BDZLR have different implicit register. In fact, the right instruction should be below:
BDZLR implicit-def $ctr, implicit $ctr, implicit $lr, implicit $rm
IsNeedFixImplicitOps -> needImplicitOpsFix