[Power10] Implement Vector Insert Builtins in LLVM/Clang

[biplmish]

Summary

This patch implements builtins for the following prototypes:

vector unsigned char vec_insertl (unsigned char, vector unsigned char, unsigned int);
vector unsigned short vec_insertl (unsigned short, vector unsigned short, unsigned int);
vector unsigned int vec_insertl (unsigned int, vector unsigned int, unsigned int);
vector unsigned long long vec_insertl (unsigned long long, vector unsigned long long, unsigned int);
vector unsigned char vec_insertl (vector unsigned char, vector unsigned char, unsigned int;
vector unsigned short vec_insertl (vector unsigned short, vector unsigned short, unsigned int);
vector unsigned int vec_insertl (vector unsigned int, vector unsigned int, unsigned int);

vector unsigned char vec_inserth (unsigned char, vector unsigned char, unsigned int);
vector unsigned short vec_inserth (unsigned short, vector unsigned short, unsigned int);
vector unsigned int vec_inserth (unsigned int, vector unsigned int, unsigned int);
vector unsigned long long vec_inserth (unsigned long long, vector unsigned long long, unsigned int);
vector unsigned char vec_inserth (vector unsigned char, vector unsigned char, unsigned int);
vector unsigned short vec_inserth (vector unsigned short, vector unsigned short, unsigned int);
vector unsigned int vec_inserth (vector unsigned int, vector unsigned int, unsigned int);

[lei]

clang/lib/Headers/altivec.h

16863

vec_insertl( should be on the next line. Same as previous definitions.
Same comment for all the def below this one.

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

555

Please match the indentation of these new instructions to the ones above and below them.

560

nit: this line should match right under int_ppc_altivec_vinsbvlx.

[amyk]

clang/include/clang/Basic/BuiltinsPPC.def

309

End with a period.

llvm/include/llvm/IR/IntrinsicsPowerPC.td

429

Nit: // P10 Vector Insert.

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

594

The indentation of VINSBLX and instructions below looks okay to me, but move the i64:$rA . . . sections below (int_ppc_altivec_ . . .

[biplmish]

clang/lib/Headers/altivec.h

16863

This is based on the clang-format update. Changes to this gives warnings from clang-format.

[biplmish]

Review comments incorporated.

[biplmish]

Update the builtin implementation to incorporate instruction changes.

[lei]

clang/lib/Headers/altivec.h

16862

consistency. bring vec_insert.. to next line same as previous def.
same for all such below.

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

522

all these indentation is off by 1.

[amyk]

I think aside from Lei's indentation nits, I think LGTM.

[lei]

I will commit this for Biplob since he does't have commit access yet.

[lei]

clang/test/CodeGen/builtins-ppc-p10vector.c

12

I just noticed this. There is no need to add this RUN line since it's the same as the one on line 2. Please post a patch to remove this and update tests to use the default CHECK.

[biplmish]

clang/test/CodeGen/builtins-ppc-p10vector.c

12

Sure. However there are also tests in Line 125,133 etc which would need modification.

Can we also do "RUN: -o - | FileCheck %s -check-prefixes=CHECK,CHECK-LE" in the test1 and remove the test3 so that the tests work in the current format.

[lei]

clang/test/CodeGen/builtins-ppc-p10vector.c

12

Please make all the necessary modification all affected testcases to use CHECK instead of CHECK-LE.

clang/include/clang/Basic/BuiltinsPPC.def

 // P10 Vector Parallel Bits built-ins.
 BUILTIN(__builtin_altivec_vpdepd, "V2ULLiV2ULLiV2ULLi", "")
 BUILTIN(__builtin_altivec_vpextd, "V2ULLiV2ULLiV2ULLi", "")
 
 // P10 Vector Clear Bytes built-ins.
 BUILTIN(__builtin_altivec_vclrlb, "V16cV16cUi", "")
 BUILTIN(__builtin_altivec_vclrrb, "V16cV16cUi", "")
 
+// P10 Vector insert built-ins
+BUILTIN(__builtin_altivec_vinsblx, "V16UcULLiULLi", "")
+BUILTIN(__builtin_altivec_vinsbrx, "V16UcULLiULLi", "")
+BUILTIN(__builtin_altivec_vinshlx, "V8UsULLiULLi", "")
+BUILTIN(__builtin_altivec_vinshrx, "V8UsULLiULLi", "")
+BUILTIN(__builtin_altivec_vinswlx, "V4UiULLiULLi", "")
+BUILTIN(__builtin_altivec_vinswrx, "V4UiULLiULLi", "")
+BUILTIN(__builtin_altivec_vinsdlx, "V2ULLiULLiULLi", "")
+BUILTIN(__builtin_altivec_vinsdrx, "V2ULLiULLiULLi", "")
+BUILTIN(__builtin_altivec_vinsbvlx, "V16UcULLiV16Uc", "")
+BUILTIN(__builtin_altivec_vinsbvrx, "V16UcULLiV16Uc", "")
+BUILTIN(__builtin_altivec_vinshvlx, "V8UsULLiV8Us", "")
+BUILTIN(__builtin_altivec_vinshvrx, "V8UsULLiV8Us", "")
+BUILTIN(__builtin_altivec_vinswvlx, "V4UiULLiV4Ui", "")
+BUILTIN(__builtin_altivec_vinswvrx, "V4UiULLiV4Ui", "")
+
 // VSX built-ins.
 
 BUILTIN(__builtin_vsx_lxvd2x, "V2divC*", "")
 BUILTIN(__builtin_vsx_lxvw4x, "V4iivC*", "")
 BUILTIN(__builtin_vsx_lxvd2x_be, "V2dSLLivC*", "")
 BUILTIN(__builtin_vsx_lxvw4x_be, "V4iSLLivC*", "")
 
 BUILTIN(__builtin_vsx_stxvd2x, "vV2div*", "")

clang/lib/Headers/altivec.h

 static __inline__ vector unsigned char __ATTRS_o_ai
 vec_clrr(vector unsigned char __a, unsigned int __n) {
 #ifdef __LITTLE_ENDIAN__
   return __builtin_altivec_vclrlb((vector signed char)__a, __n);
 #else
   return __builtin_altivec_vclrrb((vector signed char)__a, __n);
 #endif
 }
+
+/* vec_insertl */
+
+static __inline__ vector unsigned char __ATTRS_o_ai
+vec_insertl(unsigned char __a, vector unsigned char __b, unsigned int __c) {
+#ifdef __LITTLE_ENDIAN__
+  return __builtin_altivec_vinsbrx(__c, __a);
+#else
+  return __builtin_altivec_vinsblx(__c, __a);
+#endif
+}
+
+static __inline__ vector unsigned short __ATTRS_o_ai
+vec_insertl(unsigned short __a, vector unsigned short __b, unsigned int __c) {
+#ifdef __LITTLE_ENDIAN__
+  return __builtin_altivec_vinshrx(__c, __a);
+#else
+  return __builtin_altivec_vinshlx(__c, __a);
+#endif
+}
+
+static __inline__ vector unsigned int __ATTRS_o_ai
+vec_insertl(unsigned int __a, vector unsigned int __b, unsigned int __c) {
+#ifdef __LITTLE_ENDIAN__
+  return __builtin_altivec_vinswrx(__c, __a);
+#else
+  return __builtin_altivec_vinswlx(__c, __a);
+#endif
+}
+
+static __inline__ vector unsigned long long __ATTRS_o_ai vec_insertl(
+    unsigned long long __a, vector unsigned long long __b, unsigned int __c) {
+#ifdef __LITTLE_ENDIAN__
+  return __builtin_altivec_vinsdrx(__c, __a);
+#else
+  return __builtin_altivec_vinsdlx(__c, __a);
+#endif
+}
+
+static __inline__ vector unsigned char __ATTRS_o_ai vec_insertl(
+    vector unsigned char __a, vector unsigned char __b, unsigned int __c) {
+#ifdef __LITTLE_ENDIAN__
+  return __builtin_altivec_vinsbvrx(__c, __a);
+#else
+  return __builtin_altivec_vinsbvlx(__c, __a);
+#endif
+}
+
+static __inline__ vector unsigned short __ATTRS_o_ai vec_insertl(
+    vector unsigned short __a, vector unsigned short __b, unsigned int __c) {
+#ifdef __LITTLE_ENDIAN__
+  return __builtin_altivec_vinshvrx(__c, __a);
+#else
+  return __builtin_altivec_vinshvlx(__c, __a);
+#endif
+}
+
+static __inline__ vector unsigned int __ATTRS_o_ai vec_insertl(
+    vector unsigned int __a, vector unsigned int __b, unsigned int __c) {
+#ifdef __LITTLE_ENDIAN__
+  return __builtin_altivec_vinswvrx(__c, __a);
+#else
+  return __builtin_altivec_vinswvlx(__c, __a);
+#endif
+}
+
+/* vec_inserth */
+
+static __inline__ vector unsigned char __ATTRS_o_ai
+vec_inserth(unsigned char __a, vector unsigned char __b, unsigned int __c) {
+#ifdef __LITTLE_ENDIAN__
+  return __builtin_altivec_vinsblx(__c, __a);
+#else
+  return __builtin_altivec_vinsbrx(__c, __a);
+#endif
+}
+
+static __inline__ vector unsigned short __ATTRS_o_ai
+vec_inserth(unsigned short __a, vector unsigned short __b, unsigned int __c) {
+#ifdef __LITTLE_ENDIAN__
+  return __builtin_altivec_vinshlx(__c, __a);
+#else
+  return __builtin_altivec_vinshrx(__c, __a);
+#endif
+}
+
+static __inline__ vector unsigned int __ATTRS_o_ai
+vec_inserth(unsigned int __a, vector unsigned int __b, unsigned int __c) {
+#ifdef __LITTLE_ENDIAN__
+  return __builtin_altivec_vinswlx(__c, __a);
+#else
+  return __builtin_altivec_vinswrx(__c, __a);
+#endif
+}
+
+static __inline__ vector unsigned long long __ATTRS_o_ai vec_inserth(
+    unsigned long long __a, vector unsigned long long __b, unsigned int __c) {
+#ifdef __LITTLE_ENDIAN__
+  return __builtin_altivec_vinsdlx(__c, __a);
+#else
+  return __builtin_altivec_vinsdrx(__c, __a);
+#endif
+}
+
+static __inline__ vector unsigned char __ATTRS_o_ai vec_inserth(
+    vector unsigned char __a, vector unsigned char __b, unsigned int __c) {
+#ifdef __LITTLE_ENDIAN__
+  return __builtin_altivec_vinsbvlx(__c, __a);
+#else
+  return __builtin_altivec_vinsbvrx(__c, __a);
+#endif
+}
+
+static __inline__ vector unsigned short __ATTRS_o_ai vec_inserth(
+    vector unsigned short __a, vector unsigned short __b, unsigned int __c) {
+#ifdef __LITTLE_ENDIAN__
+  return __builtin_altivec_vinshvlx(__c, __a);
+#else
+  return __builtin_altivec_vinshvrx(__c, __a);
+#endif
+}
+
+static __inline__ vector unsigned int __ATTRS_o_ai vec_inserth(
+    vector unsigned int __a, vector unsigned int __b, unsigned int __c) {
+#ifdef __LITTLE_ENDIAN__
+  return __builtin_altivec_vinswvlx(__c, __a);
+#else
+  return __builtin_altivec_vinswvrx(__c, __a);
+#endif
+}
 #endif /* __POWER10_VECTOR__ */
 
 #undef __ATTRS_o_ai
 
 #endif /* __ALTIVEC_H */

clang/test/CodeGen/builtins-ppc-p10vector.c

 // REQUIRES: powerpc-registered-target
 // RUN: %clang_cc1 -target-feature +vsx -target-feature +altivec \
 // RUN:   -target-cpu pwr10 -triple powerpc64le-unknown-unknown -emit-llvm %s \
 // RUN:   -o - | FileCheck %s
 
+// RUN: %clang_cc1 -target-feature +vsx -target-feature +altivec \
+// RUN:   -target-cpu pwr10 -triple powerpc64-unknown-unknown -emit-llvm %s \
+// RUN:   -o - | FileCheck %s -check-prefix=CHECK-BE
+
+// RUN: %clang_cc1 -target-feature +vsx -target-feature +altivec \
+// RUN:   -target-cpu pwr10 -triple powerpc64le-unknown-unknown -emit-llvm %s \
+// RUN:   -o - | FileCheck %s -check-prefix=CHECK-LE
+
 #include <altivec.h>
 
 vector signed char vsca;
-vector unsigned char vuca;
-vector unsigned short vusa;
-vector unsigned int vuia;
+vector unsigned char vuca, vucb;
+vector unsigned short vusa, vusb;
+vector unsigned int vuia, vuib;
 vector unsigned long long vulla, vullb;
-unsigned int uia;
+unsigned int uia, uib;
+unsigned char uca;
+unsigned short usa;
+unsigned long long ulla;
 
 vector unsigned long long test_vpdepd(void) {
   // CHECK: @llvm.ppc.altivec.vpdepd(<2 x i64>
   // CHECK-NEXT: ret <2 x i64>
   return vec_pdep(vulla, vullb);
 }
 
 vector unsigned long long test_vpextd(void) {

 
 vector unsigned char test_vec_clrr_uc(void) {
   // CHECK-BE: @llvm.ppc.altivec.vclrrb(<16 x i8>
   // CHECK-BE-NEXT: ret <16 x i8>
   // CHECK-LE: @llvm.ppc.altivec.vclrlb(<16 x i8>
   // CHECK-LE-NEXT: ret <16 x i8>
   return vec_clrr(vuca, uia);
 }
+
+vector unsigned char test_vec_insertl_uc(void) {
+  // CHECK-BE: @llvm.ppc.altivec.vinsblx(i64 %{{.+}}, i64
+  // CHECK-BE-NEXT: ret <16 x i8>
+  // CHECK-LE: @llvm.ppc.altivec.vinsbrx(i64 %{{.+}}, i64
+  // CHECK-LE-NEXT: ret <16 x i8>
+  return vec_insertl(uca, vuca, uia);
+}
+
+vector unsigned short test_vec_insertl_us(void) {
+  // CHECK-BE: @llvm.ppc.altivec.vinshlx(i64 %{{.+}}, i64
+  // CHECK-BE-NEXT: ret <8 x i16>
+  // CHECK-LE: @llvm.ppc.altivec.vinshrx(i64 %{{.+}}, i64
+  // CHECK-LE-NEXT: ret <8 x i16>
+  return vec_insertl(usa, vusa, uia);
+}
+
+vector unsigned int test_vec_insertl_ui(void) {
+  // CHECK-BE: @llvm.ppc.altivec.vinswlx(i64 %{{.+}}, i64
+  // CHECK-BE-NEXT: ret <4 x i32>
+  // CHECK-LE: @llvm.ppc.altivec.vinswrx(i64 %{{.+}}, i64
+  // CHECK-LE-NEXT: ret <4 x i32>
+  return vec_insertl(uib, vuia, uia);
+}
+
+vector unsigned long long test_vec_insertl_ul(void) {
+  // CHECK-BE: @llvm.ppc.altivec.vinsdlx(i64 %{{.+}}, i64
+  // CHECK-BE-NEXT: ret <2 x i64>
+  // CHECK-LE: @llvm.ppc.altivec.vinsdrx(i64 %{{.+}}, i64
+  // CHECK-LE-NEXT: ret <2 x i64>
+  return vec_insertl(ulla, vulla, uia);
+}
+
+vector unsigned char test_vec_insertl_ucv(void) {
+  // CHECK-BE: @llvm.ppc.altivec.vinsbvlx(i64 %{{.+}}, <16 x i8>
+  // CHECK-BE-NEXT: ret <16 x i8>
+  // CHECK-LE: @llvm.ppc.altivec.vinsbvrx(i64 %{{.+}}, <16 x i8>
+  // CHECK-LE-NEXT: ret <16 x i8>
+  return vec_insertl(vuca, vucb, uia);
+}
+
+vector unsigned short test_vec_insertl_usv(void) {
+  // CHECK-BE: @llvm.ppc.altivec.vinshvlx(i64 %{{.+}}, <8 x i16>
+  // CHECK-BE-NEXT: ret <8 x i16>
+  // CHECK-LE: @llvm.ppc.altivec.vinshvrx(i64 %{{.+}}, <8 x i16>
+  // CHECK-LE-NEXT: ret <8 x i16>
+  return vec_insertl(vusa, vusb, uia);
+}
+
+vector unsigned int test_vec_insertl_uiv(void) {
+  // CHECK-BE: @llvm.ppc.altivec.vinswvlx(i64 %{{.+}}, <4 x i32>
+  // CHECK-BE-NEXT: ret <4 x i32>
+  // CHECK-LE: @llvm.ppc.altivec.vinswvrx(i64 %{{.+}}, <4 x i32>
+  // CHECK-LE-NEXT: ret <4 x i32>
+  return vec_insertl(vuia, vuib, uia);
+}
+
+vector unsigned char test_vec_inserth_uc(void) {
+  // CHECK-BE: @llvm.ppc.altivec.vinsbrx(i64 %{{.+}}, i64
+  // CHECK-BE-NEXT: ret <16 x i8>
+  // CHECK-LE: @llvm.ppc.altivec.vinsblx(i64 %{{.+}}, i64
+  // CHECK-LE-NEXT: ret <16 x i8>
+  return vec_inserth(uca, vuca, uia);
+}
+
+vector unsigned short test_vec_inserth_us(void) {
+  // CHECK-BE: @llvm.ppc.altivec.vinshrx(i64 %{{.+}}, i64
+  // CHECK-BE-NEXT: ret <8 x i16>
+  // CHECK-LE: @llvm.ppc.altivec.vinshlx(i64 %{{.+}}, i64
+  // CHECK-LE-NEXT: ret <8 x i16>
+  return vec_inserth(usa, vusa, uia);
+}
+
+vector unsigned int test_vec_inserth_ui(void) {
+  // CHECK-BE: @llvm.ppc.altivec.vinswrx(i64 %{{.+}}, i64
+  // CHECK-BE-NEXT: ret <4 x i32>
+  // CHECK-LE: @llvm.ppc.altivec.vinswlx(i64 %{{.+}}, i64
+  // CHECK-LE-NEXT: ret <4 x i32>
+  return vec_inserth(uib, vuia, uia);
+}
+
+vector unsigned long long test_vec_inserth_ul(void) {
+  // CHECK-BE: @llvm.ppc.altivec.vinsdrx(i64 %{{.+}}, i64
+  // CHECK-BE-NEXT: ret <2 x i64>
+  // CHECK-LE: @llvm.ppc.altivec.vinsdlx(i64 %{{.+}}, i64
+  // CHECK-LE-NEXT: ret <2 x i64>
+  return vec_inserth(ulla, vulla, uia);
+}
+
+vector unsigned char test_vec_inserth_ucv(void) {
+  // CHECK-BE: @llvm.ppc.altivec.vinsbvrx(i64 %{{.+}}, <16 x i8>
+  // CHECK-BE-NEXT: ret <16 x i8>
+  // CHECK-LE: @llvm.ppc.altivec.vinsbvlx(i64 %{{.+}}, <16 x i8>
+  // CHECK-LE-NEXT: ret <16 x i8>
+  return vec_inserth(vuca, vucb, uia);
+}
+
+vector unsigned short test_vec_inserth_usv(void) {
+  // CHECK-BE: @llvm.ppc.altivec.vinshvrx(i64 %{{.+}}, <8 x i16>
+  // CHECK-BE-NEXT: ret <8 x i16>
+  // CHECK-LE: @llvm.ppc.altivec.vinshvlx(i64 %{{.+}}, <8 x i16>
+  // CHECK-LE-NEXT: ret <8 x i16>
+  return vec_inserth(vusa, vusb, uia);
+}
+
+vector unsigned int test_vec_inserth_uiv(void) {
+  // CHECK-BE: @llvm.ppc.altivec.vinswvrx(i64 %{{.+}}, <4 x i32>
+  // CHECK-BE-NEXT: ret <4 x i32>
+  // CHECK-LE: @llvm.ppc.altivec.vinswvlx(i64 %{{.+}}, <4 x i32>
+  // CHECK-LE-NEXT: ret <4 x i32>
+  return vec_inserth(vuia, vuib, uia);
+}

llvm/include/llvm/IR/IntrinsicsPowerPC.td

let TargetPrefix = "ppc" in {  // All intrinsics start with "llvm.ppc.".
 
    // P10 Vector Clear Bytes
    def int_ppc_altivec_vclrlb :  GCCBuiltin<"__builtin_altivec_vclrlb">,
                Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty],
                          [IntrNoMem]>;
    def int_ppc_altivec_vclrrb :  GCCBuiltin<"__builtin_altivec_vclrrb">,
                Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty],
                          [IntrNoMem]>;
+
+  //P10 Vector Insert
+  def int_ppc_altivec_vinsblx : GCCBuiltin<"__builtin_altivec_vinsblx">,
+              Intrinsic<[llvm_v16i8_ty], [llvm_i64_ty, llvm_i64_ty],
+                        [IntrNoMem]>;
+  def int_ppc_altivec_vinsbrx : GCCBuiltin<"__builtin_altivec_vinsbrx">,
+              Intrinsic<[llvm_v16i8_ty], [llvm_i64_ty, llvm_i64_ty],
+                        [IntrNoMem]>;
+  def int_ppc_altivec_vinshlx : GCCBuiltin<"__builtin_altivec_vinshlx">,
+              Intrinsic<[llvm_v8i16_ty], [llvm_i64_ty, llvm_i64_ty],
+                        [IntrNoMem]>;
+  def int_ppc_altivec_vinshrx : GCCBuiltin<"__builtin_altivec_vinshrx">,
+              Intrinsic<[llvm_v8i16_ty], [llvm_i64_ty, llvm_i64_ty],
+                        [IntrNoMem]>;
+  def int_ppc_altivec_vinswlx : GCCBuiltin<"__builtin_altivec_vinswlx">,
+              Intrinsic<[llvm_v4i32_ty], [llvm_i64_ty, llvm_i64_ty],
+                        [IntrNoMem]>;
+  def int_ppc_altivec_vinswrx : GCCBuiltin<"__builtin_altivec_vinswrx">,
+              Intrinsic<[llvm_v4i32_ty], [llvm_i64_ty, llvm_i64_ty],
+                        [IntrNoMem]>;
+  def int_ppc_altivec_vinsdlx : GCCBuiltin<"__builtin_altivec_vinsdlx">,
+              Intrinsic<[llvm_v2i64_ty], [llvm_i64_ty, llvm_i64_ty],
+                        [IntrNoMem]>;
+  def int_ppc_altivec_vinsdrx : GCCBuiltin<"__builtin_altivec_vinsdrx">,
+              Intrinsic<[llvm_v2i64_ty], [llvm_i64_ty, llvm_i64_ty],
+                        [IntrNoMem]>;
+  def int_ppc_altivec_vinsbvlx : GCCBuiltin<"__builtin_altivec_vinsbvlx">,
+              Intrinsic<[llvm_v16i8_ty], [llvm_i64_ty, llvm_v16i8_ty],
+                        [IntrNoMem]>;
+  def int_ppc_altivec_vinsbvrx : GCCBuiltin<"__builtin_altivec_vinsbvrx">,
+              Intrinsic<[llvm_v16i8_ty], [llvm_i64_ty, llvm_v16i8_ty],
+                        [IntrNoMem]>;
+  def int_ppc_altivec_vinshvlx : GCCBuiltin<"__builtin_altivec_vinshvlx">,
+              Intrinsic<[llvm_v8i16_ty], [llvm_i64_ty, llvm_v8i16_ty],
+                        [IntrNoMem]>;
+  def int_ppc_altivec_vinshvrx : GCCBuiltin<"__builtin_altivec_vinshvrx">,
+              Intrinsic<[llvm_v8i16_ty], [llvm_i64_ty, llvm_v8i16_ty],
+                        [IntrNoMem]>;
+  def int_ppc_altivec_vinswvlx : GCCBuiltin<"__builtin_altivec_vinswvlx">,
+              Intrinsic<[llvm_v4i32_ty], [llvm_i64_ty, llvm_v4i32_ty],
+                        [IntrNoMem]>;
+  def int_ppc_altivec_vinswvrx : GCCBuiltin<"__builtin_altivec_vinswvrx">,
+              Intrinsic<[llvm_v4i32_ty], [llvm_i64_ty, llvm_v4i32_ty],
+                        [IntrNoMem]>;
 }
 
 // Vector average.
 def int_ppc_altivec_vavgsb : PowerPC_Vec_BBB_Intrinsic<"vavgsb">;
 def int_ppc_altivec_vavgsh : PowerPC_Vec_HHH_Intrinsic<"vavgsh">;
 def int_ppc_altivec_vavgsw : PowerPC_Vec_WWW_Intrinsic<"vavgsw">;
 def int_ppc_altivec_vavgub : PowerPC_Vec_BBB_Intrinsic<"vavgub">;
 def int_ppc_altivec_vavguh : PowerPC_Vec_HHH_Intrinsic<"vavguh">;

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

let Predicates = [PCRelativeMemops], AddedComplexity = 500 in {
 
   // If the PPCmatpcreladdr node is not caught by any other pattern it should be
   // caught here and turned into a paddi instruction to materialize the address.
   def : Pat<(PPCmatpcreladdr pcreladdr:$addr), (PADDI8pc 0, $addr)>;
 }
 
 let Predicates = [IsISA3_1] in {
    def VPDEPD : VXForm_1<1485, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
                          "vpdepd $vD, $vA, $vB", IIC_VecGeneral,
                          [(set v2i64:$vD,
                          (int_ppc_altivec_vpdepd v2i64:$vA, v2i64:$vB))]>;
    def VPEXTD : VXForm_1<1421, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
                          "vpextd $vD, $vA, $vB", IIC_VecGeneral,
                          [(set v2i64:$vD,
                          (int_ppc_altivec_vpextd v2i64:$vA, v2i64:$vB))]>;
    def PDEPD : XForm_6<31, 156, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
                        "pdepd $rA, $rS, $rB", IIC_IntGeneral,
let Predicates = [IsISA3_1] in {
    def VCLRLB : VXForm_1<397, (outs vrrc:$vD), (ins vrrc:$vA, gprc:$rB),
                          "vclrlb $vD, $vA, $rB", IIC_VecGeneral,
                          [(set v16i8:$vD,
                                (int_ppc_altivec_vclrlb v16i8:$vA, i32:$rB))]>;
    def VCLRRB : VXForm_1<461, (outs vrrc:$vD), (ins vrrc:$vA, gprc:$rB),
                          "vclrrb $vD, $vA, $rB", IIC_VecGeneral,
                          [(set v16i8:$vD,
                                (int_ppc_altivec_vclrrb v16i8:$vA, i32:$rB))]>;
+  def VINSBVLX :
+    VXForm_1
+    <15, (outs vrrc:$vD), (ins g8rc:$rA, vrrc:$vB),
+     "vinsbvlx $vD, $rA, $vB", IIC_VecGeneral,
+     [(set v16i8:$vD, (int_ppc_altivec_vinsbvlx
+     i64:$rA, v16i8:$vB))]>;
+  def VINSBVRX :
+    VXForm_1
+    <271, (outs vrrc:$vD), (ins g8rc:$rA, vrrc:$vB),
+     "vinsbvrx $vD, $rA, $vB", IIC_VecGeneral,
+     [(set v16i8:$vD, (int_ppc_altivec_vinsbvrx
+     i64:$rA, v16i8:$vB))]>;
+  def VINSHVLX :
+    VXForm_1
+    <79, (outs vrrc:$vD), (ins g8rc:$rA, vrrc:$vB),
+     "vinshvlx $vD, $rA, $vB", IIC_VecGeneral,
+     [(set v8i16:$vD, (int_ppc_altivec_vinshvlx
+     i64:$rA, v8i16:$vB))]>;
+  def VINSHVRX :
+    VXForm_1
+    <335, (outs vrrc:$vD), (ins g8rc:$rA, vrrc:$vB),
+     "vinshvrx $vD, $rA, $vB", IIC_VecGeneral,
+     [(set v8i16:$vD, (int_ppc_altivec_vinshvrx
+     i64:$rA, v8i16:$vB))]>;
+  def VINSWVLX :
+    VXForm_1
+    <143, (outs vrrc:$vD), (ins g8rc:$rA, vrrc:$vB),
+     "vinswvlx $vD, $rA, $vB", IIC_VecGeneral,
+     [(set v4i32:$vD, (int_ppc_altivec_vinswvlx
+     i64:$rA, v4i32:$vB))]>;
+  def VINSWVRX :
+    VXForm_1
+    <399, (outs vrrc:$vD), (ins g8rc:$rA, vrrc:$vB),
+     "vinswvrx $vD, $rA, $vB", IIC_VecGeneral,
+     [(set v4i32:$vD, (int_ppc_altivec_vinswvrx
+     i64:$rA, v4i32:$vB))]>;
+  def VINSBLX : VXForm_1<527, (outs vrrc:$vD), (ins g8rc:$rA, g8rc:$rB),
+                         "vinsblx $vD, $rA, $rB", IIC_VecGeneral,
+                         [(set v16i8:$vD, (int_ppc_altivec_vinsblx
+                         i64:$rA, i64:$rB))]>;
+  def VINSBRX : VXForm_1<783, (outs vrrc:$vD), (ins g8rc:$rA, g8rc:$rB),
+                         "vinsbrx $vD, $rA, $rB", IIC_VecGeneral,
+                         [(set v16i8:$vD, (int_ppc_altivec_vinsbrx
+                         i64:$rA, i64:$rB))]>;
+  def VINSHLX : VXForm_1<591, (outs vrrc:$vD), (ins g8rc:$rA, g8rc:$rB),
+                         "vinshlx $vD, $rA, $rB", IIC_VecGeneral,
+                         [(set v8i16:$vD, (int_ppc_altivec_vinshlx
+                         i64:$rA, i64:$rB))]>;
+  def VINSHRX : VXForm_1<847, (outs vrrc:$vD), (ins g8rc:$rA, g8rc:$rB),
+                         "vinshrx $vD, $rA, $rB", IIC_VecGeneral,
+                         [(set v8i16:$vD, (int_ppc_altivec_vinshrx
+                         i64:$rA, i64:$rB))]>;
+  def VINSWLX : VXForm_1<655, (outs vrrc:$vD), (ins g8rc:$rA, g8rc:$rB),
+                         "vinswlx $vD, $rA, $rB", IIC_VecGeneral,
+                         [(set v4i32:$vD, (int_ppc_altivec_vinswlx
+                         i64:$rA, i64:$rB))]>;
+  def VINSWRX : VXForm_1<911, (outs vrrc:$vD), (ins g8rc:$rA, g8rc:$rB),
+                         "vinswrx $vD, $rA, $rB", IIC_VecGeneral,
+                         [(set v4i32:$vD, (int_ppc_altivec_vinswrx
+                         i64:$rA, i64:$rB))]>;
+  def VINSDLX : VXForm_1<719, (outs vrrc:$vD), (ins g8rc:$rA, g8rc:$rB),
+                         "vinsdlx $vD, $rA, $rB", IIC_VecGeneral,
+                         [(set v2i64:$vD, (int_ppc_altivec_vinsdlx
+                         i64:$rA, i64:$rB))]>;
+  def VINSDRX : VXForm_1<975, (outs vrrc:$vD), (ins g8rc:$rA, g8rc:$rB),
+                         "vinsdrx $vD, $rA, $rB", IIC_VecGeneral,
+                         [(set v2i64:$vD, (int_ppc_altivec_vinsdrx
+                         i64:$rA, i64:$rB))]>;
 }
 
 //---------------------------- Anonymous Patterns ----------------------------//
 let Predicates = [IsISA3_1] in {
   def : Pat<(v16i8 (int_ppc_vsx_xxgenpcvbm v16i8:$VRB, imm:$IMM)),
             (v16i8 (COPY_TO_REGCLASS (XXGENPCVBM $VRB, imm:$IMM), VRRC))>;
   def : Pat<(v8i16 (int_ppc_vsx_xxgenpcvhm v8i16:$VRB, imm:$IMM)),
             (v8i16 (COPY_TO_REGCLASS (XXGENPCVHM $VRB, imm:$IMM), VRRC))>;
   def : Pat<(v4i32 (int_ppc_vsx_xxgenpcvwm v4i32:$VRB, imm:$IMM)),
             (v4i32 (COPY_TO_REGCLASS (XXGENPCVWM $VRB, imm:$IMM), VRRC))>;
   def : Pat<(v2i64 (int_ppc_vsx_xxgenpcvdm v2i64:$VRB, imm:$IMM)),
             (v2i64 (COPY_TO_REGCLASS (XXGENPCVDM $VRB, imm:$IMM), VRRC))>;
 }

llvm/test/CodeGen/PowerPC/p10-permute-ops.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -mcpu=pwr10 \
+; RUN:   -ppc-vsr-nums-as-vr -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
+
+; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -mcpu=pwr10 \
+; RUN:   -ppc-vsr-nums-as-vr -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s
+
+define <16 x i8> @testVINSBLX(i64 %a, i64 %b) {
+; CHECK-LABEL: testVINSBLX:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vinsblx v2, r3, r4
+; CHECK-NEXT:    blr
+entry:
+  %0 = tail call <16 x i8> @llvm.ppc.altivec.vinsblx(i64 %a, i64 %b)
+  ret <16 x i8> %0
+}
+declare <16 x i8> @llvm.ppc.altivec.vinsblx(i64, i64)
+
+define <16 x i8> @testVINSBRX(i64 %a, i64 %b) {
+; CHECK-LABEL: testVINSBRX:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vinsbrx v2, r3, r4
+; CHECK-NEXT:    blr
+entry:
+  %0 = tail call <16 x i8> @llvm.ppc.altivec.vinsbrx(i64 %a, i64 %b)
+  ret <16 x i8> %0
+}
+declare <16 x i8> @llvm.ppc.altivec.vinsbrx(i64, i64)
+
+define <8 x i16> @testVINSHLX(i64 %a, i64 %b) {
+; CHECK-LABEL: testVINSHLX:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vinshlx v2, r3, r4
+; CHECK-NEXT:    blr
+entry:
+  %0 = tail call <8 x i16> @llvm.ppc.altivec.vinshlx(i64 %a, i64 %b)
+  ret <8 x i16> %0
+}
+declare <8 x i16> @llvm.ppc.altivec.vinshlx(i64, i64)
+
+define <8 x i16> @testVINSHRX(i64 %a, i64 %b) {
+; CHECK-LABEL: testVINSHRX:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vinshrx v2, r3, r4
+; CHECK-NEXT:    blr
+entry:
+  %0 = tail call <8 x i16> @llvm.ppc.altivec.vinshrx(i64 %a, i64 %b)
+  ret <8 x i16> %0
+}
+declare <8 x i16> @llvm.ppc.altivec.vinshrx(i64, i64)
+
+define <4 x i32> @testVINSWLX(i64 %a, i64 %b) {
+; CHECK-LABEL: testVINSWLX:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vinswlx v2, r3, r4
+; CHECK-NEXT:    blr
+entry:
+  %0 = tail call <4 x i32> @llvm.ppc.altivec.vinswlx(i64 %a, i64 %b)
+  ret <4 x i32> %0
+}
+declare <4 x i32> @llvm.ppc.altivec.vinswlx(i64, i64)
+
+define <4 x i32> @testVINSWRX(i64 %a, i64 %b) {
+; CHECK-LABEL: testVINSWRX:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vinswrx v2, r3, r4
+; CHECK-NEXT:    blr
+entry:
+  %0 = tail call <4 x i32> @llvm.ppc.altivec.vinswrx(i64 %a, i64 %b)
+  ret <4 x i32> %0
+}
+declare <4 x i32> @llvm.ppc.altivec.vinswrx(i64, i64)
+
+define <2 x i64> @testVINSDLX(i64 %a, i64 %b) {
+; CHECK-LABEL: testVINSDLX:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vinsdlx v2, r3, r4
+; CHECK-NEXT:    blr
+entry:
+  %0 = tail call <2 x i64> @llvm.ppc.altivec.vinsdlx(i64 %a, i64 %b)
+  ret <2 x i64> %0
+}
+declare <2 x i64> @llvm.ppc.altivec.vinsdlx(i64, i64)
+
+define <2 x i64> @testVINSDRX(i64 %a, i64 %b) {
+; CHECK-LABEL: testVINSDRX:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vinsdrx v2, r3, r4
+; CHECK-NEXT:    blr
+entry:
+  %0 = tail call <2 x i64> @llvm.ppc.altivec.vinsdrx(i64 %a, i64 %b)
+  ret <2 x i64> %0
+}
+declare <2 x i64> @llvm.ppc.altivec.vinsdrx(i64, i64)
+
+define <16 x i8> @testVINSBVLX(i64 %a, <16 x i8> %b) {
+; CHECK-LABEL: testVINSBVLX:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vinsbvlx v2, r3, v2
+; CHECK-NEXT:    blr
+entry:
+  %0 = tail call <16 x i8> @llvm.ppc.altivec.vinsbvlx(i64 %a, <16 x i8> %b)
+  ret <16 x i8> %0
+}
+declare <16 x i8> @llvm.ppc.altivec.vinsbvlx(i64, <16 x i8>)
+
+define <16 x i8> @testVINSBVRX(i64 %a, <16 x i8> %b) {
+; CHECK-LABEL: testVINSBVRX:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vinsbvrx v2, r3, v2
+; CHECK-NEXT:    blr
+entry:
+  %0 = tail call <16 x i8> @llvm.ppc.altivec.vinsbvrx(i64 %a, <16 x i8> %b)
+  ret <16 x i8> %0
+}
+declare <16 x i8> @llvm.ppc.altivec.vinsbvrx(i64, <16 x i8>)
+
+define <8 x i16> @testVINSHVLX(i64 %a, <8 x i16> %b) {
+; CHECK-LABEL: testVINSHVLX:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vinshvlx v2, r3, v2
+; CHECK-NEXT:    blr
+entry:
+  %0 = tail call <8 x i16> @llvm.ppc.altivec.vinshvlx(i64 %a, <8 x i16> %b)
+  ret <8 x i16> %0
+}
+declare <8 x i16> @llvm.ppc.altivec.vinshvlx(i64, <8 x i16>)
+
+define <8 x i16> @testVINSHVRX(i64 %a, <8 x i16> %b) {
+; CHECK-LABEL: testVINSHVRX:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vinshvrx v2, r3, v2
+; CHECK-NEXT:    blr
+entry:
+  %0 = tail call <8 x i16> @llvm.ppc.altivec.vinshvrx(i64 %a, <8 x i16> %b)
+  ret <8 x i16> %0
+}
+declare <8 x i16> @llvm.ppc.altivec.vinshvrx(i64, <8 x i16>)
+
+define <4 x i32> @testVINSWVLX(i64 %a, <4 x i32> %b) {
+; CHECK-LABEL: testVINSWVLX:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vinswvlx v2, r3, v2
+; CHECK-NEXT:    blr
+entry:
+  %0 = tail call <4 x i32> @llvm.ppc.altivec.vinswvlx(i64 %a, <4 x i32> %b)
+  ret <4 x i32> %0
+}
+declare <4 x i32> @llvm.ppc.altivec.vinswvlx(i64, <4 x i32>)
+
+define <4 x i32> @testVINSWVRX(i64 %a, <4 x i32> %b) {
+; CHECK-LABEL: testVINSWVRX:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vinswvrx v2, r3, v2
+; CHECK-NEXT:    blr
+entry:
+  %0 = tail call <4 x i32> @llvm.ppc.altivec.vinswvrx(i64 %a, <4 x i32> %b)
+  ret <4 x i32> %0
+}
+declare <4 x i32> @llvm.ppc.altivec.vinswvrx(i64, <4 x i32>)

llvm/test/MC/Disassembler/PowerPC/p10insts.txt

 # CHECK xxgenpcvdm 0, 1, 2
 0xf0 0x02 0x0f 0x6a
 
 # CHECK: vclrlb 1, 4, 3
 0x10 0x24 0x19 0x8d
 
 # CHECK: vclrrb 1, 4, 3
 0x10 0x24 0x19 0xcd
+
+# CHECK: vinsbvlx 1, 3, 5
+0x10 0x23 0x28 0x0f
+
+# CHECK: vinsbvrx 1, 3, 5
+0x10 0x23 0x29 0x0f
+
+# CHECK: vinshvlx 1, 3, 5
+0x10 0x23 0x28 0x4f
+
+# CHECK: vinshvrx 1, 3, 5
+0x10 0x23 0x29 0x4f
+
+# CHECK: vinswvlx 1, 3, 5
+0x10 0x23 0x28 0x8f
+
+# CHECK: vinswvrx 1, 3, 5
+0x10 0x23 0x29 0x8f
+
+# CHECK: vinsblx 1, 2, 3
+0x10 0x22 0x1a 0x0f
+
+# CHECK: vinsbrx 1, 2, 3
+0x10 0x22 0x1b 0x0f
+
+# CHECK: vinshlx 1, 2, 3
+0x10 0x22 0x1a 0x4f
+
+# CHECK: vinshrx 1, 2, 3
+0x10 0x22 0x1b 0x4f
+
+# CHECK: vinswlx 1, 2, 3
+0x10 0x22 0x1a 0x8f
+
+# CHECK: vinswrx 1, 2, 3
+0x10 0x22 0x1b 0x8f
+
+# CHECK: vinsdlx 1, 2, 3
+0x10 0x22 0x1a 0xcf
+
+# CHECK: vinsdrx 1, 2, 3
+0x10 0x22 0x1b 0xcf

llvm/test/MC/PowerPC/p10.s

 # CHECK-LE: xxgenpcvdm 0, 1, 2                    # encoding: [0x6a,0x0f,0x02,0xf0]
             xxgenpcvdm 0, 1, 2
 # CHECK-BE: vclrlb 1, 4, 3                        # encoding: [0x10,0x24,0x19,0x8d]
 # CHECK-LE: vclrlb 1, 4, 3                        # encoding: [0x8d,0x19,0x24,0x10]
             vclrlb 1, 4, 3
 # CHECK-BE: vclrrb 1, 4, 3                        # encoding: [0x10,0x24,0x19,0xcd]
 # CHECK-LE: vclrrb 1, 4, 3                        # encoding: [0xcd,0x19,0x24,0x10]
             vclrrb 1, 4, 3
+# CHECK-BE: vinsbvlx 1, 3, 5                      # encoding: [0x10,0x23,0x28,0x0f]
+# CHECK-LE: vinsbvlx 1, 3, 5                      # encoding: [0x0f,0x28,0x23,0x10]
+            vinsbvlx 1, 3, 5
+# CHECK-BE: vinsbvrx 1, 3, 5                      # encoding: [0x10,0x23,0x29,0x0f]
+# CHECK-LE: vinsbvrx 1, 3, 5                      # encoding: [0x0f,0x29,0x23,0x10]
+            vinsbvrx 1, 3, 5
+# CHECK-BE: vinshvlx 1, 3, 5                      # encoding: [0x10,0x23,0x28,0x4f]
+# CHECK-LE: vinshvlx 1, 3, 5                      # encoding: [0x4f,0x28,0x23,0x10]
+            vinshvlx 1, 3, 5
+# CHECK-BE: vinshvrx 1, 3, 5                      # encoding: [0x10,0x23,0x29,0x4f]
+# CHECK-LE: vinshvrx 1, 3, 5                      # encoding: [0x4f,0x29,0x23,0x10]
+            vinshvrx 1, 3, 5
+# CHECK-BE: vinswvlx 1, 3, 5                      # encoding: [0x10,0x23,0x28,0x8f]
+# CHECK-LE: vinswvlx 1, 3, 5                      # encoding: [0x8f,0x28,0x23,0x10]
+            vinswvlx 1, 3, 5
+# CHECK-BE: vinswvrx 1, 3, 5                      # encoding: [0x10,0x23,0x29,0x8f]
+# CHECK-LE: vinswvrx 1, 3, 5                      # encoding: [0x8f,0x29,0x23,0x10]
+            vinswvrx 1, 3, 5
+# CHECK-BE: vinsblx 1, 2, 3                       # encoding: [0x10,0x22,0x1a,0x0f]
+# CHECK-LE: vinsblx 1, 2, 3                       # encoding: [0x0f,0x1a,0x22,0x10]
+            vinsblx 1, 2, 3
+# CHECK-BE: vinsbrx 1, 2, 3                       # encoding: [0x10,0x22,0x1b,0x0f]
+# CHECK-LE: vinsbrx 1, 2, 3                       # encoding: [0x0f,0x1b,0x22,0x10]
+            vinsbrx 1, 2, 3
+# CHECK-BE: vinshlx 1, 2, 3                       # encoding: [0x10,0x22,0x1a,0x4f]
+# CHECK-LE: vinshlx 1, 2, 3                       # encoding: [0x4f,0x1a,0x22,0x10]
+            vinshlx 1, 2, 3
+# CHECK-BE: vinshrx 1, 2, 3                       # encoding: [0x10,0x22,0x1b,0x4f]
+# CHECK-LE: vinshrx 1, 2, 3                       # encoding: [0x4f,0x1b,0x22,0x10]
+            vinshrx 1, 2, 3
+# CHECK-BE: vinswlx 1, 2, 3                       # encoding: [0x10,0x22,0x1a,0x8f]
+# CHECK-LE: vinswlx 1, 2, 3                       # encoding: [0x8f,0x1a,0x22,0x10]
+            vinswlx 1, 2, 3
+# CHECK-BE: vinswrx 1, 2, 3                       # encoding: [0x10,0x22,0x1b,0x8f]
+# CHECK-LE: vinswrx 1, 2, 3                       # encoding: [0x8f,0x1b,0x22,0x10]
+            vinswrx 1, 2, 3
+# CHECK-BE: vinsdlx 1, 2, 3                       # encoding: [0x10,0x22,0x1a,0xcf]
+# CHECK-LE: vinsdlx 1, 2, 3                       # encoding: [0xcf,0x1a,0x22,0x10]
+            vinsdlx 1, 2, 3
+# CHECK-BE: vinsdrx 1, 2, 3                       # encoding: [0x10,0x22,0x1b,0xcf]
+# CHECK-LE: vinsdrx 1, 2, 3                       # encoding: [0xcf,0x1b,0x22,0x10]
+            vinsdrx 1, 2, 3