In RISC-V vector extension, users could group multiple vector registers as one pseudo register. In mixed width operations, users could use partial vector registers to reduce the register pressure. The parameter to control register grouping and partial use is called LMUL. LMUL is a part of the type. So, we have a bunch of vector types. In order to support all these types, we need new MVT types in LLVM. In this patch, I added several MVT types that are used in RISC-V vector implementation. This is a standalone patch for MVT types without RISC-V related implementation.
|752 ↗||(On Diff #270334)|
Ditto, see comment below.
|250 ↗||(On Diff #270334)|
I wonder if we better preserve the existing numbering here, just in case these numbers have got already been serialized somewhere.
That would be my impression given the unusual ordering of some of the existing enumerators like IIT_V512 and IIT_V128.