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[MVT] Add new MVT types for RISC-V vector.

Authored by HsiangKai on Jun 12 2020, 2:18 AM.



In RISC-V vector extension, users could group multiple vector registers as one pseudo register. In mixed width operations, users could use partial vector registers to reduce the register pressure. The parameter to control register grouping and partial use is called LMUL. LMUL is a part of the type. So, we have a bunch of vector types. In order to support all these types, we need new MVT types in LLVM. In this patch, I added several MVT types that are used in RISC-V vector implementation. This is a standalone patch for MVT types without RISC-V related implementation.

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HsiangKai created this revision.Jun 12 2020, 2:18 AM
rogfer01 added inline comments.Jun 12 2020, 5:58 AM
752 ↗(On Diff #270334)

Ditto, see comment below.

250 ↗(On Diff #270334)

I wonder if we better preserve the existing numbering here, just in case these numbers have got already been serialized somewhere.

That would be my impression given the unusual ordering of some of the existing enumerators like IIT_V512 and IIT_V128.

HsiangKai marked an inline comment as done.Jun 12 2020, 8:09 AM
HsiangKai added inline comments.
250 ↗(On Diff #270334)

Good point. I didn't aware of this.

HsiangKai updated this revision to Diff 270407.Jun 12 2020, 8:10 AM

Remove redundant types.

HsiangKai updated this revision to Diff 271961.Jun 19 2020, 2:17 AM

Add nxv1f16.

It LGTM, but it's better to wait for an OK from a couple or so of other reviewers to chime in.

This revision is now accepted and ready to land.Jun 28 2020, 4:12 PM
This revision was automatically updated to reflect the committed changes.