[llvm-objdump] Decrease instruction indentation for non-x86

[MaskRay]

Summary

Place the instruction at the 24th column (0-based indexing), matching
GNU objdump AArch64/powerpc/etc when the address is low.

This is beneficial for non-x86 targets which have short instruction
lengths.

// GNU objdump AArch64
   0:   91001062        add     x2, x3, #0x4
  400078:       91001062        add     x2, x3, #0x4
// llvm-objdump, with this patch
       0: 62 10 00 91   add     x2, x3, #4
  400078: 62 10 00 91   add     x2, x3, #4
// llvm-objdump, if we change to print a word instead of bytes in the future
       0: 91001062      add     x2, x3, #4
  400078: 91001062      add     x2, x3, #4

// GNU objdump Thumb
   0:   bf00            nop

[MaskRay]

Add --match-full-lines

[jhenderson]

Seems reasonable to me. I take it we don't have any supported targets with 64-bit instructions (or at least more than 32-bits)? Similarly, I assume GNU indents to the same width for e.g. thumb 16-bit instructions as well as 32-bit instructions?

I'm happy with us moving towards better GNU compatibility for some targets without breaking it for others.

[MaskRay]

In D81590#2086917, @jhenderson wrote:

Seems reasonable to me. I take it we don't have any supported targets with 64-bit instructions (or at least more than 32-bits)? Similarly, I assume GNU indents to the same width for e.g. thumb 16-bit instructions as well as 32-bit instructions?

I'm happy with us moving towards better GNU compatibility for some targets without breaking it for others.

Added an example of thumb in the description. The instruction is also placed at the 24th column.

Power ISA v3.1 introduced 64-bit instructions. GNU objdump will not change the column of instructions:

0000000000000000 <.text>:
   0:   00 00 10 04     plwa    r3,0
   4:   00 00 60 a4 
   8:   00 00 10 04     plwa    r3,0
   c:   00 00 60 a4

It seems we don't have good support for these instructions now. (Changing the column will not alter their display if we want to use multi-line..)

llvm/test/tools/llvm-objdump/ELF/AArch64/disassemble-align.s

+# RUN: llvm-mc -filetype=obj -triple=aarch64 %s -o %t
+# RUN: llvm-objdump -d %t | tr '\t' '|' | FileCheck --match-full-lines --strict-whitespace %s
+
+## Use '|' to show where the tabs line up.
+#       CHECK:0000000000000000 <$x.0>:
+#  CHECK-NEXT:       0: 62 10 00 91  |add|x2, x3, #4
+# CHECK-EMPTY:
+#  CHECK-NEXT:0000000000000004 <$d.1>:
+#  CHECK-NEXT:       4:|ff ff 00 00|.word|0x0000ffff
+
+  add x2, x3, #4
+  .word 0xffff

llvm/tools/llvm-objdump/llvm-objdump.cpp

virtual void printInst(MCInstPrinter &IP, const MCInst *MI,
     size_t Start = OS.tell();
     if (!NoLeadingAddr)
       OS << format("%8" PRIx64 ":", Address.Address);
     if (!NoShowRawInsn) {
       OS << ' ';
       dumpBytes(Bytes, OS);
     }
 
-    // The output of printInst starts with a tab. Print some spaces so that
-    // the tab has 1 column and advances to the target tab stop.
-    unsigned TabStop = NoShowRawInsn ? 16 : 40;
+    // The output of printInst starts with a tab. Print some spaces so that the
+    // tab has 1 column and advances to the target tab stop. Give more columns
+    // to x86 which may encode an instruction with many bytes.
+    unsigned TabStop =
+        NoShowRawInsn ? 16 : STI.getTargetTriple().isX86() ? 40 : 24;
     unsigned Column = OS.tell() - Start;
     OS.indent(Column < TabStop - 1 ? TabStop - 1 - Column : 7 - Column % 8);
 
     if (MI) {
       // See MCInstPrinter::printInst. On targets where a PC relative immediate
       // is relative to the next instruction and the length of a MCInst is
       // difficult to measure (x86), this is the address of the next
       // instruction.