[CodeGen][SVE] Replace deprecated calls in getCopyFromPartsVector()

[hkao13]

Summary

Replaced getVectorNumElements() with getVectorElementCount(). Added operator overloads for class ElementCount. Fixes warning in several AArch64 unit tests.

[efriedma]

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

454

Changing the assertions here is fine.

490

There are significant functional implications here, related to the type breakdown stuff Sander is looking at... a v1i8 is actually one element, an nxv1i8 is not. This needs some real design discussion and testing.

[efriedma]

llvm/include/llvm/Support/TypeSize.h

53 ↗

(On Diff #267311)

These operators are a little dubious; it's possible for both A<B and A>=B to be false, which goes against mathematical intuition.

[hkao13]

llvm/include/llvm/Support/TypeSize.h

53 ↗

(On Diff #267311)

Thanks for the review. Strict weak ordering is implemented -- (A < B) and (A >=B) can both be false as long as (A > B) is true. Is there a case where scalable and unscalable widths would be compared? If so then I can remove the LHS and RHS scalable comparisons from the operator overloads.

[efriedma]

llvm/include/llvm/Support/TypeSize.h

53 ↗

(On Diff #267311)

I think I'd prefer to just write out the operation in the users for now, until we have some practical experience with what patterns we end up using in practice.

[hkao13]

Removed ElementCount operator overloads and reverted getVectorElementCount() for case i8 -> <1 x i1>

[hkao13]

@efriedma My weak ordering was wrong. The logic I posted above does not always hold. A > B and B < A can both be true if one is scalable and the other is not. Anyhow what you propose makes sense. I made the changes in the latest edit.

[hkao13]

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

490

I reverted this back to getVectorNumElements(), we can revisit this part in a later patch.

[efriedma]

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

467

This has the same issues as the other check; it treats an nxv1i8 as having "one" element, and I'm not sure that's appropriate here.

[hkao13]

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

467

I reverted this change as well. Thanks.

[efriedma]

LGTM

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

if (PartEVT == ValueVT)
     return Val;
 
   if (PartEVT.isVector()) {
     // If the element type of the source/dest vectors are the same, but the
     // parts vector has more elements than the value vector, then we have a
     // vector widening case (e.g. <2 x float> -> <4 x float>).  Extract the
     // elements we want.
     if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
-      assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
+      assert((PartEVT.getVectorElementCount().Min >
+              ValueVT.getVectorElementCount().Min) &&
+             (PartEVT.getVectorElementCount().Scalable ==
+              ValueVT.getVectorElementCount().Scalable) &&
              "Cannot narrow, it would be a lossy transformation");
       return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
                          DAG.getVectorIdxConstant(0, DL));
     }
 
     // Vector/Vector bitcast.
     if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
       return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
 
-    assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
+    assert(PartEVT.getVectorElementCount() == ValueVT.getVectorElementCount() &&
       "Cannot handle this kind of promotion");
     // Promoted vector extract
     return DAG.getAnyExtOrTrunc(Val, DL, ValueVT);
 
   }
 
   // Trivial bitcast if the types are the same size and the destination
   // vector type is legal.
   if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
       TLI.isTypeLegal(ValueVT))
     return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
 
   if (ValueVT.getVectorNumElements() != 1) {
      // Certain ABIs require that vectors are passed as integers. For vectors
      // are the same size, this is an obvious bitcast.
      if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits()) {
        return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
      } else if (ValueVT.getSizeInBits() < PartEVT.getSizeInBits()) {
        // Bitcast Val back the original type and extract the corresponding
        // vector we want.
        unsigned Elts = PartEVT.getSizeInBits() / ValueVT.getScalarSizeInBits();
        EVT WiderVecType = EVT::getVectorVT(*DAG.getContext(),
                                            ValueVT.getVectorElementType(), Elts);
        Val = DAG.getBitcast(WiderVecType, Val);
        return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
                           DAG.getVectorIdxConstant(0, DL));
      }
 
      diagnosePossiblyInvalidConstraint(
          *DAG.getContext(), V, "non-trivial scalar-to-vector conversion");
      return DAG.getUNDEF(ValueVT);
   }
 
   // Handle cases such as i8 -> <1 x i1>
   EVT ValueSVT = ValueVT.getVectorElementType();
   if (ValueVT.getVectorNumElements() == 1 && ValueSVT != PartEVT) {
     if (ValueSVT.getSizeInBits() == PartEVT.getSizeInBits())
       Val = DAG.getNode(ISD::BITCAST, DL, ValueSVT, Val);
     else
       Val = ValueVT.isFloatingPoint()
                 ? DAG.getFPExtendOrRound(Val, DL, ValueSVT)
                 : DAG.getAnyExtOrTrunc(Val, DL, ValueSVT);
   }