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Differential D80754

AMDGPU/GlobalISel: cmp/select method for insert element
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Authored by rampitec on May 28 2020, 12:55 PM.

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Reviewers
arsenm
vpykhtin
Commits
rG09d325b20c7d: AMDGPU/GlobalISel: cmp/select method for insert element

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Event Timeline

rampitec created this revision.May 28 2020, 12:55 PM
Herald added a project: Restricted Project. · View Herald TranscriptMay 28 2020, 12:55 PM
Herald added subscribers: kerbowa, hiraditya, t-tye and 8 others. · View Herald Transcript
rampitec added a parent revision: D80749: AMDGPU/GlobalISel: cmp/select method for extract element.May 28 2020, 12:55 PM
rampitec marked an inline comment as done.May 28 2020, 1:06 PM
rampitec added inline comments.
llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
331

I assume this will get better when it is moved after RegBankSelect. The issue is copies to VCC inserted by RegBankSelect. The code does not need to be like this, the same code in SelectionDAG creates here:

; %bb.0:                                ; %entry
        v_mov_b32_e32 v1, s0
        v_cmp_eq_u32_e64 vcc, s8, 0
        v_cndmask_b32_e32 v8, v1, v0, vcc
        v_mov_b32_e32 v1, s1
        v_cmp_eq_u32_e64 vcc, s8, 1
        v_cndmask_b32_e32 v1, v1, v0, vcc
        v_mov_b32_e32 v2, s2
        v_cmp_eq_u32_e64 vcc, s8, 2
        v_cndmask_b32_e32 v2, v2, v0, vcc
        v_mov_b32_e32 v3, s3
        v_cmp_eq_u32_e64 vcc, s8, 3
        v_cndmask_b32_e32 v3, v3, v0, vcc
        v_mov_b32_e32 v4, s4
        v_cmp_eq_u32_e64 vcc, s8, 4
        v_cndmask_b32_e32 v4, v4, v0, vcc
        v_mov_b32_e32 v5, s5
        v_cmp_eq_u32_e64 vcc, s8, 5
        v_cndmask_b32_e32 v5, v5, v0, vcc
        v_mov_b32_e32 v6, s6
        v_cmp_eq_u32_e64 vcc, s8, 6
        v_cndmask_b32_e32 v6, v6, v0, vcc
        v_mov_b32_e32 v7, s7
        v_cmp_eq_u32_e64 vcc, s8, 7
        v_cndmask_b32_e32 v7, v7, v0, vcc
        v_mov_b32_e32 v0, v8
        ; return to shader part epilog
arsenm added inline comments.May 28 2020, 1:34 PM
llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
331

Boolean handling is a mess that needs cleanups, and now we get none. I recently saw a case using 5 instructions to get a constant 0.

rampitec updated this revision to Diff 267059.May 28 2020, 3:21 PM

Changes similar to extractelement.

rampitec added a reviewer: vpykhtin.May 28 2020, 10:47 PM
vpykhtin accepted this revision.May 29 2020, 7:00 AM

LGTM

This revision is now accepted and ready to land.May 29 2020, 7:00 AM
arsenm added inline comments.May 29 2020, 12:27 PM
llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp
288

Can initialize to the size here and avoid push_back

300

Don't need getReg here

rampitec updated this revision to Diff 267356.May 29 2020, 1:34 PM
rampitec marked 2 inline comments as done.

Addressed review comments.

rampitec updated this revision to Diff 268285.Jun 3 2020, 1:01 PM

Moved into RegBankSelect.

rampitec requested review of this revision.Jun 3 2020, 1:04 PM
rampitec marked an inline comment as done.
rampitec added inline comments.
llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
56

That is an incorrect selection of G_ICMP with wave32. AMDGPUInstructionSelector::isVCC() does this:

if (RC) {
  const LLT Ty = MRI.getType(Reg);
  return RC->hasSuperClassEq(TRI.getBoolRC()) &&
         Ty.isValid() && Ty.getSizeInBits() == 1;
}

Since SGPR_32 is used for condition hasSuperClassEq() returns true, and even though we have Ty == s1 it still considers it a VCC.

rampitec marked an inline comment as done.Jun 3 2020, 2:16 PM
rampitec added inline comments.
llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
56

This can be fixed by using LLT::scalar(32) instead of LLT::scalar(1).

rampitec updated this revision to Diff 268300.Jun 3 2020, 2:17 PM

Changed scalar condition type to S32.

rampitec updated this revision to Diff 268316.Jun 3 2020, 3:10 PM

Updated test.

arsenm added inline comments.Jun 3 2020, 5:45 PM
llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
1903–1904 ↗(On Diff #268316)

This can ignore this? If it had a constant index the legalizer would have dealt with it already. It's also not wrong to do the rest for a constant

1937–1938 ↗(On Diff #268316)

RegBankSelect should never need to consider the constant bus restriction, see the long comment at the top of the file. Any vector operation should only use VGPR operands

llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
56

Yes, see the long comment at the top of the file. Scalar compares need to always produce s32, s1 is assumed VCC.

106–145

I think the register indexing looks better if the index is uniform

rampitec updated this revision to Diff 268530.Jun 4 2020, 10:53 AM
rampitec marked 4 inline comments as done.
rampitec added inline comments.
llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
106–145

It may look better, but it is not faster.

rampitec updated this revision to Diff 268928.Jun 5 2020, 1:32 PM

Rebased.

rampitec added a comment.Jun 10 2020, 11:36 AM

Ping.

arsenm accepted this revision.Jun 10 2020, 12:10 PM
This revision is now accepted and ready to land.Jun 10 2020, 12:10 PM
Closed by commit rG09d325b20c7d: AMDGPU/GlobalISel: cmp/select method for insert element (authored by rampitec). · Explain WhyJun 10 2020, 1:22 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
10 lines
40 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
2934 lines

Diff 267001

llvm/lib/Target/AMDGPU/AMDGPUCombine.td

Show All 34 Lines (match (wip_match_opcode G_AMDGPU_CVT_F32_UBYTE0,
G_AMDGPU_CVT_F32_UBYTE2, G_AMDGPU_CVT_F32_UBYTE2,
G_AMDGPU_CVT_F32_UBYTE3):$cvt_f32_ubyteN, G_AMDGPU_CVT_F32_UBYTE3):$cvt_f32_ubyteN,
[{ return matchCvtF32UByteN(*${cvt_f32_ubyteN}, MRI, *MF, ${matchinfo}); }]), [{ return matchCvtF32UByteN(*${cvt_f32_ubyteN}, MRI, *MF, ${matchinfo}); }]),
(apply [{ applyCvtF32UByteN(*${cvt_f32_ubyteN}, ${matchinfo}); }])>; (apply [{ applyCvtF32UByteN(*${cvt_f32_ubyteN}, ${matchinfo}); }])>;
def extract_elt_to_cmp_select : GICombineRule< def extract_elt_to_cmp_select : GICombineRule<
(defs root:$extract_elt), (defs root:$extract_elt),
(match (wip_match_opcode G_EXTRACT_VECTOR_ELT):$extract_elt, (match (wip_match_opcode G_EXTRACT_VECTOR_ELT):$extract_elt,
[{ return matchExtractElt(*${extract_elt}, MRI, *MF); }]), [{ return matchExtractInsertElt(*${extract_elt}, MRI, *MF); }]),
(apply [{ applyExtractEltToCmpSelect(*${extract_elt}, MRI); }])>; (apply [{ applyExtractEltToCmpSelect(*${extract_elt}, MRI); }])>;
def insert_elt_to_cmp_select : GICombineRule<
(defs root:$insert_elt),
(match (wip_match_opcode G_INSERT_VECTOR_ELT):$insert_elt,
[{ return matchExtractInsertElt(*${insert_elt}, MRI, *MF); }]),
(apply [{ applyInsertEltToCmpSelect(*${insert_elt}, MRI); }])>;
// Combines which should only apply on SI/VI // Combines which should only apply on SI/VI
def gfx6gfx7_combines : GICombineGroup<[fcmp_select_to_fmin_fmax_legacy]>; def gfx6gfx7_combines : GICombineGroup<[fcmp_select_to_fmin_fmax_legacy]>;
def AMDGPUPreLegalizerCombinerHelper: GICombinerHelper< def AMDGPUPreLegalizerCombinerHelper: GICombinerHelper<
"AMDGPUGenPreLegalizerCombinerHelper", [all_combines, "AMDGPUGenPreLegalizerCombinerHelper", [all_combines,
elide_br_by_inverting_cond]> { elide_br_by_inverting_cond]> {
let DisableRuleOption = "amdgpuprelegalizercombiner-disable-rule"; let DisableRuleOption = "amdgpuprelegalizercombiner-disable-rule";
} }
// FIXME: combines_for_extload can introduce illegal extloads which // FIXME: combines_for_extload can introduce illegal extloads which
// aren't re-legalized. // aren't re-legalized.
// FIXME: Is there a way to remove a single item from all_combines? // FIXME: Is there a way to remove a single item from all_combines?
def all_combines_minus_extload : GICombineGroup<[trivial_combines, def all_combines_minus_extload : GICombineGroup<[trivial_combines,
ptr_add_immed_chain, combine_indexed_load_store, extract_elt_to_cmp_select, ptr_add_immed_chain, combine_indexed_load_store, extract_elt_to_cmp_select,
undef_combines, identity_combines] insert_elt_to_cmp_select, undef_combines, identity_combines]
>; >;
def AMDGPUPostLegalizerCombinerHelper: GICombinerHelper< def AMDGPUPostLegalizerCombinerHelper: GICombinerHelper<
"AMDGPUGenPostLegalizerCombinerHelper", "AMDGPUGenPostLegalizerCombinerHelper",
[all_combines_minus_extload, gfx6gfx7_combines, [all_combines_minus_extload, gfx6gfx7_combines,
uchar_to_float, cvt_f32_ubyteN]> { uchar_to_float, cvt_f32_ubyteN]> {
let DisableRuleOption = "amdgpupostlegalizercombiner-disable-rule"; let DisableRuleOption = "amdgpupostlegalizercombiner-disable-rule";
} }

llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp

Show First 20 Lines • Show All 213 Lines • ▼ Show 20 Lines if (SrcTy != S32) {
CvtSrc = B.buildAnyExt(S32, CvtSrc).getReg(0); CvtSrc = B.buildAnyExt(S32, CvtSrc).getReg(0);
} }
assert(MI.getOpcode() != NewOpc); assert(MI.getOpcode() != NewOpc);
B.buildInstr(NewOpc, {MI.getOperand(0)}, {CvtSrc}, MI.getFlags()); B.buildInstr(NewOpc, {MI.getOperand(0)}, {CvtSrc}, MI.getFlags());
MI.eraseFromParent(); MI.eraseFromParent();
} }
static bool matchExtractElt(MachineInstr &MI, MachineRegisterInfo &MRI, static bool matchExtractInsertElt(MachineInstr &MI, MachineRegisterInfo &MRI,
MachineFunction &MF) { MachineFunction &MF) {
Register VecReg = MI.getOperand(1).getReg(); Register VecReg = MI.getOperand(1).getReg();
Register Idx = MI.getOperand(2).getReg(); Register Idx = MI.getOperand(MI.getNumExplicitOperands() - 1).getReg();
if (getOpcodeDef(TargetOpcode::G_CONSTANT, Idx, MRI)) if (getOpcodeDef(TargetOpcode::G_CONSTANT, Idx, MRI))
return false; return false;
// FIXME: We need another combiner post RegBankSelect. Then move this combine // FIXME: We need another combiner post RegBankSelect. Then move this combine
// there and actually query RegBank of the Idx. // there and actually query RegBank of the Idx.
bool IsDivergent = false; bool IsDivergent = false;
Show All 35 Lines Register Sel = (I == NumElem -1) ? MI.getOperand(0).getReg()
: MRI.createGenericVirtualRegister(EltTy); : MRI.createGenericVirtualRegister(EltTy);
B.buildSelect(Sel, Cmp, Elt, Res); B.buildSelect(Sel, Cmp, Elt, Res);
Res = Sel; Res = Sel;
} }
MI.eraseFromParent(); MI.eraseFromParent();
} }
static void applyInsertEltToCmpSelect(MachineInstr &MI,
MachineRegisterInfo &MRI) {
MachineIRBuilder B(MI);
Register VecReg = MI.getOperand(1).getReg();
Register Ins = MI.getOperand(2).getReg();
Register Idx = MI.getOperand(3).getReg();
LLT VecTy = MRI.getType(VecReg);
LLT EltTy = VecTy.getScalarType();
unsigned EltSize = EltTy.getSizeInBits();
unsigned NumElem = VecTy.getNumElements();
arsenmUnsubmitted
Done
ReplyInline Actions

Can initialize to the size here and avoid push_back

arsenm: Can initialize to the size here and avoid push_back
MachineOperand &Vec = MI.getOperand(1);
SmallVector<Register, 16> Ops;
for (unsigned I = 0; I < NumElem; ++I) {
// FIXME: After RegBankSelect we should know and set register bank.
Register Elt = MRI.createGenericVirtualRegister(EltTy);
B.buildExtract(Elt, Vec, I * EltSize);
Register Cmp = MRI.createGenericVirtualRegister(LLT::scalar(1));
Register IC = MRI.createGenericVirtualRegister(LLT::scalar(32));
B.buildConstant(IC, I);
B.buildICmp(CmpInst::ICMP_EQ, Cmp, Idx, IC);
arsenmUnsubmitted
Done
ReplyInline Actions

Don't need getReg here

arsenm: Don't need getReg here
Register Sel = MRI.createGenericVirtualRegister(EltTy);
B.buildSelect(Sel, Cmp, Ins, Elt);
Ops.push_back(Sel);
}
B.buildBuildVector(MI.getOperand(0).getReg(), Ops);
MI.eraseFromParent();
}
#define AMDGPUPOSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_DEPS #define AMDGPUPOSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_DEPS
#include "AMDGPUGenPostLegalizeGICombiner.inc" #include "AMDGPUGenPostLegalizeGICombiner.inc"
#undef AMDGPUPOSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_DEPS #undef AMDGPUPOSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_DEPS
namespace { namespace {
#define AMDGPUPOSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_H #define AMDGPUPOSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_H
#include "AMDGPUGenPostLegalizeGICombiner.inc" #include "AMDGPUGenPostLegalizeGICombiner.inc"
#undef AMDGPUPOSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_H #undef AMDGPUPOSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_H
▲ Show 20 Lines • Show All 123 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GPRIDX %s ; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GPRIDX %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefix=MOVREL %s ; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefix=MOVREL %s
; RUN: not --crash llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck -check-prefix=ERR %s ; RUN: not --crash llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck -check-prefix=ERR %s
; FIXME: Need constant bus fixup pre-gfx10 for movrel ; FIXME: Need constant bus fixup pre-gfx10 for movrel
; ERR: Bad machine code: VOP* instruction violates constant bus restriction ; ERR: Bad machine code: VOP* instruction violates constant bus restriction
define amdgpu_ps <8 x i32> @dyn_insertelement_v8i32_s_s_s(<8 x i32> inreg %vec, i32 inreg %val, i32 inreg %idx) { define amdgpu_ps <8 x i32> @dyn_insertelement_v8i32_s_s_s(<8 x i32> inreg %vec, i32 inreg %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v8i32_s_s_s: ; GPRIDX-LABEL: dyn_insertelement_v8i32_s_s_s:
; GPRIDX: ; %bb.0: ; %entry ; GPRIDX: ; %bb.0: ; %entry
; GPRIDX-NEXT: s_mov_b32 s0, s2 ; GPRIDX-NEXT: s_cmp_eq_u32 s11, 0
; GPRIDX-NEXT: s_mov_b32 s1, s3 ; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: s_mov_b32 s2, s4 ; GPRIDX-NEXT: s_and_b32 s0, s0, 1
; GPRIDX-NEXT: s_mov_b32 s3, s5 ; GPRIDX-NEXT: s_cmp_lg_u32 s0, 0
; GPRIDX-NEXT: s_mov_b32 s4, s6 ; GPRIDX-NEXT: s_cselect_b32 s0, s10, s2
; GPRIDX-NEXT: s_mov_b32 s5, s7 ; GPRIDX-NEXT: s_cmp_eq_u32 s11, 1
; GPRIDX-NEXT: s_mov_b32 s6, s8 ; GPRIDX-NEXT: s_cselect_b32 s1, 1, 0
; GPRIDX-NEXT: s_mov_b32 s7, s9 ; GPRIDX-NEXT: s_and_b32 s1, s1, 1
; GPRIDX-NEXT: s_mov_b32 m0, s11 ; GPRIDX-NEXT: s_cmp_lg_u32 s1, 0
; GPRIDX-NEXT: s_nop 0 ; GPRIDX-NEXT: s_cselect_b32 s1, s10, s3
; GPRIDX-NEXT: s_movreld_b32 s0, s10 ; GPRIDX-NEXT: s_cmp_eq_u32 s11, 2
; GPRIDX-NEXT: s_cselect_b32 s2, 1, 0
; GPRIDX-NEXT: s_and_b32 s2, s2, 1
; GPRIDX-NEXT: s_cmp_lg_u32 s2, 0
; GPRIDX-NEXT: s_cselect_b32 s2, s10, s4
; GPRIDX-NEXT: s_cmp_eq_u32 s11, 3
; GPRIDX-NEXT: s_cselect_b32 s3, 1, 0
; GPRIDX-NEXT: s_and_b32 s3, s3, 1
; GPRIDX-NEXT: s_cmp_lg_u32 s3, 0
; GPRIDX-NEXT: s_cselect_b32 s3, s10, s5
; GPRIDX-NEXT: s_cmp_eq_u32 s11, 4
; GPRIDX-NEXT: s_cselect_b32 s4, 1, 0
; GPRIDX-NEXT: s_and_b32 s4, s4, 1
; GPRIDX-NEXT: s_cmp_lg_u32 s4, 0
; GPRIDX-NEXT: s_cselect_b32 s4, s10, s6
; GPRIDX-NEXT: s_cmp_eq_u32 s11, 5
; GPRIDX-NEXT: s_cselect_b32 s5, 1, 0
; GPRIDX-NEXT: s_and_b32 s5, s5, 1
; GPRIDX-NEXT: s_cmp_lg_u32 s5, 0
; GPRIDX-NEXT: s_cselect_b32 s5, s10, s7
; GPRIDX-NEXT: s_cmp_eq_u32 s11, 6
; GPRIDX-NEXT: s_cselect_b32 s6, 1, 0
; GPRIDX-NEXT: s_and_b32 s6, s6, 1
; GPRIDX-NEXT: s_cmp_lg_u32 s6, 0
; GPRIDX-NEXT: s_cselect_b32 s6, s10, s8
; GPRIDX-NEXT: s_cmp_eq_u32 s11, 7
; GPRIDX-NEXT: s_cselect_b32 s7, 1, 0
; GPRIDX-NEXT: s_and_b32 s7, s7, 1
; GPRIDX-NEXT: s_cmp_lg_u32 s7, 0
; GPRIDX-NEXT: s_cselect_b32 s7, s10, s9
; GPRIDX-NEXT: ; return to shader part epilog ; GPRIDX-NEXT: ; return to shader part epilog
; ;
; MOVREL-LABEL: dyn_insertelement_v8i32_s_s_s: ; MOVREL-LABEL: dyn_insertelement_v8i32_s_s_s:
; MOVREL: ; %bb.0: ; %entry ; MOVREL: ; %bb.0: ; %entry
; MOVREL-NEXT: s_mov_b32 s0, s2 ; MOVREL-NEXT: s_cmp_eq_u32 s11, 0
rampitecAuthorUnsubmitted
Done
ReplyInline Actions

That is an incorrect selection of G_ICMP with wave32. AMDGPUInstructionSelector::isVCC() does this:

if (RC) {
  const LLT Ty = MRI.getType(Reg);
  return RC->hasSuperClassEq(TRI.getBoolRC()) &&
         Ty.isValid() && Ty.getSizeInBits() == 1;
}

Since SGPR_32 is used for condition hasSuperClassEq() returns true, and even though we have Ty == s1 it still considers it a VCC.

rampitec: That is an incorrect selection of G_ICMP with wave32. AMDGPUInstructionSelector::isVCC() does…
rampitecAuthorUnsubmitted
Done
ReplyInline Actions

This can be fixed by using LLT::scalar(32) instead of LLT::scalar(1).

rampitec: This can be fixed by using LLT::scalar(32) instead of LLT::scalar(1).
arsenmUnsubmitted
Not Done
ReplyInline Actions

Yes, see the long comment at the top of the file. Scalar compares need to always produce s32, s1 is assumed VCC.

arsenm: Yes, see the long comment at the top of the file. Scalar compares need to always produce s32…
; MOVREL-NEXT: s_mov_b32 m0, s11
; MOVREL-NEXT: s_mov_b32 s1, s3
; MOVREL-NEXT: s_mov_b32 s2, s4
; MOVREL-NEXT: s_mov_b32 s3, s5
; MOVREL-NEXT: s_mov_b32 s4, s6
; MOVREL-NEXT: s_mov_b32 s5, s7
; MOVREL-NEXT: s_mov_b32 s6, s8
; MOVREL-NEXT: s_mov_b32 s7, s9
; MOVREL-NEXT: s_movreld_b32 s0, s10
; MOVREL-NEXT: ; implicit-def: $vcc_hi ; MOVREL-NEXT: ; implicit-def: $vcc_hi
; MOVREL-NEXT: s_cselect_b32 s0, 1, 0
; MOVREL-NEXT: s_and_b32 s0, s0, 1
; MOVREL-NEXT: s_cmp_lg_u32 s0, 0
; MOVREL-NEXT: s_cselect_b32 s0, s10, s2
; MOVREL-NEXT: s_cmp_eq_u32 s11, 1
; MOVREL-NEXT: s_cselect_b32 s1, 1, 0
; MOVREL-NEXT: s_and_b32 s1, s1, 1
; MOVREL-NEXT: s_cmp_lg_u32 s1, 0
; MOVREL-NEXT: s_cselect_b32 s1, s10, s3
; MOVREL-NEXT: s_cmp_eq_u32 s11, 2
; MOVREL-NEXT: s_cselect_b32 s2, 1, 0
; MOVREL-NEXT: s_and_b32 s2, s2, 1
; MOVREL-NEXT: s_cmp_lg_u32 s2, 0
; MOVREL-NEXT: s_cselect_b32 s2, s10, s4
; MOVREL-NEXT: s_cmp_eq_u32 s11, 3
; MOVREL-NEXT: s_cselect_b32 s3, 1, 0
; MOVREL-NEXT: s_and_b32 s3, s3, 1
; MOVREL-NEXT: s_cmp_lg_u32 s3, 0
; MOVREL-NEXT: s_cselect_b32 s3, s10, s5
; MOVREL-NEXT: s_cmp_eq_u32 s11, 4
; MOVREL-NEXT: s_cselect_b32 s4, 1, 0
; MOVREL-NEXT: s_and_b32 s4, s4, 1
; MOVREL-NEXT: s_cmp_lg_u32 s4, 0
; MOVREL-NEXT: s_cselect_b32 s4, s10, s6
; MOVREL-NEXT: s_cmp_eq_u32 s11, 5
; MOVREL-NEXT: s_cselect_b32 s5, 1, 0
; MOVREL-NEXT: s_and_b32 s5, s5, 1
; MOVREL-NEXT: s_cmp_lg_u32 s5, 0
; MOVREL-NEXT: s_cselect_b32 s5, s10, s7
; MOVREL-NEXT: s_cmp_eq_u32 s11, 6
; MOVREL-NEXT: s_cselect_b32 s6, 1, 0
; MOVREL-NEXT: s_and_b32 s6, s6, 1
; MOVREL-NEXT: s_cmp_lg_u32 s6, 0
; MOVREL-NEXT: s_cselect_b32 s6, s10, s8
; MOVREL-NEXT: s_cmp_eq_u32 s11, 7
; MOVREL-NEXT: s_cselect_b32 s7, 1, 0
; MOVREL-NEXT: s_and_b32 s7, s7, 1
; MOVREL-NEXT: s_cmp_lg_u32 s7, 0
; MOVREL-NEXT: s_cselect_b32 s7, s10, s9
; MOVREL-NEXT: ; return to shader part epilog ; MOVREL-NEXT: ; return to shader part epilog
entry: entry:
%insert = insertelement <8 x i32> %vec, i32 %val, i32 %idx %insert = insertelement <8 x i32> %vec, i32 %val, i32 %idx
ret <8 x i32> %insert ret <8 x i32> %insert
} }
define amdgpu_ps <8 x i8 addrspace(3)*> @dyn_insertelement_v8p3i8_s_s_s(<8 x i8 addrspace(3)*> inreg %vec, i8 addrspace(3)* inreg %val, i32 inreg %idx) { define amdgpu_ps <8 x i8 addrspace(3)*> @dyn_insertelement_v8p3i8_s_s_s(<8 x i8 addrspace(3)*> inreg %vec, i8 addrspace(3)* inreg %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v8p3i8_s_s_s: ; GPRIDX-LABEL: dyn_insertelement_v8p3i8_s_s_s:
; GPRIDX: ; %bb.0: ; %entry ; GPRIDX: ; %bb.0: ; %entry
; GPRIDX-NEXT: s_mov_b32 s0, s2 ; GPRIDX-NEXT: s_cmp_eq_u32 s11, 0
; GPRIDX-NEXT: s_mov_b32 s1, s3 ; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: s_mov_b32 s2, s4 ; GPRIDX-NEXT: s_and_b32 s0, s0, 1
; GPRIDX-NEXT: s_mov_b32 s3, s5 ; GPRIDX-NEXT: s_cmp_lg_u32 s0, 0
; GPRIDX-NEXT: s_mov_b32 s4, s6 ; GPRIDX-NEXT: s_cselect_b32 s0, s10, s2
; GPRIDX-NEXT: s_mov_b32 s5, s7 ; GPRIDX-NEXT: s_cmp_eq_u32 s11, 1
; GPRIDX-NEXT: s_mov_b32 s6, s8 ; GPRIDX-NEXT: s_cselect_b32 s1, 1, 0
; GPRIDX-NEXT: s_mov_b32 s7, s9 ; GPRIDX-NEXT: s_and_b32 s1, s1, 1
; GPRIDX-NEXT: s_mov_b32 m0, s11 ; GPRIDX-NEXT: s_cmp_lg_u32 s1, 0
; GPRIDX-NEXT: s_nop 0 ; GPRIDX-NEXT: s_cselect_b32 s1, s10, s3
; GPRIDX-NEXT: s_movreld_b32 s0, s10 ; GPRIDX-NEXT: s_cmp_eq_u32 s11, 2
; GPRIDX-NEXT: s_cselect_b32 s2, 1, 0
; GPRIDX-NEXT: s_and_b32 s2, s2, 1
; GPRIDX-NEXT: s_cmp_lg_u32 s2, 0
; GPRIDX-NEXT: s_cselect_b32 s2, s10, s4
; GPRIDX-NEXT: s_cmp_eq_u32 s11, 3
; GPRIDX-NEXT: s_cselect_b32 s3, 1, 0
; GPRIDX-NEXT: s_and_b32 s3, s3, 1
; GPRIDX-NEXT: s_cmp_lg_u32 s3, 0
; GPRIDX-NEXT: s_cselect_b32 s3, s10, s5
; GPRIDX-NEXT: s_cmp_eq_u32 s11, 4
; GPRIDX-NEXT: s_cselect_b32 s4, 1, 0
; GPRIDX-NEXT: s_and_b32 s4, s4, 1
; GPRIDX-NEXT: s_cmp_lg_u32 s4, 0
; GPRIDX-NEXT: s_cselect_b32 s4, s10, s6
; GPRIDX-NEXT: s_cmp_eq_u32 s11, 5
; GPRIDX-NEXT: s_cselect_b32 s5, 1, 0
; GPRIDX-NEXT: s_and_b32 s5, s5, 1
; GPRIDX-NEXT: s_cmp_lg_u32 s5, 0
; GPRIDX-NEXT: s_cselect_b32 s5, s10, s7
; GPRIDX-NEXT: s_cmp_eq_u32 s11, 6
; GPRIDX-NEXT: s_cselect_b32 s6, 1, 0
; GPRIDX-NEXT: s_and_b32 s6, s6, 1
; GPRIDX-NEXT: s_cmp_lg_u32 s6, 0
; GPRIDX-NEXT: s_cselect_b32 s6, s10, s8
; GPRIDX-NEXT: s_cmp_eq_u32 s11, 7
; GPRIDX-NEXT: s_cselect_b32 s7, 1, 0
; GPRIDX-NEXT: s_and_b32 s7, s7, 1
; GPRIDX-NEXT: s_cmp_lg_u32 s7, 0
; GPRIDX-NEXT: s_cselect_b32 s7, s10, s9
arsenmUnsubmitted
Done
ReplyInline Actions

I think the register indexing looks better if the index is uniform

arsenm: I think the register indexing looks better if the index is uniform
rampitecAuthorUnsubmitted
Done
ReplyInline Actions

It may look better, but it is not faster.

rampitec: It may look better, but it is not faster.
; GPRIDX-NEXT: ; return to shader part epilog ; GPRIDX-NEXT: ; return to shader part epilog
; ;
; MOVREL-LABEL: dyn_insertelement_v8p3i8_s_s_s: ; MOVREL-LABEL: dyn_insertelement_v8p3i8_s_s_s:
; MOVREL: ; %bb.0: ; %entry ; MOVREL: ; %bb.0: ; %entry
; MOVREL-NEXT: s_mov_b32 s0, s2 ; MOVREL-NEXT: s_cmp_eq_u32 s11, 0
; MOVREL-NEXT: s_mov_b32 m0, s11
; MOVREL-NEXT: s_mov_b32 s1, s3
; MOVREL-NEXT: s_mov_b32 s2, s4
; MOVREL-NEXT: s_mov_b32 s3, s5
; MOVREL-NEXT: s_mov_b32 s4, s6
; MOVREL-NEXT: s_mov_b32 s5, s7
; MOVREL-NEXT: s_mov_b32 s6, s8
; MOVREL-NEXT: s_mov_b32 s7, s9
; MOVREL-NEXT: s_movreld_b32 s0, s10
; MOVREL-NEXT: ; implicit-def: $vcc_hi ; MOVREL-NEXT: ; implicit-def: $vcc_hi
; MOVREL-NEXT: s_cselect_b32 s0, 1, 0
; MOVREL-NEXT: s_and_b32 s0, s0, 1
; MOVREL-NEXT: s_cmp_lg_u32 s0, 0
; MOVREL-NEXT: s_cselect_b32 s0, s10, s2
; MOVREL-NEXT: s_cmp_eq_u32 s11, 1
; MOVREL-NEXT: s_cselect_b32 s1, 1, 0
; MOVREL-NEXT: s_and_b32 s1, s1, 1
; MOVREL-NEXT: s_cmp_lg_u32 s1, 0
; MOVREL-NEXT: s_cselect_b32 s1, s10, s3
; MOVREL-NEXT: s_cmp_eq_u32 s11, 2
; MOVREL-NEXT: s_cselect_b32 s2, 1, 0
; MOVREL-NEXT: s_and_b32 s2, s2, 1
; MOVREL-NEXT: s_cmp_lg_u32 s2, 0
; MOVREL-NEXT: s_cselect_b32 s2, s10, s4
; MOVREL-NEXT: s_cmp_eq_u32 s11, 3
; MOVREL-NEXT: s_cselect_b32 s3, 1, 0
; MOVREL-NEXT: s_and_b32 s3, s3, 1
; MOVREL-NEXT: s_cmp_lg_u32 s3, 0
; MOVREL-NEXT: s_cselect_b32 s3, s10, s5
; MOVREL-NEXT: s_cmp_eq_u32 s11, 4
; MOVREL-NEXT: s_cselect_b32 s4, 1, 0
; MOVREL-NEXT: s_and_b32 s4, s4, 1
; MOVREL-NEXT: s_cmp_lg_u32 s4, 0
; MOVREL-NEXT: s_cselect_b32 s4, s10, s6
; MOVREL-NEXT: s_cmp_eq_u32 s11, 5
; MOVREL-NEXT: s_cselect_b32 s5, 1, 0
; MOVREL-NEXT: s_and_b32 s5, s5, 1
; MOVREL-NEXT: s_cmp_lg_u32 s5, 0
; MOVREL-NEXT: s_cselect_b32 s5, s10, s7
; MOVREL-NEXT: s_cmp_eq_u32 s11, 6
; MOVREL-NEXT: s_cselect_b32 s6, 1, 0
; MOVREL-NEXT: s_and_b32 s6, s6, 1
; MOVREL-NEXT: s_cmp_lg_u32 s6, 0
; MOVREL-NEXT: s_cselect_b32 s6, s10, s8
; MOVREL-NEXT: s_cmp_eq_u32 s11, 7
; MOVREL-NEXT: s_cselect_b32 s7, 1, 0
; MOVREL-NEXT: s_and_b32 s7, s7, 1
; MOVREL-NEXT: s_cmp_lg_u32 s7, 0
; MOVREL-NEXT: s_cselect_b32 s7, s10, s9
; MOVREL-NEXT: ; return to shader part epilog ; MOVREL-NEXT: ; return to shader part epilog
entry: entry:
%insert = insertelement <8 x i8 addrspace(3)*> %vec, i8 addrspace(3)* %val, i32 %idx %insert = insertelement <8 x i8 addrspace(3)*> %vec, i8 addrspace(3)* %val, i32 %idx
ret <8 x i8 addrspace(3)*> %insert ret <8 x i8 addrspace(3)*> %insert
} }
define <8 x float> @dyn_insertelement_v8f32_const_s_v_v(float %val, i32 %idx) { define <8 x float> @dyn_insertelement_v8f32_const_s_v_v(float %val, i32 %idx) {
; GPRIDX-LABEL: dyn_insertelement_v8f32_const_s_v_v: ; GPRIDX-LABEL: dyn_insertelement_v8f32_const_s_v_v:
; GPRIDX: ; %bb.0: ; %entry ; GPRIDX: ; %bb.0: ; %entry
; GPRIDX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GPRIDX-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GPRIDX-NEXT: s_mov_b32 s11, 0x41000000 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
; GPRIDX-NEXT: s_mov_b32 s10, 0x40e00000 ; GPRIDX-NEXT: v_cndmask_b32_e32 v8, 1.0, v0, vcc
; GPRIDX-NEXT: s_mov_b32 s9, 0x40c00000 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1
; GPRIDX-NEXT: s_mov_b32 s8, 0x40a00000 ; GPRIDX-NEXT: v_cndmask_b32_e32 v9, 2.0, v0, vcc
; GPRIDX-NEXT: s_mov_b32 s7, 4.0 ; GPRIDX-NEXT: v_mov_b32_e32 v2, 0x40400000
; GPRIDX-NEXT: s_mov_b32 s6, 0x40400000 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 2, v1
; GPRIDX-NEXT: s_mov_b32 s5, 2.0 ; GPRIDX-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
; GPRIDX-NEXT: s_mov_b32 s4, 1.0 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 3, v1
; GPRIDX-NEXT: v_mov_b32_e32 v17, s11 ; GPRIDX-NEXT: v_cndmask_b32_e32 v3, 4.0, v0, vcc
; GPRIDX-NEXT: v_mov_b32_e32 v16, s10 ; GPRIDX-NEXT: v_mov_b32_e32 v4, 0x40a00000
; GPRIDX-NEXT: v_mov_b32_e32 v15, s9 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 4, v1
; GPRIDX-NEXT: v_mov_b32_e32 v14, s8 ; GPRIDX-NEXT: v_cndmask_b32_e32 v4, v4, v0, vcc
; GPRIDX-NEXT: v_mov_b32_e32 v13, s7 ; GPRIDX-NEXT: v_mov_b32_e32 v5, 0x40c00000
; GPRIDX-NEXT: v_mov_b32_e32 v12, s6 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 5, v1
; GPRIDX-NEXT: v_mov_b32_e32 v11, s5 ; GPRIDX-NEXT: v_cndmask_b32_e32 v5, v5, v0, vcc
; GPRIDX-NEXT: v_mov_b32_e32 v10, s4 ; GPRIDX-NEXT: v_mov_b32_e32 v6, 0x40e00000
; GPRIDX-NEXT: s_mov_b64 s[4:5], exec ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 6, v1
; GPRIDX-NEXT: BB2_1: ; =>This Inner Loop Header: Depth=1 ; GPRIDX-NEXT: v_cndmask_b32_e32 v6, v6, v0, vcc
; GPRIDX-NEXT: v_readfirstlane_b32 s6, v1 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 7, v1
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, s6, v1 ; GPRIDX-NEXT: v_mov_b32_e32 v7, 0x41000000
; GPRIDX-NEXT: s_set_gpr_idx_on s6, gpr_idx(DST) ; GPRIDX-NEXT: v_cndmask_b32_e32 v7, v7, v0, vcc
; GPRIDX-NEXT: v_mov_b32_e32 v2, v10 ; GPRIDX-NEXT: v_mov_b32_e32 v0, v8
; GPRIDX-NEXT: v_mov_b32_e32 v3, v11 ; GPRIDX-NEXT: v_mov_b32_e32 v1, v9
; GPRIDX-NEXT: v_mov_b32_e32 v4, v12
; GPRIDX-NEXT: v_mov_b32_e32 v5, v13
; GPRIDX-NEXT: v_mov_b32_e32 v6, v14
; GPRIDX-NEXT: v_mov_b32_e32 v7, v15
; GPRIDX-NEXT: v_mov_b32_e32 v8, v16
; GPRIDX-NEXT: v_mov_b32_e32 v9, v17
; GPRIDX-NEXT: v_mov_b32_e32 v2, v0
; GPRIDX-NEXT: s_set_gpr_idx_off
; GPRIDX-NEXT: s_and_saveexec_b64 vcc, vcc
; GPRIDX-NEXT: s_xor_b64 exec, exec, vcc
; GPRIDX-NEXT: s_cbranch_execnz BB2_1
; GPRIDX-NEXT: ; %bb.2:
; GPRIDX-NEXT: s_mov_b64 exec, s[4:5]
; GPRIDX-NEXT: v_mov_b32_e32 v0, v2
; GPRIDX-NEXT: v_mov_b32_e32 v1, v3
; GPRIDX-NEXT: v_mov_b32_e32 v2, v4
; GPRIDX-NEXT: v_mov_b32_e32 v3, v5
; GPRIDX-NEXT: v_mov_b32_e32 v4, v6
; GPRIDX-NEXT: v_mov_b32_e32 v5, v7
; GPRIDX-NEXT: v_mov_b32_e32 v6, v8
; GPRIDX-NEXT: v_mov_b32_e32 v7, v9
; GPRIDX-NEXT: s_setpc_b64 s[30:31] ; GPRIDX-NEXT: s_setpc_b64 s[30:31]
; ;
; MOVREL-LABEL: dyn_insertelement_v8f32_const_s_v_v: ; MOVREL-LABEL: dyn_insertelement_v8f32_const_s_v_v:
; MOVREL: ; %bb.0: ; %entry ; MOVREL: ; %bb.0: ; %entry
; MOVREL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; MOVREL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0 ; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
; MOVREL-NEXT: s_mov_b32 s11, 0x41000000 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
; MOVREL-NEXT: s_mov_b32 s10, 0x40e00000
; MOVREL-NEXT: s_mov_b32 s9, 0x40c00000
; MOVREL-NEXT: s_mov_b32 s8, 0x40a00000
; MOVREL-NEXT: s_mov_b32 s7, 4.0
; MOVREL-NEXT: s_mov_b32 s6, 0x40400000
; MOVREL-NEXT: s_mov_b32 s5, 2.0
; MOVREL-NEXT: s_mov_b32 s4, 1.0
; MOVREL-NEXT: v_mov_b32_e32 v17, s11
; MOVREL-NEXT: v_mov_b32_e32 v16, s10
; MOVREL-NEXT: v_mov_b32_e32 v15, s9
; MOVREL-NEXT: v_mov_b32_e32 v14, s8
; MOVREL-NEXT: v_mov_b32_e32 v13, s7
; MOVREL-NEXT: v_mov_b32_e32 v12, s6
; MOVREL-NEXT: v_mov_b32_e32 v11, s5
; MOVREL-NEXT: v_mov_b32_e32 v10, s4
; MOVREL-NEXT: s_mov_b32 s4, exec_lo
; MOVREL-NEXT: ; implicit-def: $vcc_hi ; MOVREL-NEXT: ; implicit-def: $vcc_hi
; MOVREL-NEXT: BB2_1: ; =>This Inner Loop Header: Depth=1 ; MOVREL-NEXT: v_cndmask_b32_e32 v8, 1.0, v0, vcc_lo
; MOVREL-NEXT: v_readfirstlane_b32 s5, v1 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
; MOVREL-NEXT: v_mov_b32_e32 v2, v10 ; MOVREL-NEXT: v_cndmask_b32_e32 v9, 2.0, v0, vcc_lo
; MOVREL-NEXT: v_mov_b32_e32 v3, v11 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v1
; MOVREL-NEXT: v_mov_b32_e32 v4, v12 ; MOVREL-NEXT: v_cndmask_b32_e32 v2, 0x40400000, v0, vcc_lo
; MOVREL-NEXT: v_mov_b32_e32 v5, v13 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v1
; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, s5, v1 ; MOVREL-NEXT: v_cndmask_b32_e32 v3, 4.0, v0, vcc_lo
; MOVREL-NEXT: s_mov_b32 m0, s5 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v1
; MOVREL-NEXT: v_mov_b32_e32 v6, v14 ; MOVREL-NEXT: v_cndmask_b32_e32 v4, 0x40a00000, v0, vcc_lo
; MOVREL-NEXT: v_mov_b32_e32 v7, v15 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v1
; MOVREL-NEXT: v_mov_b32_e32 v8, v16 ; MOVREL-NEXT: v_cndmask_b32_e32 v5, 0x40c00000, v0, vcc_lo
; MOVREL-NEXT: v_mov_b32_e32 v9, v17 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v1
; MOVREL-NEXT: v_movreld_b32_e32 v2, v0 ; MOVREL-NEXT: v_cndmask_b32_e32 v6, 0x40e00000, v0, vcc_lo
; MOVREL-NEXT: s_and_saveexec_b32 vcc_lo, vcc_lo ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v1
; MOVREL-NEXT: s_xor_b32 exec_lo, exec_lo, vcc_lo ; MOVREL-NEXT: v_mov_b32_e32 v1, v9
; MOVREL-NEXT: s_cbranch_execnz BB2_1 ; MOVREL-NEXT: v_cndmask_b32_e32 v7, 0x41000000, v0, vcc_lo
; MOVREL-NEXT: ; %bb.2: ; MOVREL-NEXT: v_mov_b32_e32 v0, v8
; MOVREL-NEXT: s_mov_b32 exec_lo, s4
; MOVREL-NEXT: v_mov_b32_e32 v0, v2
; MOVREL-NEXT: v_mov_b32_e32 v1, v3
; MOVREL-NEXT: v_mov_b32_e32 v2, v4
; MOVREL-NEXT: v_mov_b32_e32 v3, v5
; MOVREL-NEXT: v_mov_b32_e32 v4, v6
; MOVREL-NEXT: v_mov_b32_e32 v5, v7
; MOVREL-NEXT: v_mov_b32_e32 v6, v8
; MOVREL-NEXT: v_mov_b32_e32 v7, v9
; MOVREL-NEXT: s_setpc_b64 s[30:31] ; MOVREL-NEXT: s_setpc_b64 s[30:31]
entry: entry:
%insert = insertelement <8 x float> <float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0, float 8.0>, float %val, i32 %idx %insert = insertelement <8 x float> <float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0, float 8.0>, float %val, i32 %idx
ret <8 x float> %insert ret <8 x float> %insert
} }
define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_s_s_v(<8 x float> inreg %vec, float inreg %val, i32 %idx) { define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_s_s_v(<8 x float> inreg %vec, float inreg %val, i32 %idx) {
; GPRIDX-LABEL: dyn_insertelement_v8f32_s_s_v: ; GPRIDX-LABEL: dyn_insertelement_v8f32_s_s_v:
; GPRIDX: ; %bb.0: ; %entry ; GPRIDX: ; %bb.0: ; %entry
; GPRIDX-NEXT: s_mov_b32 s1, s3 ; GPRIDX-NEXT: v_mov_b32_e32 v7, s10
; GPRIDX-NEXT: s_mov_b32 s3, s5 ; GPRIDX-NEXT: v_mov_b32_e32 v1, s2
; GPRIDX-NEXT: s_mov_b32 s5, s7 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GPRIDX-NEXT: s_mov_b32 s7, s9 ; GPRIDX-NEXT: v_cndmask_b32_e32 v8, v1, v7, vcc
; GPRIDX-NEXT: s_mov_b32 s0, s2 ; GPRIDX-NEXT: v_mov_b32_e32 v1, s3
; GPRIDX-NEXT: s_mov_b32 s2, s4 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; GPRIDX-NEXT: s_mov_b32 s4, s6 ; GPRIDX-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
; GPRIDX-NEXT: s_mov_b32 s6, s8 ; GPRIDX-NEXT: v_mov_b32_e32 v2, s4
; GPRIDX-NEXT: v_mov_b32_e32 v16, s7 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 2, v0
; GPRIDX-NEXT: v_mov_b32_e32 v8, v0 ; GPRIDX-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc
; GPRIDX-NEXT: v_mov_b32_e32 v15, s6 ; GPRIDX-NEXT: v_mov_b32_e32 v3, s5
; GPRIDX-NEXT: v_mov_b32_e32 v14, s5 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 3, v0
; GPRIDX-NEXT: v_mov_b32_e32 v13, s4 ; GPRIDX-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc
; GPRIDX-NEXT: v_mov_b32_e32 v12, s3 ; GPRIDX-NEXT: v_mov_b32_e32 v4, s6
; GPRIDX-NEXT: v_mov_b32_e32 v11, s2 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 4, v0
; GPRIDX-NEXT: v_mov_b32_e32 v10, s1 ; GPRIDX-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
; GPRIDX-NEXT: v_mov_b32_e32 v9, s0 ; GPRIDX-NEXT: v_mov_b32_e32 v5, s7
; GPRIDX-NEXT: s_mov_b64 s[0:1], exec ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 5, v0
; GPRIDX-NEXT: BB3_1: ; =>This Inner Loop Header: Depth=1 ; GPRIDX-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
; GPRIDX-NEXT: v_readfirstlane_b32 s2, v8 ; GPRIDX-NEXT: v_mov_b32_e32 v6, s8
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, s2, v8 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 6, v0
; GPRIDX-NEXT: s_set_gpr_idx_on s2, gpr_idx(DST) ; GPRIDX-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc
; GPRIDX-NEXT: v_mov_b32_e32 v0, v9 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 7, v0
; GPRIDX-NEXT: v_mov_b32_e32 v1, v10 ; GPRIDX-NEXT: v_mov_b32_e32 v9, s9
; GPRIDX-NEXT: v_mov_b32_e32 v2, v11 ; GPRIDX-NEXT: v_cndmask_b32_e32 v7, v9, v7, vcc
; GPRIDX-NEXT: v_mov_b32_e32 v3, v12 ; GPRIDX-NEXT: v_mov_b32_e32 v0, v8
; GPRIDX-NEXT: v_mov_b32_e32 v4, v13
; GPRIDX-NEXT: v_mov_b32_e32 v5, v14
; GPRIDX-NEXT: v_mov_b32_e32 v6, v15
; GPRIDX-NEXT: v_mov_b32_e32 v7, v16
; GPRIDX-NEXT: v_mov_b32_e32 v0, s10
; GPRIDX-NEXT: s_set_gpr_idx_off
; GPRIDX-NEXT: s_and_saveexec_b64 vcc, vcc
; GPRIDX-NEXT: s_xor_b64 exec, exec, vcc
; GPRIDX-NEXT: s_cbranch_execnz BB3_1
; GPRIDX-NEXT: ; %bb.2:
; GPRIDX-NEXT: s_mov_b64 exec, s[0:1]
; GPRIDX-NEXT: ; return to shader part epilog ; GPRIDX-NEXT: ; return to shader part epilog
; ;
; MOVREL-LABEL: dyn_insertelement_v8f32_s_s_v: ; MOVREL-LABEL: dyn_insertelement_v8f32_s_s_v:
; MOVREL: ; %bb.0: ; %entry ; MOVREL: ; %bb.0: ; %entry
; MOVREL-NEXT: s_mov_b32 s1, s3 ; MOVREL-NEXT: v_mov_b32_e32 v1, s2
; MOVREL-NEXT: s_mov_b32 s3, s5 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; MOVREL-NEXT: s_mov_b32 s5, s7 ; MOVREL-NEXT: v_mov_b32_e32 v2, s3
; MOVREL-NEXT: s_mov_b32 s7, s9 ; MOVREL-NEXT: v_mov_b32_e32 v3, s4
; MOVREL-NEXT: s_mov_b32 s0, s2 ; MOVREL-NEXT: v_mov_b32_e32 v4, s5
; MOVREL-NEXT: s_mov_b32 s2, s4 ; MOVREL-NEXT: v_mov_b32_e32 v5, s6
; MOVREL-NEXT: s_mov_b32 s4, s6 ; MOVREL-NEXT: v_cndmask_b32_e64 v8, v1, s10, vcc_lo
; MOVREL-NEXT: s_mov_b32 s6, s8 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
; MOVREL-NEXT: v_mov_b32_e32 v16, s7 ; MOVREL-NEXT: v_mov_b32_e32 v6, s7
; MOVREL-NEXT: v_mov_b32_e32 v14, s5 ; MOVREL-NEXT: v_mov_b32_e32 v7, s8
; MOVREL-NEXT: v_mov_b32_e32 v12, s3 ; MOVREL-NEXT: v_mov_b32_e32 v9, s9
; MOVREL-NEXT: v_mov_b32_e32 v13, s4
; MOVREL-NEXT: v_mov_b32_e32 v15, s6
; MOVREL-NEXT: v_mov_b32_e32 v11, s2
; MOVREL-NEXT: v_mov_b32_e32 v10, s1
; MOVREL-NEXT: v_mov_b32_e32 v9, s0
; MOVREL-NEXT: s_mov_b32 s0, exec_lo
; MOVREL-NEXT: ; implicit-def: $vcc_hi ; MOVREL-NEXT: ; implicit-def: $vcc_hi
; MOVREL-NEXT: BB3_1: ; =>This Inner Loop Header: Depth=1 ; MOVREL-NEXT: v_cndmask_b32_e64 v1, v2, s10, vcc_lo
; MOVREL-NEXT: v_readfirstlane_b32 s1, v0 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v0
; MOVREL-NEXT: v_mov_b32_e32 v1, v9 ; MOVREL-NEXT: v_cndmask_b32_e64 v2, v3, s10, vcc_lo
; MOVREL-NEXT: v_mov_b32_e32 v2, v10 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v0
; MOVREL-NEXT: v_mov_b32_e32 v3, v11 ; MOVREL-NEXT: v_cndmask_b32_e64 v3, v4, s10, vcc_lo
; MOVREL-NEXT: v_mov_b32_e32 v4, v12 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v0
; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, s1, v0 ; MOVREL-NEXT: v_cndmask_b32_e64 v4, v5, s10, vcc_lo
; MOVREL-NEXT: s_mov_b32 m0, s1 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v0
; MOVREL-NEXT: v_mov_b32_e32 v5, v13 ; MOVREL-NEXT: v_cndmask_b32_e64 v5, v6, s10, vcc_lo
; MOVREL-NEXT: v_mov_b32_e32 v6, v14 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v0
; MOVREL-NEXT: v_mov_b32_e32 v7, v15 ; MOVREL-NEXT: v_cndmask_b32_e64 v6, v7, s10, vcc_lo
; MOVREL-NEXT: v_mov_b32_e32 v8, v16 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v0
; MOVREL-NEXT: v_movreld_b32_e32 v1, s10 ; MOVREL-NEXT: v_mov_b32_e32 v0, v8
; MOVREL-NEXT: s_and_saveexec_b32 vcc_lo, vcc_lo ; MOVREL-NEXT: v_cndmask_b32_e64 v7, v9, s10, vcc_lo
; MOVREL-NEXT: s_xor_b32 exec_lo, exec_lo, vcc_lo
; MOVREL-NEXT: s_cbranch_execnz BB3_1
; MOVREL-NEXT: ; %bb.2:
; MOVREL-NEXT: s_mov_b32 exec_lo, s0
; MOVREL-NEXT: v_mov_b32_e32 v0, v1
; MOVREL-NEXT: v_mov_b32_e32 v1, v2
; MOVREL-NEXT: v_mov_b32_e32 v2, v3
; MOVREL-NEXT: v_mov_b32_e32 v3, v4
; MOVREL-NEXT: v_mov_b32_e32 v4, v5
; MOVREL-NEXT: v_mov_b32_e32 v5, v6
; MOVREL-NEXT: v_mov_b32_e32 v6, v7
; MOVREL-NEXT: v_mov_b32_e32 v7, v8
; MOVREL-NEXT: ; return to shader part epilog ; MOVREL-NEXT: ; return to shader part epilog
entry: entry:
%insert = insertelement <8 x float> %vec, float %val, i32 %idx %insert = insertelement <8 x float> %vec, float %val, i32 %idx
ret <8 x float> %insert ret <8 x float> %insert
} }
define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_s_v_s(<8 x float> inreg %vec, float %val, i32 inreg %idx) { define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_s_v_s(<8 x float> inreg %vec, float %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v8f32_s_v_s: ; GPRIDX-LABEL: dyn_insertelement_v8f32_s_v_s:
; GPRIDX: ; %bb.0: ; %entry ; GPRIDX: ; %bb.0: ; %entry
; GPRIDX-NEXT: s_mov_b32 s0, s2 ; GPRIDX-NEXT: s_cmp_eq_u32 s10, 0
; GPRIDX-NEXT: s_mov_b32 s1, s3 ; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: s_mov_b32 s2, s4 ; GPRIDX-NEXT: s_and_b32 s0, 1, s0
; GPRIDX-NEXT: s_mov_b32 s3, s5 ; GPRIDX-NEXT: s_cmp_eq_u32 s10, 1
; GPRIDX-NEXT: s_mov_b32 s4, s6 ; GPRIDX-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GPRIDX-NEXT: s_mov_b32 s5, s7 ; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: s_mov_b32 s6, s8 ; GPRIDX-NEXT: s_and_b32 s0, 1, s0
; GPRIDX-NEXT: s_mov_b32 s7, s9 ; GPRIDX-NEXT: v_mov_b32_e32 v1, s2
; GPRIDX-NEXT: v_mov_b32_e32 v8, v0 ; GPRIDX-NEXT: s_cmp_eq_u32 s10, 2
rampitecAuthorUnsubmitted
Done
ReplyInline Actions

I assume this will get better when it is moved after RegBankSelect. The issue is copies to VCC inserted by RegBankSelect. The code does not need to be like this, the same code in SelectionDAG creates here:

; %bb.0:                                ; %entry
        v_mov_b32_e32 v1, s0
        v_cmp_eq_u32_e64 vcc, s8, 0
        v_cndmask_b32_e32 v8, v1, v0, vcc
        v_mov_b32_e32 v1, s1
        v_cmp_eq_u32_e64 vcc, s8, 1
        v_cndmask_b32_e32 v1, v1, v0, vcc
        v_mov_b32_e32 v2, s2
        v_cmp_eq_u32_e64 vcc, s8, 2
        v_cndmask_b32_e32 v2, v2, v0, vcc
        v_mov_b32_e32 v3, s3
        v_cmp_eq_u32_e64 vcc, s8, 3
        v_cndmask_b32_e32 v3, v3, v0, vcc
        v_mov_b32_e32 v4, s4
        v_cmp_eq_u32_e64 vcc, s8, 4
        v_cndmask_b32_e32 v4, v4, v0, vcc
        v_mov_b32_e32 v5, s5
        v_cmp_eq_u32_e64 vcc, s8, 5
        v_cndmask_b32_e32 v5, v5, v0, vcc
        v_mov_b32_e32 v6, s6
        v_cmp_eq_u32_e64 vcc, s8, 6
        v_cndmask_b32_e32 v6, v6, v0, vcc
        v_mov_b32_e32 v7, s7
        v_cmp_eq_u32_e64 vcc, s8, 7
        v_cndmask_b32_e32 v7, v7, v0, vcc
        v_mov_b32_e32 v0, v8
        ; return to shader part epilog
rampitec: I assume this will get better when it is moved after RegBankSelect. The issue is copies to VCC…
arsenmUnsubmitted
Not Done
ReplyInline Actions

Boolean handling is a mess that needs cleanups, and now we get none. I recently saw a case using 5 instructions to get a constant 0.

arsenm: Boolean handling is a mess that needs cleanups, and now we get none. I recently saw a case…
; GPRIDX-NEXT: v_mov_b32_e32 v0, s0 ; GPRIDX-NEXT: v_cndmask_b32_e32 v8, v1, v0, vcc
; GPRIDX-NEXT: v_mov_b32_e32 v1, s1 ; GPRIDX-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GPRIDX-NEXT: v_mov_b32_e32 v2, s2 ; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: v_mov_b32_e32 v3, s3 ; GPRIDX-NEXT: s_and_b32 s0, 1, s0
; GPRIDX-NEXT: v_mov_b32_e32 v4, s4 ; GPRIDX-NEXT: v_mov_b32_e32 v1, s3
; GPRIDX-NEXT: v_mov_b32_e32 v5, s5 ; GPRIDX-NEXT: s_cmp_eq_u32 s10, 3
; GPRIDX-NEXT: v_mov_b32_e32 v6, s6 ; GPRIDX-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc
; GPRIDX-NEXT: v_mov_b32_e32 v7, s7 ; GPRIDX-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GPRIDX-NEXT: s_set_gpr_idx_on s10, gpr_idx(DST) ; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: s_and_b32 s0, 1, s0
; GPRIDX-NEXT: v_mov_b32_e32 v2, s4
; GPRIDX-NEXT: s_cmp_eq_u32 s10, 4
; GPRIDX-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
; GPRIDX-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: s_and_b32 s0, 1, s0
; GPRIDX-NEXT: v_mov_b32_e32 v3, s5
; GPRIDX-NEXT: s_cmp_eq_u32 s10, 5
; GPRIDX-NEXT: v_cndmask_b32_e32 v3, v3, v0, vcc
; GPRIDX-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: s_and_b32 s0, 1, s0
; GPRIDX-NEXT: v_mov_b32_e32 v4, s6
; GPRIDX-NEXT: s_cmp_eq_u32 s10, 6
; GPRIDX-NEXT: v_cndmask_b32_e32 v4, v4, v0, vcc
; GPRIDX-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: s_and_b32 s0, 1, s0
; GPRIDX-NEXT: v_mov_b32_e32 v5, s7
; GPRIDX-NEXT: s_cmp_eq_u32 s10, 7
; GPRIDX-NEXT: v_cndmask_b32_e32 v5, v5, v0, vcc
; GPRIDX-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: v_mov_b32_e32 v6, s8
; GPRIDX-NEXT: s_and_b32 s0, 1, s0
; GPRIDX-NEXT: v_cndmask_b32_e32 v6, v6, v0, vcc
; GPRIDX-NEXT: v_mov_b32_e32 v7, s9
; GPRIDX-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GPRIDX-NEXT: v_cndmask_b32_e32 v7, v7, v0, vcc
; GPRIDX-NEXT: v_mov_b32_e32 v0, v8 ; GPRIDX-NEXT: v_mov_b32_e32 v0, v8
; GPRIDX-NEXT: s_set_gpr_idx_off
; GPRIDX-NEXT: ; return to shader part epilog ; GPRIDX-NEXT: ; return to shader part epilog
; ;
; MOVREL-LABEL: dyn_insertelement_v8f32_s_v_s: ; MOVREL-LABEL: dyn_insertelement_v8f32_s_v_s:
; MOVREL: ; %bb.0: ; %entry ; MOVREL: ; %bb.0: ; %entry
; MOVREL-NEXT: s_mov_b32 s0, s2 ; MOVREL-NEXT: s_cmp_eq_u32 s10, 0
; MOVREL-NEXT: s_mov_b32 s1, s3
; MOVREL-NEXT: s_mov_b32 s2, s4
; MOVREL-NEXT: s_mov_b32 s3, s5
; MOVREL-NEXT: s_mov_b32 s4, s6
; MOVREL-NEXT: s_mov_b32 s5, s7
; MOVREL-NEXT: s_mov_b32 s6, s8
; MOVREL-NEXT: s_mov_b32 s7, s9
; MOVREL-NEXT: v_mov_b32_e32 v8, v0
; MOVREL-NEXT: v_mov_b32_e32 v0, s0
; MOVREL-NEXT: s_mov_b32 m0, s10
; MOVREL-NEXT: v_mov_b32_e32 v1, s1
; MOVREL-NEXT: v_mov_b32_e32 v2, s2
; MOVREL-NEXT: v_mov_b32_e32 v3, s3
; MOVREL-NEXT: v_mov_b32_e32 v4, s4
; MOVREL-NEXT: v_mov_b32_e32 v5, s5
; MOVREL-NEXT: v_mov_b32_e32 v6, s6
; MOVREL-NEXT: v_mov_b32_e32 v7, s7
; MOVREL-NEXT: v_movreld_b32_e32 v0, v8
; MOVREL-NEXT: ; implicit-def: $vcc_hi ; MOVREL-NEXT: ; implicit-def: $vcc_hi
; MOVREL-NEXT: s_cselect_b32 s0, 1, 0
; MOVREL-NEXT: s_and_b32 s0, 1, s0
; MOVREL-NEXT: s_cmp_eq_u32 s10, 1
; MOVREL-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
; MOVREL-NEXT: s_cselect_b32 s1, 1, 0
; MOVREL-NEXT: v_cndmask_b32_e32 v8, s2, v0, vcc_lo
; MOVREL-NEXT: s_and_b32 s1, 1, s1
; MOVREL-NEXT: s_cmp_eq_u32 s10, 2
; MOVREL-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s1
; MOVREL-NEXT: s_cselect_b32 s11, 1, 0
; MOVREL-NEXT: v_cndmask_b32_e32 v1, s3, v0, vcc_lo
; MOVREL-NEXT: s_and_b32 s11, 1, s11
; MOVREL-NEXT: s_cmp_eq_u32 s10, 3
; MOVREL-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s11
; MOVREL-NEXT: s_cselect_b32 s12, 1, 0
; MOVREL-NEXT: v_cndmask_b32_e32 v2, s4, v0, vcc_lo
; MOVREL-NEXT: s_and_b32 s12, 1, s12
; MOVREL-NEXT: s_cmp_eq_u32 s10, 4
; MOVREL-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s12
; MOVREL-NEXT: s_cselect_b32 s13, 1, 0
; MOVREL-NEXT: v_cndmask_b32_e32 v3, s5, v0, vcc_lo
; MOVREL-NEXT: s_and_b32 s13, 1, s13
; MOVREL-NEXT: s_cmp_eq_u32 s10, 5
; MOVREL-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s13
; MOVREL-NEXT: s_cselect_b32 s14, 1, 0
; MOVREL-NEXT: v_cndmask_b32_e32 v4, s6, v0, vcc_lo
; MOVREL-NEXT: s_and_b32 s0, 1, s14
; MOVREL-NEXT: s_cmp_eq_u32 s10, 6
; MOVREL-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
; MOVREL-NEXT: s_cselect_b32 s2, 1, 0
; MOVREL-NEXT: v_cndmask_b32_e32 v5, s7, v0, vcc_lo
; MOVREL-NEXT: s_and_b32 s1, 1, s2
; MOVREL-NEXT: s_cmp_eq_u32 s10, 7
; MOVREL-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s1
; MOVREL-NEXT: s_cselect_b32 s2, 1, 0
; MOVREL-NEXT: v_cndmask_b32_e32 v6, s8, v0, vcc_lo
; MOVREL-NEXT: s_and_b32 s2, 1, s2
; MOVREL-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s2
; MOVREL-NEXT: v_cndmask_b32_e32 v7, s9, v0, vcc_lo
; MOVREL-NEXT: v_mov_b32_e32 v0, v8
; MOVREL-NEXT: ; return to shader part epilog ; MOVREL-NEXT: ; return to shader part epilog
entry: entry:
%insert = insertelement <8 x float> %vec, float %val, i32 %idx %insert = insertelement <8 x float> %vec, float %val, i32 %idx
ret <8 x float> %insert ret <8 x float> %insert
} }
define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_v_s_s(<8 x float> %vec, float inreg %val, i32 inreg %idx) { define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_v_s_s(<8 x float> %vec, float inreg %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v8f32_v_s_s: ; GPRIDX-LABEL: dyn_insertelement_v8f32_v_s_s:
; GPRIDX: ; %bb.0: ; %entry ; GPRIDX: ; %bb.0: ; %entry
; GPRIDX-NEXT: s_set_gpr_idx_on s3, gpr_idx(DST) ; GPRIDX-NEXT: s_cmp_eq_u32 s3, 0
; GPRIDX-NEXT: v_mov_b32_e32 v0, s2 ; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: s_set_gpr_idx_off ; GPRIDX-NEXT: s_and_b32 s0, 1, s0
; GPRIDX-NEXT: s_cmp_eq_u32 s3, 1
; GPRIDX-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: s_and_b32 s0, 1, s0
; GPRIDX-NEXT: v_mov_b32_e32 v8, s2
; GPRIDX-NEXT: s_cmp_eq_u32 s3, 2
; GPRIDX-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc
; GPRIDX-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: s_and_b32 s0, 1, s0
; GPRIDX-NEXT: s_cmp_eq_u32 s3, 3
; GPRIDX-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc
; GPRIDX-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: s_and_b32 s0, 1, s0
; GPRIDX-NEXT: s_cmp_eq_u32 s3, 4
; GPRIDX-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc
; GPRIDX-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: s_and_b32 s0, 1, s0
; GPRIDX-NEXT: s_cmp_eq_u32 s3, 5
; GPRIDX-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc
; GPRIDX-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: s_and_b32 s0, 1, s0
; GPRIDX-NEXT: s_cmp_eq_u32 s3, 6
; GPRIDX-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc
; GPRIDX-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: s_and_b32 s0, 1, s0
; GPRIDX-NEXT: s_cmp_eq_u32 s3, 7
; GPRIDX-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc
; GPRIDX-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: s_and_b32 s0, 1, s0
; GPRIDX-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc
; GPRIDX-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GPRIDX-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc
; GPRIDX-NEXT: ; return to shader part epilog ; GPRIDX-NEXT: ; return to shader part epilog
; ;
; MOVREL-LABEL: dyn_insertelement_v8f32_v_s_s: ; MOVREL-LABEL: dyn_insertelement_v8f32_v_s_s:
; MOVREL: ; %bb.0: ; %entry ; MOVREL: ; %bb.0: ; %entry
; MOVREL-NEXT: s_mov_b32 m0, s3 ; MOVREL-NEXT: s_cmp_eq_u32 s3, 0
; MOVREL-NEXT: ; implicit-def: $vcc_hi ; MOVREL-NEXT: ; implicit-def: $vcc_hi
; MOVREL-NEXT: v_movreld_b32_e32 v0, s2 ; MOVREL-NEXT: s_cselect_b32 s0, 1, 0
; MOVREL-NEXT: s_and_b32 s0, 1, s0
; MOVREL-NEXT: s_cmp_eq_u32 s3, 1
; MOVREL-NEXT: v_cmp_ne_u32_e64 s0, 0, s0
; MOVREL-NEXT: s_cselect_b32 s1, 1, 0
; MOVREL-NEXT: v_cndmask_b32_e64 v0, v0, s2, s0
; MOVREL-NEXT: s_and_b32 s1, 1, s1
; MOVREL-NEXT: s_cmp_eq_u32 s3, 2
; MOVREL-NEXT: v_cmp_ne_u32_e64 s1, 0, s1
; MOVREL-NEXT: s_cselect_b32 s4, 1, 0
; MOVREL-NEXT: v_cndmask_b32_e64 v1, v1, s2, s1
; MOVREL-NEXT: s_and_b32 s4, 1, s4
; MOVREL-NEXT: s_cmp_eq_u32 s3, 3
; MOVREL-NEXT: v_cmp_ne_u32_e64 s1, 0, s4
; MOVREL-NEXT: s_cselect_b32 s5, 1, 0
; MOVREL-NEXT: v_cndmask_b32_e64 v2, v2, s2, s1
; MOVREL-NEXT: s_and_b32 s5, 1, s5
; MOVREL-NEXT: s_cmp_eq_u32 s3, 4
; MOVREL-NEXT: v_cmp_ne_u32_e64 s4, 0, s5
; MOVREL-NEXT: s_cselect_b32 s6, 1, 0
; MOVREL-NEXT: v_cndmask_b32_e64 v3, v3, s2, s4
; MOVREL-NEXT: s_and_b32 s6, 1, s6
; MOVREL-NEXT: s_cmp_eq_u32 s3, 5
; MOVREL-NEXT: v_cmp_ne_u32_e64 s4, 0, s6
; MOVREL-NEXT: s_cselect_b32 s7, 1, 0
; MOVREL-NEXT: v_cndmask_b32_e64 v4, v4, s2, s4
; MOVREL-NEXT: s_and_b32 s0, 1, s7
; MOVREL-NEXT: s_cmp_eq_u32 s3, 6
; MOVREL-NEXT: v_cmp_ne_u32_e64 s0, 0, s0
; MOVREL-NEXT: s_cselect_b32 s7, 1, 0
; MOVREL-NEXT: v_cndmask_b32_e64 v5, v5, s2, s0
; MOVREL-NEXT: s_and_b32 s1, 1, s7
; MOVREL-NEXT: s_cmp_eq_u32 s3, 7
; MOVREL-NEXT: v_cmp_ne_u32_e64 s0, 0, s1
; MOVREL-NEXT: s_cselect_b32 s3, 1, 0
; MOVREL-NEXT: v_cndmask_b32_e64 v6, v6, s2, s0
; MOVREL-NEXT: s_and_b32 s3, 1, s3
; MOVREL-NEXT: v_cmp_ne_u32_e64 s0, 0, s3
; MOVREL-NEXT: v_cndmask_b32_e64 v7, v7, s2, s0
; MOVREL-NEXT: ; return to shader part epilog ; MOVREL-NEXT: ; return to shader part epilog
entry: entry:
%insert = insertelement <8 x float> %vec, float %val, i32 %idx %insert = insertelement <8 x float> %vec, float %val, i32 %idx
ret <8 x float> %insert ret <8 x float> %insert
} }
define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_s_v_v(<8 x float> inreg %vec, float %val, i32 %idx) { define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_s_v_v(<8 x float> inreg %vec, float %val, i32 %idx) {
; GPRIDX-LABEL: dyn_insertelement_v8f32_s_v_v: ; GPRIDX-LABEL: dyn_insertelement_v8f32_s_v_v:
; GPRIDX: ; %bb.0: ; %entry ; GPRIDX: ; %bb.0: ; %entry
; GPRIDX-NEXT: s_mov_b32 s1, s3 ; GPRIDX-NEXT: v_mov_b32_e32 v2, s2
; GPRIDX-NEXT: s_mov_b32 s3, s5 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
; GPRIDX-NEXT: s_mov_b32 s5, s7 ; GPRIDX-NEXT: v_cndmask_b32_e32 v8, v2, v0, vcc
; GPRIDX-NEXT: s_mov_b32 s7, s9 ; GPRIDX-NEXT: v_mov_b32_e32 v2, s3
; GPRIDX-NEXT: s_mov_b32 s0, s2 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1
; GPRIDX-NEXT: s_mov_b32 s2, s4 ; GPRIDX-NEXT: v_cndmask_b32_e32 v9, v2, v0, vcc
; GPRIDX-NEXT: s_mov_b32 s4, s6 ; GPRIDX-NEXT: v_mov_b32_e32 v2, s4
; GPRIDX-NEXT: s_mov_b32 s6, s8 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 2, v1
; GPRIDX-NEXT: v_mov_b32_e32 v17, s7 ; GPRIDX-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
; GPRIDX-NEXT: v_mov_b32_e32 v8, v0 ; GPRIDX-NEXT: v_mov_b32_e32 v3, s5
; GPRIDX-NEXT: v_mov_b32_e32 v9, v1 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 3, v1
; GPRIDX-NEXT: v_mov_b32_e32 v16, s6 ; GPRIDX-NEXT: v_cndmask_b32_e32 v3, v3, v0, vcc
; GPRIDX-NEXT: v_mov_b32_e32 v15, s5 ; GPRIDX-NEXT: v_mov_b32_e32 v4, s6
; GPRIDX-NEXT: v_mov_b32_e32 v14, s4 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 4, v1
; GPRIDX-NEXT: v_mov_b32_e32 v13, s3 ; GPRIDX-NEXT: v_cndmask_b32_e32 v4, v4, v0, vcc
; GPRIDX-NEXT: v_mov_b32_e32 v12, s2 ; GPRIDX-NEXT: v_mov_b32_e32 v5, s7
; GPRIDX-NEXT: v_mov_b32_e32 v11, s1 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 5, v1
; GPRIDX-NEXT: v_mov_b32_e32 v10, s0 ; GPRIDX-NEXT: v_cndmask_b32_e32 v5, v5, v0, vcc
; GPRIDX-NEXT: s_mov_b64 s[0:1], exec ; GPRIDX-NEXT: v_mov_b32_e32 v6, s8
; GPRIDX-NEXT: BB6_1: ; =>This Inner Loop Header: Depth=1 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 6, v1
; GPRIDX-NEXT: v_readfirstlane_b32 s2, v9 ; GPRIDX-NEXT: v_cndmask_b32_e32 v6, v6, v0, vcc
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, s2, v9 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 7, v1
; GPRIDX-NEXT: s_set_gpr_idx_on s2, gpr_idx(DST) ; GPRIDX-NEXT: v_mov_b32_e32 v7, s9
; GPRIDX-NEXT: v_mov_b32_e32 v0, v10 ; GPRIDX-NEXT: v_cndmask_b32_e32 v7, v7, v0, vcc
; GPRIDX-NEXT: v_mov_b32_e32 v1, v11
; GPRIDX-NEXT: v_mov_b32_e32 v2, v12
; GPRIDX-NEXT: v_mov_b32_e32 v3, v13
; GPRIDX-NEXT: v_mov_b32_e32 v4, v14
; GPRIDX-NEXT: v_mov_b32_e32 v5, v15
; GPRIDX-NEXT: v_mov_b32_e32 v6, v16
; GPRIDX-NEXT: v_mov_b32_e32 v7, v17
; GPRIDX-NEXT: v_mov_b32_e32 v0, v8 ; GPRIDX-NEXT: v_mov_b32_e32 v0, v8
; GPRIDX-NEXT: s_set_gpr_idx_off ; GPRIDX-NEXT: v_mov_b32_e32 v1, v9
; GPRIDX-NEXT: s_and_saveexec_b64 vcc, vcc
; GPRIDX-NEXT: s_xor_b64 exec, exec, vcc
; GPRIDX-NEXT: s_cbranch_execnz BB6_1
; GPRIDX-NEXT: ; %bb.2:
; GPRIDX-NEXT: s_mov_b64 exec, s[0:1]
; GPRIDX-NEXT: ; return to shader part epilog ; GPRIDX-NEXT: ; return to shader part epilog
; ;
; MOVREL-LABEL: dyn_insertelement_v8f32_s_v_v: ; MOVREL-LABEL: dyn_insertelement_v8f32_s_v_v:
; MOVREL: ; %bb.0: ; %entry ; MOVREL: ; %bb.0: ; %entry
; MOVREL-NEXT: s_mov_b32 s1, s3 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
; MOVREL-NEXT: s_mov_b32 s3, s5
; MOVREL-NEXT: s_mov_b32 s5, s7
; MOVREL-NEXT: s_mov_b32 s7, s9
; MOVREL-NEXT: s_mov_b32 s0, s2
; MOVREL-NEXT: s_mov_b32 s2, s4
; MOVREL-NEXT: s_mov_b32 s4, s6
; MOVREL-NEXT: s_mov_b32 s6, s8
; MOVREL-NEXT: v_mov_b32_e32 v17, s7
; MOVREL-NEXT: v_mov_b32_e32 v15, s5
; MOVREL-NEXT: v_mov_b32_e32 v13, s3
; MOVREL-NEXT: v_mov_b32_e32 v14, s4
; MOVREL-NEXT: v_mov_b32_e32 v16, s6
; MOVREL-NEXT: v_mov_b32_e32 v12, s2
; MOVREL-NEXT: v_mov_b32_e32 v11, s1
; MOVREL-NEXT: v_mov_b32_e32 v10, s0
; MOVREL-NEXT: s_mov_b32 s0, exec_lo
; MOVREL-NEXT: ; implicit-def: $vcc_hi ; MOVREL-NEXT: ; implicit-def: $vcc_hi
; MOVREL-NEXT: BB6_1: ; =>This Inner Loop Header: Depth=1 ; MOVREL-NEXT: v_cndmask_b32_e32 v8, s2, v0, vcc_lo
; MOVREL-NEXT: v_readfirstlane_b32 s1, v1 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
; MOVREL-NEXT: v_mov_b32_e32 v2, v10 ; MOVREL-NEXT: v_cndmask_b32_e32 v9, s3, v0, vcc_lo
; MOVREL-NEXT: v_mov_b32_e32 v3, v11 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v1
; MOVREL-NEXT: v_mov_b32_e32 v4, v12 ; MOVREL-NEXT: v_cndmask_b32_e32 v2, s4, v0, vcc_lo
; MOVREL-NEXT: v_mov_b32_e32 v5, v13 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v1
; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, s1, v1 ; MOVREL-NEXT: v_cndmask_b32_e32 v3, s5, v0, vcc_lo
; MOVREL-NEXT: s_mov_b32 m0, s1 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v1
; MOVREL-NEXT: v_mov_b32_e32 v6, v14 ; MOVREL-NEXT: v_cndmask_b32_e32 v4, s6, v0, vcc_lo
; MOVREL-NEXT: v_mov_b32_e32 v7, v15 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v1
; MOVREL-NEXT: v_mov_b32_e32 v8, v16 ; MOVREL-NEXT: v_cndmask_b32_e32 v5, s7, v0, vcc_lo
; MOVREL-NEXT: v_mov_b32_e32 v9, v17 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v1
; MOVREL-NEXT: v_movreld_b32_e32 v2, v0 ; MOVREL-NEXT: v_cndmask_b32_e32 v6, s8, v0, vcc_lo
; MOVREL-NEXT: s_and_saveexec_b32 vcc_lo, vcc_lo ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v1
; MOVREL-NEXT: s_xor_b32 exec_lo, exec_lo, vcc_lo ; MOVREL-NEXT: v_mov_b32_e32 v1, v9
; MOVREL-NEXT: s_cbranch_execnz BB6_1 ; MOVREL-NEXT: v_cndmask_b32_e32 v7, s9, v0, vcc_lo
; MOVREL-NEXT: ; %bb.2: ; MOVREL-NEXT: v_mov_b32_e32 v0, v8
; MOVREL-NEXT: s_mov_b32 exec_lo, s0
; MOVREL-NEXT: v_mov_b32_e32 v0, v2
; MOVREL-NEXT: v_mov_b32_e32 v1, v3
; MOVREL-NEXT: v_mov_b32_e32 v2, v4
; MOVREL-NEXT: v_mov_b32_e32 v3, v5
; MOVREL-NEXT: v_mov_b32_e32 v4, v6
; MOVREL-NEXT: v_mov_b32_e32 v5, v7
; MOVREL-NEXT: v_mov_b32_e32 v6, v8
; MOVREL-NEXT: v_mov_b32_e32 v7, v9
; MOVREL-NEXT: ; return to shader part epilog ; MOVREL-NEXT: ; return to shader part epilog
entry: entry:
%insert = insertelement <8 x float> %vec, float %val, i32 %idx %insert = insertelement <8 x float> %vec, float %val, i32 %idx
ret <8 x float> %insert ret <8 x float> %insert
} }
define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_v_s_v(<8 x float> %vec, float inreg %val, i32 %idx) { define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_v_s_v(<8 x float> %vec, float inreg %val, i32 %idx) {
; GPRIDX-LABEL: dyn_insertelement_v8f32_v_s_v: ; GPRIDX-LABEL: dyn_insertelement_v8f32_v_s_v:
; GPRIDX: ; %bb.0: ; %entry ; GPRIDX: ; %bb.0: ; %entry
; GPRIDX-NEXT: s_mov_b64 s[0:1], exec
; GPRIDX-NEXT: BB7_1: ; =>This Inner Loop Header: Depth=1
; GPRIDX-NEXT: v_readfirstlane_b32 s3, v8
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, s3, v8
; GPRIDX-NEXT: s_set_gpr_idx_on s3, gpr_idx(DST)
; GPRIDX-NEXT: v_mov_b32_e32 v16, v7
; GPRIDX-NEXT: v_mov_b32_e32 v15, v6
; GPRIDX-NEXT: v_mov_b32_e32 v14, v5
; GPRIDX-NEXT: v_mov_b32_e32 v13, v4
; GPRIDX-NEXT: v_mov_b32_e32 v12, v3
; GPRIDX-NEXT: v_mov_b32_e32 v11, v2
; GPRIDX-NEXT: v_mov_b32_e32 v10, v1
; GPRIDX-NEXT: v_mov_b32_e32 v9, v0
; GPRIDX-NEXT: v_mov_b32_e32 v9, s2 ; GPRIDX-NEXT: v_mov_b32_e32 v9, s2
; GPRIDX-NEXT: s_set_gpr_idx_off ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 0, v8
; GPRIDX-NEXT: s_and_saveexec_b64 vcc, vcc ; GPRIDX-NEXT: v_cndmask_b32_e32 v0, v0, v9, vcc
; GPRIDX-NEXT: s_xor_b64 exec, exec, vcc ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 1, v8
; GPRIDX-NEXT: s_cbranch_execnz BB7_1 ; GPRIDX-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc
; GPRIDX-NEXT: ; %bb.2: ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 2, v8
; GPRIDX-NEXT: s_mov_b64 exec, s[0:1] ; GPRIDX-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc
; GPRIDX-NEXT: v_mov_b32_e32 v0, v9 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 3, v8
; GPRIDX-NEXT: v_mov_b32_e32 v1, v10 ; GPRIDX-NEXT: v_cndmask_b32_e32 v3, v3, v9, vcc
; GPRIDX-NEXT: v_mov_b32_e32 v2, v11 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 4, v8
; GPRIDX-NEXT: v_mov_b32_e32 v3, v12 ; GPRIDX-NEXT: v_cndmask_b32_e32 v4, v4, v9, vcc
; GPRIDX-NEXT: v_mov_b32_e32 v4, v13 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 5, v8
; GPRIDX-NEXT: v_mov_b32_e32 v5, v14 ; GPRIDX-NEXT: v_cndmask_b32_e32 v5, v5, v9, vcc
; GPRIDX-NEXT: v_mov_b32_e32 v6, v15 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 6, v8
; GPRIDX-NEXT: v_mov_b32_e32 v7, v16 ; GPRIDX-NEXT: v_cndmask_b32_e32 v6, v6, v9, vcc
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 7, v8
; GPRIDX-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc
; GPRIDX-NEXT: ; return to shader part epilog ; GPRIDX-NEXT: ; return to shader part epilog
; ;
; MOVREL-LABEL: dyn_insertelement_v8f32_v_s_v: ; MOVREL-LABEL: dyn_insertelement_v8f32_v_s_v:
; MOVREL: ; %bb.0: ; %entry ; MOVREL: ; %bb.0: ; %entry
; MOVREL-NEXT: s_mov_b32 s0, exec_lo ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v8
; MOVREL-NEXT: ; implicit-def: $vcc_hi ; MOVREL-NEXT: ; implicit-def: $vcc_hi
; MOVREL-NEXT: BB7_1: ; =>This Inner Loop Header: Depth=1 ; MOVREL-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc_lo
; MOVREL-NEXT: v_readfirstlane_b32 s1, v8 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v8
; MOVREL-NEXT: v_mov_b32_e32 v16, v7 ; MOVREL-NEXT: v_cndmask_b32_e64 v1, v1, s2, vcc_lo
; MOVREL-NEXT: v_mov_b32_e32 v9, v0 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v8
; MOVREL-NEXT: v_mov_b32_e32 v15, v6 ; MOVREL-NEXT: v_cndmask_b32_e64 v2, v2, s2, vcc_lo
; MOVREL-NEXT: v_mov_b32_e32 v14, v5 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v8
; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, s1, v8 ; MOVREL-NEXT: v_cndmask_b32_e64 v3, v3, s2, vcc_lo
; MOVREL-NEXT: s_mov_b32 m0, s1 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v8
; MOVREL-NEXT: v_mov_b32_e32 v13, v4 ; MOVREL-NEXT: v_cndmask_b32_e64 v4, v4, s2, vcc_lo
; MOVREL-NEXT: v_mov_b32_e32 v12, v3 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v8
; MOVREL-NEXT: v_mov_b32_e32 v11, v2 ; MOVREL-NEXT: v_cndmask_b32_e64 v5, v5, s2, vcc_lo
; MOVREL-NEXT: v_mov_b32_e32 v10, v1 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v8
; MOVREL-NEXT: v_movreld_b32_e32 v9, s2 ; MOVREL-NEXT: v_cndmask_b32_e64 v6, v6, s2, vcc_lo
; MOVREL-NEXT: s_and_saveexec_b32 vcc_lo, vcc_lo ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v8
; MOVREL-NEXT: s_xor_b32 exec_lo, exec_lo, vcc_lo ; MOVREL-NEXT: v_cndmask_b32_e64 v7, v7, s2, vcc_lo
; MOVREL-NEXT: s_cbranch_execnz BB7_1
; MOVREL-NEXT: ; %bb.2:
; MOVREL-NEXT: s_mov_b32 exec_lo, s0
; MOVREL-NEXT: v_mov_b32_e32 v0, v9
; MOVREL-NEXT: v_mov_b32_e32 v1, v10
; MOVREL-NEXT: v_mov_b32_e32 v2, v11
; MOVREL-NEXT: v_mov_b32_e32 v3, v12
; MOVREL-NEXT: v_mov_b32_e32 v4, v13
; MOVREL-NEXT: v_mov_b32_e32 v5, v14
; MOVREL-NEXT: v_mov_b32_e32 v6, v15
; MOVREL-NEXT: v_mov_b32_e32 v7, v16
; MOVREL-NEXT: ; return to shader part epilog ; MOVREL-NEXT: ; return to shader part epilog
entry: entry:
%insert = insertelement <8 x float> %vec, float %val, i32 %idx %insert = insertelement <8 x float> %vec, float %val, i32 %idx
ret <8 x float> %insert ret <8 x float> %insert
} }
define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_v_v_s(<8 x float> %vec, float %val, i32 inreg %idx) { define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_v_v_s(<8 x float> %vec, float %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v8f32_v_v_s: ; GPRIDX-LABEL: dyn_insertelement_v8f32_v_v_s:
; GPRIDX: ; %bb.0: ; %entry ; GPRIDX: ; %bb.0: ; %entry
; GPRIDX-NEXT: s_set_gpr_idx_on s2, gpr_idx(DST) ; GPRIDX-NEXT: s_cmp_eq_u32 s2, 0
; GPRIDX-NEXT: v_mov_b32_e32 v0, v8 ; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: s_set_gpr_idx_off ; GPRIDX-NEXT: s_and_b32 s0, 1, s0
; GPRIDX-NEXT: s_cmp_eq_u32 s2, 1
; GPRIDX-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: s_and_b32 s0, 1, s0
; GPRIDX-NEXT: s_cmp_eq_u32 s2, 2
; GPRIDX-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc
; GPRIDX-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: s_and_b32 s0, 1, s0
; GPRIDX-NEXT: s_cmp_eq_u32 s2, 3
; GPRIDX-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc
; GPRIDX-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: s_and_b32 s0, 1, s0
; GPRIDX-NEXT: s_cmp_eq_u32 s2, 4
; GPRIDX-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc
; GPRIDX-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: s_and_b32 s0, 1, s0
; GPRIDX-NEXT: s_cmp_eq_u32 s2, 5
; GPRIDX-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc
; GPRIDX-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: s_and_b32 s0, 1, s0
; GPRIDX-NEXT: s_cmp_eq_u32 s2, 6
; GPRIDX-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc
; GPRIDX-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: s_and_b32 s0, 1, s0
; GPRIDX-NEXT: s_cmp_eq_u32 s2, 7
; GPRIDX-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc
; GPRIDX-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: s_and_b32 s0, 1, s0
; GPRIDX-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc
; GPRIDX-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GPRIDX-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc
; GPRIDX-NEXT: ; return to shader part epilog ; GPRIDX-NEXT: ; return to shader part epilog
; ;
; MOVREL-LABEL: dyn_insertelement_v8f32_v_v_s: ; MOVREL-LABEL: dyn_insertelement_v8f32_v_v_s:
; MOVREL: ; %bb.0: ; %entry ; MOVREL: ; %bb.0: ; %entry
; MOVREL-NEXT: s_mov_b32 m0, s2 ; MOVREL-NEXT: s_cmp_eq_u32 s2, 0
; MOVREL-NEXT: ; implicit-def: $vcc_hi ; MOVREL-NEXT: ; implicit-def: $vcc_hi
; MOVREL-NEXT: v_movreld_b32_e32 v0, v8 ; MOVREL-NEXT: s_cselect_b32 s0, 1, 0
; MOVREL-NEXT: s_and_b32 s0, 1, s0
; MOVREL-NEXT: s_cmp_eq_u32 s2, 1
; MOVREL-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
; MOVREL-NEXT: s_cselect_b32 s1, 1, 0
; MOVREL-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc_lo
; MOVREL-NEXT: s_and_b32 s1, 1, s1
; MOVREL-NEXT: s_cmp_eq_u32 s2, 2
; MOVREL-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s1
; MOVREL-NEXT: s_cselect_b32 s3, 1, 0
; MOVREL-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc_lo
; MOVREL-NEXT: s_and_b32 s3, 1, s3
; MOVREL-NEXT: s_cmp_eq_u32 s2, 3
; MOVREL-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s3
; MOVREL-NEXT: s_cselect_b32 s4, 1, 0
; MOVREL-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc_lo
; MOVREL-NEXT: s_and_b32 s4, 1, s4
; MOVREL-NEXT: s_cmp_eq_u32 s2, 4
; MOVREL-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s4
; MOVREL-NEXT: s_cselect_b32 s5, 1, 0
; MOVREL-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc_lo
; MOVREL-NEXT: s_and_b32 s5, 1, s5
; MOVREL-NEXT: s_cmp_eq_u32 s2, 5
; MOVREL-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s5
; MOVREL-NEXT: s_cselect_b32 s6, 1, 0
; MOVREL-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc_lo
; MOVREL-NEXT: s_and_b32 s0, 1, s6
; MOVREL-NEXT: s_cmp_eq_u32 s2, 6
; MOVREL-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
; MOVREL-NEXT: s_cselect_b32 s6, 1, 0
; MOVREL-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc_lo
; MOVREL-NEXT: s_and_b32 s1, 1, s6
; MOVREL-NEXT: s_cmp_eq_u32 s2, 7
; MOVREL-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s1
; MOVREL-NEXT: s_cselect_b32 s2, 1, 0
; MOVREL-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc_lo
; MOVREL-NEXT: s_and_b32 s2, 1, s2
; MOVREL-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s2
; MOVREL-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc_lo
; MOVREL-NEXT: ; return to shader part epilog ; MOVREL-NEXT: ; return to shader part epilog
entry: entry:
%insert = insertelement <8 x float> %vec, float %val, i32 %idx %insert = insertelement <8 x float> %vec, float %val, i32 %idx
ret <8 x float> %insert ret <8 x float> %insert
} }
define amdgpu_ps <8 x float> @dyn_insertelement_v8p3i8_v_v_s(<8 x i8 addrspace(3)*> %vec, i8 addrspace(3)* %val, i32 inreg %idx) { define amdgpu_ps <8 x float> @dyn_insertelement_v8p3i8_v_v_s(<8 x i8 addrspace(3)*> %vec, i8 addrspace(3)* %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v8p3i8_v_v_s: ; GPRIDX-LABEL: dyn_insertelement_v8p3i8_v_v_s:
; GPRIDX: ; %bb.0: ; %entry ; GPRIDX: ; %bb.0: ; %entry
; GPRIDX-NEXT: s_set_gpr_idx_on s2, gpr_idx(DST) ; GPRIDX-NEXT: s_cmp_eq_u32 s2, 0
; GPRIDX-NEXT: v_mov_b32_e32 v0, v8 ; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: s_set_gpr_idx_off ; GPRIDX-NEXT: s_and_b32 s0, 1, s0
; GPRIDX-NEXT: s_cmp_eq_u32 s2, 1
; GPRIDX-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: s_and_b32 s0, 1, s0
; GPRIDX-NEXT: s_cmp_eq_u32 s2, 2
; GPRIDX-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc
; GPRIDX-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: s_and_b32 s0, 1, s0
; GPRIDX-NEXT: s_cmp_eq_u32 s2, 3
; GPRIDX-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc
; GPRIDX-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: s_and_b32 s0, 1, s0
; GPRIDX-NEXT: s_cmp_eq_u32 s2, 4
; GPRIDX-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc
; GPRIDX-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: s_and_b32 s0, 1, s0
; GPRIDX-NEXT: s_cmp_eq_u32 s2, 5
; GPRIDX-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc
; GPRIDX-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: s_and_b32 s0, 1, s0
; GPRIDX-NEXT: s_cmp_eq_u32 s2, 6
; GPRIDX-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc
; GPRIDX-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: s_and_b32 s0, 1, s0
; GPRIDX-NEXT: s_cmp_eq_u32 s2, 7
; GPRIDX-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc
; GPRIDX-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: s_and_b32 s0, 1, s0
; GPRIDX-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc
; GPRIDX-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GPRIDX-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc
; GPRIDX-NEXT: ; return to shader part epilog ; GPRIDX-NEXT: ; return to shader part epilog
; ;
; MOVREL-LABEL: dyn_insertelement_v8p3i8_v_v_s: ; MOVREL-LABEL: dyn_insertelement_v8p3i8_v_v_s:
; MOVREL: ; %bb.0: ; %entry ; MOVREL: ; %bb.0: ; %entry
; MOVREL-NEXT: s_mov_b32 m0, s2 ; MOVREL-NEXT: s_cmp_eq_u32 s2, 0
; MOVREL-NEXT: ; implicit-def: $vcc_hi ; MOVREL-NEXT: ; implicit-def: $vcc_hi
; MOVREL-NEXT: v_movreld_b32_e32 v0, v8 ; MOVREL-NEXT: s_cselect_b32 s0, 1, 0
; MOVREL-NEXT: s_and_b32 s0, 1, s0
; MOVREL-NEXT: s_cmp_eq_u32 s2, 1
; MOVREL-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
; MOVREL-NEXT: s_cselect_b32 s1, 1, 0
; MOVREL-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc_lo
; MOVREL-NEXT: s_and_b32 s1, 1, s1
; MOVREL-NEXT: s_cmp_eq_u32 s2, 2
; MOVREL-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s1
; MOVREL-NEXT: s_cselect_b32 s3, 1, 0
; MOVREL-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc_lo
; MOVREL-NEXT: s_and_b32 s3, 1, s3
; MOVREL-NEXT: s_cmp_eq_u32 s2, 3
; MOVREL-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s3
; MOVREL-NEXT: s_cselect_b32 s4, 1, 0
; MOVREL-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc_lo
; MOVREL-NEXT: s_and_b32 s4, 1, s4
; MOVREL-NEXT: s_cmp_eq_u32 s2, 4
; MOVREL-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s4
; MOVREL-NEXT: s_cselect_b32 s5, 1, 0
; MOVREL-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc_lo
; MOVREL-NEXT: s_and_b32 s5, 1, s5
; MOVREL-NEXT: s_cmp_eq_u32 s2, 5
; MOVREL-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s5
; MOVREL-NEXT: s_cselect_b32 s6, 1, 0
; MOVREL-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc_lo
; MOVREL-NEXT: s_and_b32 s0, 1, s6
; MOVREL-NEXT: s_cmp_eq_u32 s2, 6
; MOVREL-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
; MOVREL-NEXT: s_cselect_b32 s6, 1, 0
; MOVREL-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc_lo
; MOVREL-NEXT: s_and_b32 s1, 1, s6
; MOVREL-NEXT: s_cmp_eq_u32 s2, 7
; MOVREL-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s1
; MOVREL-NEXT: s_cselect_b32 s2, 1, 0
; MOVREL-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc_lo
; MOVREL-NEXT: s_and_b32 s2, 1, s2
; MOVREL-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s2
; MOVREL-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc_lo
; MOVREL-NEXT: ; return to shader part epilog ; MOVREL-NEXT: ; return to shader part epilog
entry: entry:
%insert = insertelement <8 x i8 addrspace(3)*> %vec, i8 addrspace(3)* %val, i32 %idx %insert = insertelement <8 x i8 addrspace(3)*> %vec, i8 addrspace(3)* %val, i32 %idx
%cast.0 = ptrtoint <8 x i8 addrspace(3)*> %insert to <8 x i32> %cast.0 = ptrtoint <8 x i8 addrspace(3)*> %insert to <8 x i32>
%cast.1 = bitcast <8 x i32> %cast.0 to <8 x float> %cast.1 = bitcast <8 x i32> %cast.0 to <8 x float>
ret <8 x float> %cast.1 ret <8 x float> %cast.1
} }
define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_v_v_v(<8 x float> %vec, float %val, i32 %idx) { define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_v_v_v(<8 x float> %vec, float %val, i32 %idx) {
; GPRIDX-LABEL: dyn_insertelement_v8f32_v_v_v: ; GPRIDX-LABEL: dyn_insertelement_v8f32_v_v_v:
; GPRIDX: ; %bb.0: ; %entry ; GPRIDX: ; %bb.0: ; %entry
; GPRIDX-NEXT: s_mov_b64 s[0:1], exec ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 0, v9
; GPRIDX-NEXT: BB10_1: ; =>This Inner Loop Header: Depth=1 ; GPRIDX-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc
; GPRIDX-NEXT: v_readfirstlane_b32 s2, v9 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 1, v9
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, s2, v9 ; GPRIDX-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc
; GPRIDX-NEXT: s_set_gpr_idx_on s2, gpr_idx(DST) ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 2, v9
; GPRIDX-NEXT: v_mov_b32_e32 v17, v7 ; GPRIDX-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc
; GPRIDX-NEXT: v_mov_b32_e32 v16, v6 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 3, v9
; GPRIDX-NEXT: v_mov_b32_e32 v15, v5 ; GPRIDX-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc
; GPRIDX-NEXT: v_mov_b32_e32 v14, v4 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 4, v9
; GPRIDX-NEXT: v_mov_b32_e32 v13, v3 ; GPRIDX-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc
; GPRIDX-NEXT: v_mov_b32_e32 v12, v2 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 5, v9
; GPRIDX-NEXT: v_mov_b32_e32 v11, v1 ; GPRIDX-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc
; GPRIDX-NEXT: v_mov_b32_e32 v10, v0 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 6, v9
; GPRIDX-NEXT: v_mov_b32_e32 v10, v8 ; GPRIDX-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc
; GPRIDX-NEXT: s_set_gpr_idx_off ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 7, v9
; GPRIDX-NEXT: s_and_saveexec_b64 vcc, vcc ; GPRIDX-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc
; GPRIDX-NEXT: s_xor_b64 exec, exec, vcc
; GPRIDX-NEXT: s_cbranch_execnz BB10_1
; GPRIDX-NEXT: ; %bb.2:
; GPRIDX-NEXT: s_mov_b64 exec, s[0:1]
; GPRIDX-NEXT: v_mov_b32_e32 v0, v10
; GPRIDX-NEXT: v_mov_b32_e32 v1, v11
; GPRIDX-NEXT: v_mov_b32_e32 v2, v12
; GPRIDX-NEXT: v_mov_b32_e32 v3, v13
; GPRIDX-NEXT: v_mov_b32_e32 v4, v14
; GPRIDX-NEXT: v_mov_b32_e32 v5, v15
; GPRIDX-NEXT: v_mov_b32_e32 v6, v16
; GPRIDX-NEXT: v_mov_b32_e32 v7, v17
; GPRIDX-NEXT: ; return to shader part epilog ; GPRIDX-NEXT: ; return to shader part epilog
; ;
; MOVREL-LABEL: dyn_insertelement_v8f32_v_v_v: ; MOVREL-LABEL: dyn_insertelement_v8f32_v_v_v:
; MOVREL: ; %bb.0: ; %entry ; MOVREL: ; %bb.0: ; %entry
; MOVREL-NEXT: s_mov_b32 s0, exec_lo ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v9
; MOVREL-NEXT: ; implicit-def: $vcc_hi ; MOVREL-NEXT: ; implicit-def: $vcc_hi
; MOVREL-NEXT: BB10_1: ; =>This Inner Loop Header: Depth=1 ; MOVREL-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc_lo
; MOVREL-NEXT: v_readfirstlane_b32 s1, v9 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v9
; MOVREL-NEXT: v_mov_b32_e32 v17, v7 ; MOVREL-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc_lo
; MOVREL-NEXT: v_mov_b32_e32 v10, v0 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v9
; MOVREL-NEXT: v_mov_b32_e32 v16, v6 ; MOVREL-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc_lo
; MOVREL-NEXT: v_mov_b32_e32 v15, v5 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v9
; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, s1, v9 ; MOVREL-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc_lo
; MOVREL-NEXT: s_mov_b32 m0, s1 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v9
; MOVREL-NEXT: v_mov_b32_e32 v14, v4 ; MOVREL-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc_lo
; MOVREL-NEXT: v_mov_b32_e32 v13, v3 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v9
; MOVREL-NEXT: v_mov_b32_e32 v12, v2 ; MOVREL-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc_lo
; MOVREL-NEXT: v_mov_b32_e32 v11, v1 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v9
; MOVREL-NEXT: v_movreld_b32_e32 v10, v8 ; MOVREL-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc_lo
; MOVREL-NEXT: s_and_saveexec_b32 vcc_lo, vcc_lo ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v9
; MOVREL-NEXT: s_xor_b32 exec_lo, exec_lo, vcc_lo ; MOVREL-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc_lo
; MOVREL-NEXT: s_cbranch_execnz BB10_1
; MOVREL-NEXT: ; %bb.2:
; MOVREL-NEXT: s_mov_b32 exec_lo, s0
; MOVREL-NEXT: v_mov_b32_e32 v0, v10
; MOVREL-NEXT: v_mov_b32_e32 v1, v11
; MOVREL-NEXT: v_mov_b32_e32 v2, v12
; MOVREL-NEXT: v_mov_b32_e32 v3, v13
; MOVREL-NEXT: v_mov_b32_e32 v4, v14
; MOVREL-NEXT: v_mov_b32_e32 v5, v15
; MOVREL-NEXT: v_mov_b32_e32 v6, v16
; MOVREL-NEXT: v_mov_b32_e32 v7, v17
; MOVREL-NEXT: ; return to shader part epilog ; MOVREL-NEXT: ; return to shader part epilog
entry: entry:
%insert = insertelement <8 x float> %vec, float %val, i32 %idx %insert = insertelement <8 x float> %vec, float %val, i32 %idx
ret <8 x float> %insert ret <8 x float> %insert
} }
define amdgpu_ps <8 x i64> @dyn_insertelement_v8i64_s_s_s(<8 x i64> inreg %vec, i64 inreg %val, i32 inreg %idx) { define amdgpu_ps <8 x i64> @dyn_insertelement_v8i64_s_s_s(<8 x i64> inreg %vec, i64 inreg %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v8i64_s_s_s: ; GPRIDX-LABEL: dyn_insertelement_v8i64_s_s_s:
▲ Show 20 Lines • Show All 914 Lines • ▼ Show 20 Linesentry:
store volatile <2 x double> %vec.2, <2 x double> addrspace(1)* undef store volatile <2 x double> %vec.2, <2 x double> addrspace(1)* undef
store volatile <2 x double> %vec.3, <2 x double> addrspace(1)* undef store volatile <2 x double> %vec.3, <2 x double> addrspace(1)* undef
ret void ret void
} }
define amdgpu_ps <3 x i32> @dyn_insertelement_v3i32_s_s_s(<3 x i32> inreg %vec, i32 inreg %val, i32 inreg %idx) { define amdgpu_ps <3 x i32> @dyn_insertelement_v3i32_s_s_s(<3 x i32> inreg %vec, i32 inreg %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v3i32_s_s_s: ; GPRIDX-LABEL: dyn_insertelement_v3i32_s_s_s:
; GPRIDX: ; %bb.0: ; %entry ; GPRIDX: ; %bb.0: ; %entry
; GPRIDX-NEXT: s_mov_b32 s0, s2 ; GPRIDX-NEXT: s_cmp_eq_u32 s6, 0
; GPRIDX-NEXT: s_mov_b32 s1, s3 ; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: s_mov_b32 s2, s4 ; GPRIDX-NEXT: s_and_b32 s0, s0, 1
; GPRIDX-NEXT: s_mov_b32 m0, s6 ; GPRIDX-NEXT: s_cmp_lg_u32 s0, 0
; GPRIDX-NEXT: s_nop 0 ; GPRIDX-NEXT: s_cselect_b32 s0, s5, s2
; GPRIDX-NEXT: s_movreld_b32 s0, s5 ; GPRIDX-NEXT: s_cmp_eq_u32 s6, 1
; GPRIDX-NEXT: s_cselect_b32 s1, 1, 0
; GPRIDX-NEXT: s_and_b32 s1, s1, 1
; GPRIDX-NEXT: s_cmp_lg_u32 s1, 0
; GPRIDX-NEXT: s_cselect_b32 s1, s5, s3
; GPRIDX-NEXT: s_cmp_eq_u32 s6, 2
; GPRIDX-NEXT: s_cselect_b32 s2, 1, 0
; GPRIDX-NEXT: s_and_b32 s2, s2, 1
; GPRIDX-NEXT: s_cmp_lg_u32 s2, 0
; GPRIDX-NEXT: s_cselect_b32 s2, s5, s4
; GPRIDX-NEXT: ; return to shader part epilog ; GPRIDX-NEXT: ; return to shader part epilog
; ;
; MOVREL-LABEL: dyn_insertelement_v3i32_s_s_s: ; MOVREL-LABEL: dyn_insertelement_v3i32_s_s_s:
; MOVREL: ; %bb.0: ; %entry ; MOVREL: ; %bb.0: ; %entry
; MOVREL-NEXT: s_mov_b32 s0, s2 ; MOVREL-NEXT: s_cmp_eq_u32 s6, 0
; MOVREL-NEXT: s_mov_b32 m0, s6
; MOVREL-NEXT: s_mov_b32 s1, s3
; MOVREL-NEXT: s_mov_b32 s2, s4
; MOVREL-NEXT: ; implicit-def: $vcc_hi ; MOVREL-NEXT: ; implicit-def: $vcc_hi
; MOVREL-NEXT: s_movreld_b32 s0, s5 ; MOVREL-NEXT: s_cselect_b32 s0, 1, 0
; MOVREL-NEXT: s_and_b32 s0, s0, 1
; MOVREL-NEXT: s_cmp_lg_u32 s0, 0
; MOVREL-NEXT: s_cselect_b32 s0, s5, s2
; MOVREL-NEXT: s_cmp_eq_u32 s6, 1
; MOVREL-NEXT: s_cselect_b32 s1, 1, 0
; MOVREL-NEXT: s_and_b32 s1, s1, 1
; MOVREL-NEXT: s_cmp_lg_u32 s1, 0
; MOVREL-NEXT: s_cselect_b32 s1, s5, s3
; MOVREL-NEXT: s_cmp_eq_u32 s6, 2
; MOVREL-NEXT: s_cselect_b32 s2, 1, 0
; MOVREL-NEXT: s_and_b32 s2, s2, 1
; MOVREL-NEXT: s_cmp_lg_u32 s2, 0
; MOVREL-NEXT: s_cselect_b32 s2, s5, s4
; MOVREL-NEXT: ; return to shader part epilog ; MOVREL-NEXT: ; return to shader part epilog
entry: entry:
%insert = insertelement <3 x i32> %vec, i32 %val, i32 %idx %insert = insertelement <3 x i32> %vec, i32 %val, i32 %idx
ret <3 x i32> %insert ret <3 x i32> %insert
} }
define amdgpu_ps <3 x float> @dyn_insertelement_v3i32_v_v_s(<3 x float> %vec, float %val, i32 inreg %idx) { define amdgpu_ps <3 x float> @dyn_insertelement_v3i32_v_v_s(<3 x float> %vec, float %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v3i32_v_v_s: ; GPRIDX-LABEL: dyn_insertelement_v3i32_v_v_s:
; GPRIDX: ; %bb.0: ; %entry ; GPRIDX: ; %bb.0: ; %entry
; GPRIDX-NEXT: s_set_gpr_idx_on s2, gpr_idx(DST) ; GPRIDX-NEXT: s_cmp_eq_u32 s2, 0
; GPRIDX-NEXT: v_mov_b32_e32 v0, v3 ; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: s_set_gpr_idx_off ; GPRIDX-NEXT: s_and_b32 s0, 1, s0
; GPRIDX-NEXT: s_cmp_eq_u32 s2, 1
; GPRIDX-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: s_and_b32 s0, 1, s0
; GPRIDX-NEXT: s_cmp_eq_u32 s2, 2
; GPRIDX-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GPRIDX-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: s_and_b32 s0, 1, s0
; GPRIDX-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GPRIDX-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GPRIDX-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GPRIDX-NEXT: ; return to shader part epilog ; GPRIDX-NEXT: ; return to shader part epilog
; ;
; MOVREL-LABEL: dyn_insertelement_v3i32_v_v_s: ; MOVREL-LABEL: dyn_insertelement_v3i32_v_v_s:
; MOVREL: ; %bb.0: ; %entry ; MOVREL: ; %bb.0: ; %entry
; MOVREL-NEXT: s_mov_b32 m0, s2 ; MOVREL-NEXT: s_cmp_eq_u32 s2, 0
; MOVREL-NEXT: ; implicit-def: $vcc_hi ; MOVREL-NEXT: ; implicit-def: $vcc_hi
; MOVREL-NEXT: v_movreld_b32_e32 v0, v3 ; MOVREL-NEXT: s_cselect_b32 s0, 1, 0
; MOVREL-NEXT: s_and_b32 s0, 1, s0
; MOVREL-NEXT: s_cmp_eq_u32 s2, 1
; MOVREL-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
; MOVREL-NEXT: s_cselect_b32 s1, 1, 0
; MOVREL-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
; MOVREL-NEXT: s_and_b32 s1, 1, s1
; MOVREL-NEXT: s_cmp_eq_u32 s2, 2
; MOVREL-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s1
; MOVREL-NEXT: s_cselect_b32 s2, 1, 0
; MOVREL-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
; MOVREL-NEXT: s_and_b32 s2, 1, s2
; MOVREL-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s2
; MOVREL-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
; MOVREL-NEXT: ; return to shader part epilog ; MOVREL-NEXT: ; return to shader part epilog
entry: entry:
%insert = insertelement <3 x float> %vec, float %val, i32 %idx %insert = insertelement <3 x float> %vec, float %val, i32 %idx
ret <3 x float> %insert ret <3 x float> %insert
} }
define amdgpu_ps <5 x i32> @dyn_insertelement_v5i32_s_s_s(<5 x i32> inreg %vec, i32 inreg %val, i32 inreg %idx) { define amdgpu_ps <5 x i32> @dyn_insertelement_v5i32_s_s_s(<5 x i32> inreg %vec, i32 inreg %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v5i32_s_s_s: ; GPRIDX-LABEL: dyn_insertelement_v5i32_s_s_s:
; GPRIDX: ; %bb.0: ; %entry ; GPRIDX: ; %bb.0: ; %entry
; GPRIDX-NEXT: s_mov_b32 s0, s2 ; GPRIDX-NEXT: s_cmp_eq_u32 s8, 0
; GPRIDX-NEXT: s_mov_b32 s1, s3 ; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: s_mov_b32 s2, s4 ; GPRIDX-NEXT: s_and_b32 s0, s0, 1
; GPRIDX-NEXT: s_mov_b32 s3, s5 ; GPRIDX-NEXT: s_cmp_lg_u32 s0, 0
; GPRIDX-NEXT: s_mov_b32 s4, s6 ; GPRIDX-NEXT: s_cselect_b32 s0, s7, s2
; GPRIDX-NEXT: s_mov_b32 m0, s8 ; GPRIDX-NEXT: s_cmp_eq_u32 s8, 1
; GPRIDX-NEXT: s_nop 0 ; GPRIDX-NEXT: s_cselect_b32 s1, 1, 0
; GPRIDX-NEXT: s_movreld_b32 s0, s7 ; GPRIDX-NEXT: s_and_b32 s1, s1, 1
; GPRIDX-NEXT: s_cmp_lg_u32 s1, 0
; GPRIDX-NEXT: s_cselect_b32 s1, s7, s3
; GPRIDX-NEXT: s_cmp_eq_u32 s8, 2
; GPRIDX-NEXT: s_cselect_b32 s2, 1, 0
; GPRIDX-NEXT: s_and_b32 s2, s2, 1
; GPRIDX-NEXT: s_cmp_lg_u32 s2, 0
; GPRIDX-NEXT: s_cselect_b32 s2, s7, s4
; GPRIDX-NEXT: s_cmp_eq_u32 s8, 3
; GPRIDX-NEXT: s_cselect_b32 s3, 1, 0
; GPRIDX-NEXT: s_and_b32 s3, s3, 1
; GPRIDX-NEXT: s_cmp_lg_u32 s3, 0
; GPRIDX-NEXT: s_cselect_b32 s3, s7, s5
; GPRIDX-NEXT: s_cmp_eq_u32 s8, 4
; GPRIDX-NEXT: s_cselect_b32 s4, 1, 0
; GPRIDX-NEXT: s_and_b32 s4, s4, 1
; GPRIDX-NEXT: s_cmp_lg_u32 s4, 0
; GPRIDX-NEXT: s_cselect_b32 s4, s7, s6
; GPRIDX-NEXT: ; return to shader part epilog ; GPRIDX-NEXT: ; return to shader part epilog
; ;
; MOVREL-LABEL: dyn_insertelement_v5i32_s_s_s: ; MOVREL-LABEL: dyn_insertelement_v5i32_s_s_s:
; MOVREL: ; %bb.0: ; %entry ; MOVREL: ; %bb.0: ; %entry
; MOVREL-NEXT: s_mov_b32 s0, s2 ; MOVREL-NEXT: s_cmp_eq_u32 s8, 0
; MOVREL-NEXT: s_mov_b32 m0, s8
; MOVREL-NEXT: s_mov_b32 s1, s3
; MOVREL-NEXT: s_mov_b32 s2, s4
; MOVREL-NEXT: s_mov_b32 s3, s5
; MOVREL-NEXT: s_mov_b32 s4, s6
; MOVREL-NEXT: s_movreld_b32 s0, s7
; MOVREL-NEXT: ; implicit-def: $vcc_hi ; MOVREL-NEXT: ; implicit-def: $vcc_hi
; MOVREL-NEXT: s_cselect_b32 s0, 1, 0
; MOVREL-NEXT: s_and_b32 s0, s0, 1
; MOVREL-NEXT: s_cmp_lg_u32 s0, 0
; MOVREL-NEXT: s_cselect_b32 s0, s7, s2
; MOVREL-NEXT: s_cmp_eq_u32 s8, 1
; MOVREL-NEXT: s_cselect_b32 s1, 1, 0
; MOVREL-NEXT: s_and_b32 s1, s1, 1
; MOVREL-NEXT: s_cmp_lg_u32 s1, 0
; MOVREL-NEXT: s_cselect_b32 s1, s7, s3
; MOVREL-NEXT: s_cmp_eq_u32 s8, 2
; MOVREL-NEXT: s_cselect_b32 s2, 1, 0
; MOVREL-NEXT: s_and_b32 s2, s2, 1
; MOVREL-NEXT: s_cmp_lg_u32 s2, 0
; MOVREL-NEXT: s_cselect_b32 s2, s7, s4
; MOVREL-NEXT: s_cmp_eq_u32 s8, 3
; MOVREL-NEXT: s_cselect_b32 s3, 1, 0
; MOVREL-NEXT: s_and_b32 s3, s3, 1
; MOVREL-NEXT: s_cmp_lg_u32 s3, 0
; MOVREL-NEXT: s_cselect_b32 s3, s7, s5
; MOVREL-NEXT: s_cmp_eq_u32 s8, 4
; MOVREL-NEXT: s_cselect_b32 s4, 1, 0
; MOVREL-NEXT: s_and_b32 s4, s4, 1
; MOVREL-NEXT: s_cmp_lg_u32 s4, 0
; MOVREL-NEXT: s_cselect_b32 s4, s7, s6
; MOVREL-NEXT: ; return to shader part epilog ; MOVREL-NEXT: ; return to shader part epilog
entry: entry:
%insert = insertelement <5 x i32> %vec, i32 %val, i32 %idx %insert = insertelement <5 x i32> %vec, i32 %val, i32 %idx
ret <5 x i32> %insert ret <5 x i32> %insert
} }
define amdgpu_ps <5 x float> @dyn_insertelement_v5i32_v_v_s(<5 x float> %vec, float %val, i32 inreg %idx) { define amdgpu_ps <5 x float> @dyn_insertelement_v5i32_v_v_s(<5 x float> %vec, float %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v5i32_v_v_s: ; GPRIDX-LABEL: dyn_insertelement_v5i32_v_v_s:
; GPRIDX: ; %bb.0: ; %entry ; GPRIDX: ; %bb.0: ; %entry
; GPRIDX-NEXT: s_set_gpr_idx_on s2, gpr_idx(DST) ; GPRIDX-NEXT: s_cmp_eq_u32 s2, 0
; GPRIDX-NEXT: v_mov_b32_e32 v0, v5 ; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: s_set_gpr_idx_off ; GPRIDX-NEXT: s_and_b32 s0, 1, s0
; GPRIDX-NEXT: s_cmp_eq_u32 s2, 1
; GPRIDX-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: s_and_b32 s0, 1, s0
; GPRIDX-NEXT: s_cmp_eq_u32 s2, 2
; GPRIDX-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc
; GPRIDX-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: s_and_b32 s0, 1, s0
; GPRIDX-NEXT: s_cmp_eq_u32 s2, 3
; GPRIDX-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
; GPRIDX-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: s_and_b32 s0, 1, s0
; GPRIDX-NEXT: s_cmp_eq_u32 s2, 4
; GPRIDX-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc
; GPRIDX-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: s_and_b32 s0, 1, s0
; GPRIDX-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
; GPRIDX-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GPRIDX-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
; GPRIDX-NEXT: ; return to shader part epilog ; GPRIDX-NEXT: ; return to shader part epilog
; ;
; MOVREL-LABEL: dyn_insertelement_v5i32_v_v_s: ; MOVREL-LABEL: dyn_insertelement_v5i32_v_v_s:
; MOVREL: ; %bb.0: ; %entry ; MOVREL: ; %bb.0: ; %entry
; MOVREL-NEXT: s_mov_b32 m0, s2 ; MOVREL-NEXT: s_cmp_eq_u32 s2, 0
; MOVREL-NEXT: ; implicit-def: $vcc_hi ; MOVREL-NEXT: ; implicit-def: $vcc_hi
; MOVREL-NEXT: v_movreld_b32_e32 v0, v5 ; MOVREL-NEXT: s_cselect_b32 s0, 1, 0
; MOVREL-NEXT: s_and_b32 s0, 1, s0
; MOVREL-NEXT: s_cmp_eq_u32 s2, 1
; MOVREL-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
; MOVREL-NEXT: s_cselect_b32 s1, 1, 0
; MOVREL-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc_lo
; MOVREL-NEXT: s_and_b32 s1, 1, s1
; MOVREL-NEXT: s_cmp_eq_u32 s2, 2
; MOVREL-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s1
; MOVREL-NEXT: s_cselect_b32 s3, 1, 0
; MOVREL-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo
; MOVREL-NEXT: s_and_b32 s3, 1, s3
; MOVREL-NEXT: s_cmp_eq_u32 s2, 3
; MOVREL-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s3
; MOVREL-NEXT: s_cselect_b32 s4, 1, 0
; MOVREL-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo
; MOVREL-NEXT: s_and_b32 s4, 1, s4
; MOVREL-NEXT: s_cmp_eq_u32 s2, 4
; MOVREL-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s4
; MOVREL-NEXT: s_cselect_b32 s2, 1, 0
; MOVREL-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
; MOVREL-NEXT: s_and_b32 s0, 1, s2
; MOVREL-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
; MOVREL-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc_lo
; MOVREL-NEXT: ; return to shader part epilog ; MOVREL-NEXT: ; return to shader part epilog
entry: entry:
%insert = insertelement <5 x float> %vec, float %val, i32 %idx %insert = insertelement <5 x float> %vec, float %val, i32 %idx
ret <5 x float> %insert ret <5 x float> %insert
} }
define amdgpu_ps <32 x i32> @dyn_insertelement_v32i32_s_s_s(<32 x i32> inreg %vec, i32 inreg %val, i32 inreg %idx) { define amdgpu_ps <32 x i32> @dyn_insertelement_v32i32_s_s_s(<32 x i32> inreg %vec, i32 inreg %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v32i32_s_s_s: ; GPRIDX-LABEL: dyn_insertelement_v32i32_s_s_s:
▲ Show 20 Lines • Show All 95 Lines • ▼ Show 20 Lines
entry: entry:
%insert = insertelement <32 x float> %vec, float %val, i32 %idx %insert = insertelement <32 x float> %vec, float %val, i32 %idx
ret <32 x float> %insert ret <32 x float> %insert
} }
define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_s_s_s_add_1(<8 x float> inreg %vec, float inreg %val, i32 inreg %idx) { define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_s_s_s_add_1(<8 x float> inreg %vec, float inreg %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v8f32_s_s_s_add_1: ; GPRIDX-LABEL: dyn_insertelement_v8f32_s_s_s_add_1:
; GPRIDX: ; %bb.0: ; %entry ; GPRIDX: ; %bb.0: ; %entry
; GPRIDX-NEXT: s_mov_b32 s0, s2 ; GPRIDX-NEXT: s_add_i32 s11, s11, 1
; GPRIDX-NEXT: s_mov_b32 s1, s3 ; GPRIDX-NEXT: s_cmp_eq_u32 s11, 0
; GPRIDX-NEXT: s_mov_b32 s2, s4 ; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: s_mov_b32 s3, s5 ; GPRIDX-NEXT: s_and_b32 s0, s0, 1
; GPRIDX-NEXT: s_mov_b32 s4, s6 ; GPRIDX-NEXT: s_cmp_lg_u32 s0, 0
; GPRIDX-NEXT: s_mov_b32 s5, s7 ; GPRIDX-NEXT: s_cselect_b32 s0, s10, s2
; GPRIDX-NEXT: s_mov_b32 s6, s8 ; GPRIDX-NEXT: s_cmp_eq_u32 s11, 1
; GPRIDX-NEXT: s_mov_b32 s7, s9 ; GPRIDX-NEXT: s_cselect_b32 s1, 1, 0
; GPRIDX-NEXT: s_mov_b32 m0, s11 ; GPRIDX-NEXT: s_and_b32 s1, s1, 1
; GPRIDX-NEXT: s_nop 0 ; GPRIDX-NEXT: s_cmp_lg_u32 s1, 0
; GPRIDX-NEXT: s_movreld_b32 s1, s10 ; GPRIDX-NEXT: s_cselect_b32 s1, s10, s3
; GPRIDX-NEXT: s_cmp_eq_u32 s11, 2
; GPRIDX-NEXT: s_cselect_b32 s2, 1, 0
; GPRIDX-NEXT: s_and_b32 s2, s2, 1
; GPRIDX-NEXT: s_cmp_lg_u32 s2, 0
; GPRIDX-NEXT: s_cselect_b32 s2, s10, s4
; GPRIDX-NEXT: s_cmp_eq_u32 s11, 3
; GPRIDX-NEXT: s_cselect_b32 s3, 1, 0
; GPRIDX-NEXT: s_and_b32 s3, s3, 1
; GPRIDX-NEXT: s_cmp_lg_u32 s3, 0
; GPRIDX-NEXT: s_cselect_b32 s3, s10, s5
; GPRIDX-NEXT: s_cmp_eq_u32 s11, 4
; GPRIDX-NEXT: s_cselect_b32 s4, 1, 0
; GPRIDX-NEXT: s_and_b32 s4, s4, 1
; GPRIDX-NEXT: s_cmp_lg_u32 s4, 0
; GPRIDX-NEXT: s_cselect_b32 s4, s10, s6
; GPRIDX-NEXT: s_cmp_eq_u32 s11, 5
; GPRIDX-NEXT: s_cselect_b32 s5, 1, 0
; GPRIDX-NEXT: s_and_b32 s5, s5, 1
; GPRIDX-NEXT: s_cmp_lg_u32 s5, 0
; GPRIDX-NEXT: s_cselect_b32 s5, s10, s7
; GPRIDX-NEXT: s_cmp_eq_u32 s11, 6
; GPRIDX-NEXT: s_cselect_b32 s6, 1, 0
; GPRIDX-NEXT: s_and_b32 s6, s6, 1
; GPRIDX-NEXT: s_cmp_lg_u32 s6, 0
; GPRIDX-NEXT: s_cselect_b32 s6, s10, s8
; GPRIDX-NEXT: s_cmp_eq_u32 s11, 7
; GPRIDX-NEXT: s_cselect_b32 s7, 1, 0
; GPRIDX-NEXT: s_and_b32 s7, s7, 1
; GPRIDX-NEXT: s_cmp_lg_u32 s7, 0
; GPRIDX-NEXT: s_cselect_b32 s7, s10, s9
; GPRIDX-NEXT: v_mov_b32_e32 v0, s0 ; GPRIDX-NEXT: v_mov_b32_e32 v0, s0
; GPRIDX-NEXT: v_mov_b32_e32 v1, s1 ; GPRIDX-NEXT: v_mov_b32_e32 v1, s1
; GPRIDX-NEXT: v_mov_b32_e32 v2, s2 ; GPRIDX-NEXT: v_mov_b32_e32 v2, s2
; GPRIDX-NEXT: v_mov_b32_e32 v3, s3 ; GPRIDX-NEXT: v_mov_b32_e32 v3, s3
; GPRIDX-NEXT: v_mov_b32_e32 v4, s4 ; GPRIDX-NEXT: v_mov_b32_e32 v4, s4
; GPRIDX-NEXT: v_mov_b32_e32 v5, s5 ; GPRIDX-NEXT: v_mov_b32_e32 v5, s5
; GPRIDX-NEXT: v_mov_b32_e32 v6, s6 ; GPRIDX-NEXT: v_mov_b32_e32 v6, s6
; GPRIDX-NEXT: v_mov_b32_e32 v7, s7 ; GPRIDX-NEXT: v_mov_b32_e32 v7, s7
; GPRIDX-NEXT: ; return to shader part epilog ; GPRIDX-NEXT: ; return to shader part epilog
; ;
; MOVREL-LABEL: dyn_insertelement_v8f32_s_s_s_add_1: ; MOVREL-LABEL: dyn_insertelement_v8f32_s_s_s_add_1:
; MOVREL: ; %bb.0: ; %entry ; MOVREL: ; %bb.0: ; %entry
; MOVREL-NEXT: s_mov_b32 s1, s3 ; MOVREL-NEXT: s_add_i32 s11, s11, 1
; MOVREL-NEXT: s_mov_b32 m0, s11 ; MOVREL-NEXT: ; implicit-def: $vcc_hi
; MOVREL-NEXT: s_mov_b32 s0, s2 ; MOVREL-NEXT: s_cmp_eq_u32 s11, 0
; MOVREL-NEXT: s_mov_b32 s2, s4 ; MOVREL-NEXT: s_cselect_b32 s0, 1, 0
; MOVREL-NEXT: s_mov_b32 s3, s5 ; MOVREL-NEXT: s_and_b32 s0, s0, 1
; MOVREL-NEXT: s_mov_b32 s4, s6 ; MOVREL-NEXT: s_cmp_lg_u32 s0, 0
; MOVREL-NEXT: s_mov_b32 s5, s7 ; MOVREL-NEXT: s_cselect_b32 s0, s10, s2
; MOVREL-NEXT: s_mov_b32 s6, s8 ; MOVREL-NEXT: s_cmp_eq_u32 s11, 1
; MOVREL-NEXT: s_mov_b32 s7, s9
; MOVREL-NEXT: s_movreld_b32 s1, s10
; MOVREL-NEXT: v_mov_b32_e32 v0, s0 ; MOVREL-NEXT: v_mov_b32_e32 v0, s0
; MOVREL-NEXT: s_cselect_b32 s1, 1, 0
; MOVREL-NEXT: s_and_b32 s1, s1, 1
; MOVREL-NEXT: s_cmp_lg_u32 s1, 0
; MOVREL-NEXT: s_cselect_b32 s1, s10, s3
; MOVREL-NEXT: s_cmp_eq_u32 s11, 2
; MOVREL-NEXT: v_mov_b32_e32 v1, s1 ; MOVREL-NEXT: v_mov_b32_e32 v1, s1
; MOVREL-NEXT: s_cselect_b32 s2, 1, 0
; MOVREL-NEXT: s_and_b32 s2, s2, 1
; MOVREL-NEXT: s_cmp_lg_u32 s2, 0
; MOVREL-NEXT: s_cselect_b32 s2, s10, s4
; MOVREL-NEXT: s_cmp_eq_u32 s11, 3
; MOVREL-NEXT: v_mov_b32_e32 v2, s2 ; MOVREL-NEXT: v_mov_b32_e32 v2, s2
; MOVREL-NEXT: s_cselect_b32 s3, 1, 0
; MOVREL-NEXT: s_and_b32 s3, s3, 1
; MOVREL-NEXT: s_cmp_lg_u32 s3, 0
; MOVREL-NEXT: s_cselect_b32 s3, s10, s5
; MOVREL-NEXT: s_cmp_eq_u32 s11, 4
; MOVREL-NEXT: v_mov_b32_e32 v3, s3 ; MOVREL-NEXT: v_mov_b32_e32 v3, s3
; MOVREL-NEXT: s_cselect_b32 s4, 1, 0
; MOVREL-NEXT: s_and_b32 s4, s4, 1
; MOVREL-NEXT: s_cmp_lg_u32 s4, 0
; MOVREL-NEXT: s_cselect_b32 s4, s10, s6
; MOVREL-NEXT: s_cmp_eq_u32 s11, 5
; MOVREL-NEXT: v_mov_b32_e32 v4, s4 ; MOVREL-NEXT: v_mov_b32_e32 v4, s4
; MOVREL-NEXT: s_cselect_b32 s5, 1, 0
; MOVREL-NEXT: s_and_b32 s5, s5, 1
; MOVREL-NEXT: s_cmp_lg_u32 s5, 0
; MOVREL-NEXT: s_cselect_b32 s5, s10, s7
; MOVREL-NEXT: s_cmp_eq_u32 s11, 6
; MOVREL-NEXT: v_mov_b32_e32 v5, s5 ; MOVREL-NEXT: v_mov_b32_e32 v5, s5
; MOVREL-NEXT: s_cselect_b32 s6, 1, 0
; MOVREL-NEXT: s_and_b32 s6, s6, 1
; MOVREL-NEXT: s_cmp_lg_u32 s6, 0
; MOVREL-NEXT: s_cselect_b32 s6, s10, s8
; MOVREL-NEXT: s_cmp_eq_u32 s11, 7
; MOVREL-NEXT: v_mov_b32_e32 v6, s6 ; MOVREL-NEXT: v_mov_b32_e32 v6, s6
; MOVREL-NEXT: s_cselect_b32 s7, 1, 0
; MOVREL-NEXT: s_and_b32 s7, s7, 1
; MOVREL-NEXT: s_cmp_lg_u32 s7, 0
; MOVREL-NEXT: s_cselect_b32 s7, s10, s9
; MOVREL-NEXT: v_mov_b32_e32 v7, s7 ; MOVREL-NEXT: v_mov_b32_e32 v7, s7
; MOVREL-NEXT: ; implicit-def: $vcc_hi
; MOVREL-NEXT: ; return to shader part epilog ; MOVREL-NEXT: ; return to shader part epilog
entry: entry:
%idx.add = add i32 %idx, 1 %idx.add = add i32 %idx, 1
%insert = insertelement <8 x float> %vec, float %val, i32 %idx.add %insert = insertelement <8 x float> %vec, float %val, i32 %idx.add
ret <8 x float> %insert ret <8 x float> %insert
} }
define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_s_s_s_add_7(<8 x float> inreg %vec, float inreg %val, i32 inreg %idx) { define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_s_s_s_add_7(<8 x float> inreg %vec, float inreg %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v8f32_s_s_s_add_7: ; GPRIDX-LABEL: dyn_insertelement_v8f32_s_s_s_add_7:
; GPRIDX: ; %bb.0: ; %entry ; GPRIDX: ; %bb.0: ; %entry
; GPRIDX-NEXT: s_mov_b32 s0, s2 ; GPRIDX-NEXT: s_add_i32 s11, s11, 7
; GPRIDX-NEXT: s_mov_b32 s1, s3 ; GPRIDX-NEXT: s_cmp_eq_u32 s11, 0
; GPRIDX-NEXT: s_mov_b32 s2, s4 ; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: s_mov_b32 s3, s5 ; GPRIDX-NEXT: s_and_b32 s0, s0, 1
; GPRIDX-NEXT: s_mov_b32 s4, s6 ; GPRIDX-NEXT: s_cmp_lg_u32 s0, 0
; GPRIDX-NEXT: s_mov_b32 s5, s7 ; GPRIDX-NEXT: s_cselect_b32 s0, s10, s2
; GPRIDX-NEXT: s_mov_b32 s6, s8 ; GPRIDX-NEXT: s_cmp_eq_u32 s11, 1
; GPRIDX-NEXT: s_mov_b32 s7, s9 ; GPRIDX-NEXT: s_cselect_b32 s1, 1, 0
; GPRIDX-NEXT: s_mov_b32 m0, s11 ; GPRIDX-NEXT: s_and_b32 s1, s1, 1
; GPRIDX-NEXT: s_nop 0 ; GPRIDX-NEXT: s_cmp_lg_u32 s1, 0
; GPRIDX-NEXT: s_movreld_b32 s7, s10 ; GPRIDX-NEXT: s_cselect_b32 s1, s10, s3
; GPRIDX-NEXT: s_cmp_eq_u32 s11, 2
; GPRIDX-NEXT: s_cselect_b32 s2, 1, 0
; GPRIDX-NEXT: s_and_b32 s2, s2, 1
; GPRIDX-NEXT: s_cmp_lg_u32 s2, 0
; GPRIDX-NEXT: s_cselect_b32 s2, s10, s4
; GPRIDX-NEXT: s_cmp_eq_u32 s11, 3
; GPRIDX-NEXT: s_cselect_b32 s3, 1, 0
; GPRIDX-NEXT: s_and_b32 s3, s3, 1
; GPRIDX-NEXT: s_cmp_lg_u32 s3, 0
; GPRIDX-NEXT: s_cselect_b32 s3, s10, s5
; GPRIDX-NEXT: s_cmp_eq_u32 s11, 4
; GPRIDX-NEXT: s_cselect_b32 s4, 1, 0
; GPRIDX-NEXT: s_and_b32 s4, s4, 1
; GPRIDX-NEXT: s_cmp_lg_u32 s4, 0
; GPRIDX-NEXT: s_cselect_b32 s4, s10, s6
; GPRIDX-NEXT: s_cmp_eq_u32 s11, 5
; GPRIDX-NEXT: s_cselect_b32 s5, 1, 0
; GPRIDX-NEXT: s_and_b32 s5, s5, 1
; GPRIDX-NEXT: s_cmp_lg_u32 s5, 0
; GPRIDX-NEXT: s_cselect_b32 s5, s10, s7
; GPRIDX-NEXT: s_cmp_eq_u32 s11, 6
; GPRIDX-NEXT: s_cselect_b32 s6, 1, 0
; GPRIDX-NEXT: s_and_b32 s6, s6, 1
; GPRIDX-NEXT: s_cmp_lg_u32 s6, 0
; GPRIDX-NEXT: s_cselect_b32 s6, s10, s8
; GPRIDX-NEXT: s_cmp_eq_u32 s11, 7
; GPRIDX-NEXT: s_cselect_b32 s7, 1, 0
; GPRIDX-NEXT: s_and_b32 s7, s7, 1
; GPRIDX-NEXT: s_cmp_lg_u32 s7, 0
; GPRIDX-NEXT: s_cselect_b32 s7, s10, s9
; GPRIDX-NEXT: v_mov_b32_e32 v0, s0 ; GPRIDX-NEXT: v_mov_b32_e32 v0, s0
; GPRIDX-NEXT: v_mov_b32_e32 v1, s1 ; GPRIDX-NEXT: v_mov_b32_e32 v1, s1
; GPRIDX-NEXT: v_mov_b32_e32 v2, s2 ; GPRIDX-NEXT: v_mov_b32_e32 v2, s2
; GPRIDX-NEXT: v_mov_b32_e32 v3, s3 ; GPRIDX-NEXT: v_mov_b32_e32 v3, s3
; GPRIDX-NEXT: v_mov_b32_e32 v4, s4 ; GPRIDX-NEXT: v_mov_b32_e32 v4, s4
; GPRIDX-NEXT: v_mov_b32_e32 v5, s5 ; GPRIDX-NEXT: v_mov_b32_e32 v5, s5
; GPRIDX-NEXT: v_mov_b32_e32 v6, s6 ; GPRIDX-NEXT: v_mov_b32_e32 v6, s6
; GPRIDX-NEXT: v_mov_b32_e32 v7, s7 ; GPRIDX-NEXT: v_mov_b32_e32 v7, s7
; GPRIDX-NEXT: ; return to shader part epilog ; GPRIDX-NEXT: ; return to shader part epilog
; ;
; MOVREL-LABEL: dyn_insertelement_v8f32_s_s_s_add_7: ; MOVREL-LABEL: dyn_insertelement_v8f32_s_s_s_add_7:
; MOVREL: ; %bb.0: ; %entry ; MOVREL: ; %bb.0: ; %entry
; MOVREL-NEXT: s_mov_b32 s1, s3 ; MOVREL-NEXT: s_add_i32 s11, s11, 7
; MOVREL-NEXT: s_mov_b32 s3, s5 ; MOVREL-NEXT: ; implicit-def: $vcc_hi
; MOVREL-NEXT: s_mov_b32 s5, s7 ; MOVREL-NEXT: s_cmp_eq_u32 s11, 0
; MOVREL-NEXT: s_mov_b32 s7, s9 ; MOVREL-NEXT: s_cselect_b32 s0, 1, 0
; MOVREL-NEXT: s_mov_b32 m0, s11 ; MOVREL-NEXT: s_and_b32 s0, s0, 1
; MOVREL-NEXT: s_mov_b32 s0, s2 ; MOVREL-NEXT: s_cmp_lg_u32 s0, 0
; MOVREL-NEXT: s_mov_b32 s2, s4 ; MOVREL-NEXT: s_cselect_b32 s0, s10, s2
; MOVREL-NEXT: s_mov_b32 s4, s6 ; MOVREL-NEXT: s_cmp_eq_u32 s11, 1
; MOVREL-NEXT: s_mov_b32 s6, s8
; MOVREL-NEXT: s_movreld_b32 s7, s10
; MOVREL-NEXT: v_mov_b32_e32 v0, s0 ; MOVREL-NEXT: v_mov_b32_e32 v0, s0
; MOVREL-NEXT: s_cselect_b32 s1, 1, 0
; MOVREL-NEXT: s_and_b32 s1, s1, 1
; MOVREL-NEXT: s_cmp_lg_u32 s1, 0
; MOVREL-NEXT: s_cselect_b32 s1, s10, s3
; MOVREL-NEXT: s_cmp_eq_u32 s11, 2
; MOVREL-NEXT: v_mov_b32_e32 v1, s1 ; MOVREL-NEXT: v_mov_b32_e32 v1, s1
; MOVREL-NEXT: s_cselect_b32 s2, 1, 0
; MOVREL-NEXT: s_and_b32 s2, s2, 1
; MOVREL-NEXT: s_cmp_lg_u32 s2, 0
; MOVREL-NEXT: s_cselect_b32 s2, s10, s4
; MOVREL-NEXT: s_cmp_eq_u32 s11, 3
; MOVREL-NEXT: v_mov_b32_e32 v2, s2 ; MOVREL-NEXT: v_mov_b32_e32 v2, s2
; MOVREL-NEXT: s_cselect_b32 s3, 1, 0
; MOVREL-NEXT: s_and_b32 s3, s3, 1
; MOVREL-NEXT: s_cmp_lg_u32 s3, 0
; MOVREL-NEXT: s_cselect_b32 s3, s10, s5
; MOVREL-NEXT: s_cmp_eq_u32 s11, 4
; MOVREL-NEXT: v_mov_b32_e32 v3, s3 ; MOVREL-NEXT: v_mov_b32_e32 v3, s3
; MOVREL-NEXT: s_cselect_b32 s4, 1, 0
; MOVREL-NEXT: s_and_b32 s4, s4, 1
; MOVREL-NEXT: s_cmp_lg_u32 s4, 0
; MOVREL-NEXT: s_cselect_b32 s4, s10, s6
; MOVREL-NEXT: s_cmp_eq_u32 s11, 5
; MOVREL-NEXT: v_mov_b32_e32 v4, s4 ; MOVREL-NEXT: v_mov_b32_e32 v4, s4
; MOVREL-NEXT: s_cselect_b32 s5, 1, 0
; MOVREL-NEXT: s_and_b32 s5, s5, 1
; MOVREL-NEXT: s_cmp_lg_u32 s5, 0
; MOVREL-NEXT: s_cselect_b32 s5, s10, s7
; MOVREL-NEXT: s_cmp_eq_u32 s11, 6
; MOVREL-NEXT: v_mov_b32_e32 v5, s5 ; MOVREL-NEXT: v_mov_b32_e32 v5, s5
; MOVREL-NEXT: s_cselect_b32 s6, 1, 0
; MOVREL-NEXT: s_and_b32 s6, s6, 1
; MOVREL-NEXT: s_cmp_lg_u32 s6, 0
; MOVREL-NEXT: s_cselect_b32 s6, s10, s8
; MOVREL-NEXT: s_cmp_eq_u32 s11, 7
; MOVREL-NEXT: v_mov_b32_e32 v6, s6 ; MOVREL-NEXT: v_mov_b32_e32 v6, s6
; MOVREL-NEXT: s_cselect_b32 s7, 1, 0
; MOVREL-NEXT: s_and_b32 s7, s7, 1
; MOVREL-NEXT: s_cmp_lg_u32 s7, 0
; MOVREL-NEXT: s_cselect_b32 s7, s10, s9
; MOVREL-NEXT: v_mov_b32_e32 v7, s7 ; MOVREL-NEXT: v_mov_b32_e32 v7, s7
; MOVREL-NEXT: ; implicit-def: $vcc_hi
; MOVREL-NEXT: ; return to shader part epilog ; MOVREL-NEXT: ; return to shader part epilog
entry: entry:
%idx.add = add i32 %idx, 7 %idx.add = add i32 %idx, 7
%insert = insertelement <8 x float> %vec, float %val, i32 %idx.add %insert = insertelement <8 x float> %vec, float %val, i32 %idx.add
ret <8 x float> %insert ret <8 x float> %insert
} }
define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_v_v_v_add_1(<8 x float> %vec, float %val, i32 %idx) { define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_v_v_v_add_1(<8 x float> %vec, float %val, i32 %idx) {
; GPRIDX-LABEL: dyn_insertelement_v8f32_v_v_v_add_1: ; GPRIDX-LABEL: dyn_insertelement_v8f32_v_v_v_add_1:
; GPRIDX: ; %bb.0: ; %entry ; GPRIDX: ; %bb.0: ; %entry
; GPRIDX-NEXT: s_mov_b64 s[0:1], exec ; GPRIDX-NEXT: v_add_u32_e32 v9, 1, v9
; GPRIDX-NEXT: BB29_1: ; =>This Inner Loop Header: Depth=1 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 0, v9
; GPRIDX-NEXT: v_readfirstlane_b32 s2, v9 ; GPRIDX-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, s2, v9 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 1, v9
; GPRIDX-NEXT: s_set_gpr_idx_on s2, gpr_idx(DST) ; GPRIDX-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc
; GPRIDX-NEXT: v_mov_b32_e32 v17, v7 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 2, v9
; GPRIDX-NEXT: v_mov_b32_e32 v16, v6 ; GPRIDX-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc
; GPRIDX-NEXT: v_mov_b32_e32 v15, v5 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 3, v9
; GPRIDX-NEXT: v_mov_b32_e32 v14, v4 ; GPRIDX-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc
; GPRIDX-NEXT: v_mov_b32_e32 v13, v3 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 4, v9
; GPRIDX-NEXT: v_mov_b32_e32 v12, v2 ; GPRIDX-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc
; GPRIDX-NEXT: v_mov_b32_e32 v11, v1 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 5, v9
; GPRIDX-NEXT: v_mov_b32_e32 v10, v0 ; GPRIDX-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc
; GPRIDX-NEXT: v_mov_b32_e32 v11, v8 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 6, v9
; GPRIDX-NEXT: s_set_gpr_idx_off ; GPRIDX-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc
; GPRIDX-NEXT: s_and_saveexec_b64 vcc, vcc ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 7, v9
; GPRIDX-NEXT: s_xor_b64 exec, exec, vcc ; GPRIDX-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc
; GPRIDX-NEXT: s_cbranch_execnz BB29_1
; GPRIDX-NEXT: ; %bb.2:
; GPRIDX-NEXT: s_mov_b64 exec, s[0:1]
; GPRIDX-NEXT: v_mov_b32_e32 v0, v10
; GPRIDX-NEXT: v_mov_b32_e32 v1, v11
; GPRIDX-NEXT: v_mov_b32_e32 v2, v12
; GPRIDX-NEXT: v_mov_b32_e32 v3, v13
; GPRIDX-NEXT: v_mov_b32_e32 v4, v14
; GPRIDX-NEXT: v_mov_b32_e32 v5, v15
; GPRIDX-NEXT: v_mov_b32_e32 v6, v16
; GPRIDX-NEXT: v_mov_b32_e32 v7, v17
; GPRIDX-NEXT: ; return to shader part epilog ; GPRIDX-NEXT: ; return to shader part epilog
; ;
; MOVREL-LABEL: dyn_insertelement_v8f32_v_v_v_add_1: ; MOVREL-LABEL: dyn_insertelement_v8f32_v_v_v_add_1:
; MOVREL: ; %bb.0: ; %entry ; MOVREL: ; %bb.0: ; %entry
; MOVREL-NEXT: s_mov_b32 s0, exec_lo ; MOVREL-NEXT: v_add_nc_u32_e32 v9, 1, v9
; MOVREL-NEXT: ; implicit-def: $vcc_hi ; MOVREL-NEXT: ; implicit-def: $vcc_hi
; MOVREL-NEXT: BB29_1: ; =>This Inner Loop Header: Depth=1 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v9
; MOVREL-NEXT: v_readfirstlane_b32 s1, v9 ; MOVREL-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc_lo
; MOVREL-NEXT: v_mov_b32_e32 v17, v7 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v9
; MOVREL-NEXT: v_mov_b32_e32 v11, v1 ; MOVREL-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc_lo
; MOVREL-NEXT: v_mov_b32_e32 v16, v6 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v9
; MOVREL-NEXT: v_mov_b32_e32 v15, v5 ; MOVREL-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc_lo
; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, s1, v9 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v9
; MOVREL-NEXT: s_mov_b32 m0, s1 ; MOVREL-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc_lo
; MOVREL-NEXT: v_mov_b32_e32 v14, v4 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v9
; MOVREL-NEXT: v_mov_b32_e32 v13, v3 ; MOVREL-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc_lo
; MOVREL-NEXT: v_mov_b32_e32 v12, v2 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v9
; MOVREL-NEXT: v_mov_b32_e32 v10, v0 ; MOVREL-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc_lo
; MOVREL-NEXT: v_movreld_b32_e32 v11, v8 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v9
; MOVREL-NEXT: s_and_saveexec_b32 vcc_lo, vcc_lo ; MOVREL-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc_lo
; MOVREL-NEXT: s_xor_b32 exec_lo, exec_lo, vcc_lo ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v9
; MOVREL-NEXT: s_cbranch_execnz BB29_1 ; MOVREL-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc_lo
; MOVREL-NEXT: ; %bb.2:
; MOVREL-NEXT: s_mov_b32 exec_lo, s0
; MOVREL-NEXT: v_mov_b32_e32 v0, v10
; MOVREL-NEXT: v_mov_b32_e32 v1, v11
; MOVREL-NEXT: v_mov_b32_e32 v2, v12
; MOVREL-NEXT: v_mov_b32_e32 v3, v13
; MOVREL-NEXT: v_mov_b32_e32 v4, v14
; MOVREL-NEXT: v_mov_b32_e32 v5, v15
; MOVREL-NEXT: v_mov_b32_e32 v6, v16
; MOVREL-NEXT: v_mov_b32_e32 v7, v17
; MOVREL-NEXT: ; return to shader part epilog ; MOVREL-NEXT: ; return to shader part epilog
entry: entry:
%idx.add = add i32 %idx, 1 %idx.add = add i32 %idx, 1
%insert = insertelement <8 x float> %vec, float %val, i32 %idx.add %insert = insertelement <8 x float> %vec, float %val, i32 %idx.add
ret <8 x float> %insert ret <8 x float> %insert
} }
define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_v_v_v_add_7(<8 x float> %vec, float %val, i32 %idx) { define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_v_v_v_add_7(<8 x float> %vec, float %val, i32 %idx) {
; GPRIDX-LABEL: dyn_insertelement_v8f32_v_v_v_add_7: ; GPRIDX-LABEL: dyn_insertelement_v8f32_v_v_v_add_7:
; GPRIDX: ; %bb.0: ; %entry ; GPRIDX: ; %bb.0: ; %entry
; GPRIDX-NEXT: s_mov_b64 s[0:1], exec ; GPRIDX-NEXT: v_add_u32_e32 v9, 7, v9
; GPRIDX-NEXT: BB30_1: ; =>This Inner Loop Header: Depth=1 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 0, v9
; GPRIDX-NEXT: v_readfirstlane_b32 s2, v9 ; GPRIDX-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, s2, v9 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 1, v9
; GPRIDX-NEXT: s_set_gpr_idx_on s2, gpr_idx(DST) ; GPRIDX-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc
; GPRIDX-NEXT: v_mov_b32_e32 v17, v7 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 2, v9
; GPRIDX-NEXT: v_mov_b32_e32 v16, v6 ; GPRIDX-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc
; GPRIDX-NEXT: v_mov_b32_e32 v15, v5 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 3, v9
; GPRIDX-NEXT: v_mov_b32_e32 v14, v4 ; GPRIDX-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc
; GPRIDX-NEXT: v_mov_b32_e32 v13, v3 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 4, v9
; GPRIDX-NEXT: v_mov_b32_e32 v12, v2 ; GPRIDX-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc
; GPRIDX-NEXT: v_mov_b32_e32 v11, v1 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 5, v9
; GPRIDX-NEXT: v_mov_b32_e32 v10, v0 ; GPRIDX-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc
; GPRIDX-NEXT: v_mov_b32_e32 v17, v8 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 6, v9
; GPRIDX-NEXT: s_set_gpr_idx_off ; GPRIDX-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc
; GPRIDX-NEXT: s_and_saveexec_b64 vcc, vcc ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 7, v9
; GPRIDX-NEXT: s_xor_b64 exec, exec, vcc ; GPRIDX-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc
; GPRIDX-NEXT: s_cbranch_execnz BB30_1
; GPRIDX-NEXT: ; %bb.2:
; GPRIDX-NEXT: s_mov_b64 exec, s[0:1]
; GPRIDX-NEXT: v_mov_b32_e32 v0, v10
; GPRIDX-NEXT: v_mov_b32_e32 v1, v11
; GPRIDX-NEXT: v_mov_b32_e32 v2, v12
; GPRIDX-NEXT: v_mov_b32_e32 v3, v13
; GPRIDX-NEXT: v_mov_b32_e32 v4, v14
; GPRIDX-NEXT: v_mov_b32_e32 v5, v15
; GPRIDX-NEXT: v_mov_b32_e32 v6, v16
; GPRIDX-NEXT: v_mov_b32_e32 v7, v17
; GPRIDX-NEXT: ; return to shader part epilog ; GPRIDX-NEXT: ; return to shader part epilog
; ;
; MOVREL-LABEL: dyn_insertelement_v8f32_v_v_v_add_7: ; MOVREL-LABEL: dyn_insertelement_v8f32_v_v_v_add_7:
; MOVREL: ; %bb.0: ; %entry ; MOVREL: ; %bb.0: ; %entry
; MOVREL-NEXT: s_mov_b32 s0, exec_lo ; MOVREL-NEXT: v_add_nc_u32_e32 v9, 7, v9
; MOVREL-NEXT: ; implicit-def: $vcc_hi ; MOVREL-NEXT: ; implicit-def: $vcc_hi
; MOVREL-NEXT: BB30_1: ; =>This Inner Loop Header: Depth=1 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v9
; MOVREL-NEXT: v_readfirstlane_b32 s1, v9 ; MOVREL-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc_lo
; MOVREL-NEXT: v_mov_b32_e32 v17, v7 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v9
; MOVREL-NEXT: v_mov_b32_e32 v16, v6 ; MOVREL-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc_lo
; MOVREL-NEXT: v_mov_b32_e32 v15, v5 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v9
; MOVREL-NEXT: v_mov_b32_e32 v14, v4 ; MOVREL-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc_lo
; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, s1, v9 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v9
; MOVREL-NEXT: s_mov_b32 m0, s1 ; MOVREL-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc_lo
; MOVREL-NEXT: v_mov_b32_e32 v13, v3 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v9
; MOVREL-NEXT: v_mov_b32_e32 v12, v2 ; MOVREL-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc_lo
; MOVREL-NEXT: v_mov_b32_e32 v11, v1 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v9
; MOVREL-NEXT: v_mov_b32_e32 v10, v0 ; MOVREL-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc_lo
; MOVREL-NEXT: v_movreld_b32_e32 v17, v8 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v9
; MOVREL-NEXT: s_and_saveexec_b32 vcc_lo, vcc_lo ; MOVREL-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc_lo
; MOVREL-NEXT: s_xor_b32 exec_lo, exec_lo, vcc_lo ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v9
; MOVREL-NEXT: s_cbranch_execnz BB30_1 ; MOVREL-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc_lo
; MOVREL-NEXT: ; %bb.2:
; MOVREL-NEXT: s_mov_b32 exec_lo, s0
; MOVREL-NEXT: v_mov_b32_e32 v0, v10
; MOVREL-NEXT: v_mov_b32_e32 v1, v11
; MOVREL-NEXT: v_mov_b32_e32 v2, v12
; MOVREL-NEXT: v_mov_b32_e32 v3, v13
; MOVREL-NEXT: v_mov_b32_e32 v4, v14
; MOVREL-NEXT: v_mov_b32_e32 v5, v15
; MOVREL-NEXT: v_mov_b32_e32 v6, v16
; MOVREL-NEXT: v_mov_b32_e32 v7, v17
; MOVREL-NEXT: ; return to shader part epilog ; MOVREL-NEXT: ; return to shader part epilog
entry: entry:
%idx.add = add i32 %idx, 7 %idx.add = add i32 %idx, 7
%insert = insertelement <8 x float> %vec, float %val, i32 %idx.add %insert = insertelement <8 x float> %vec, float %val, i32 %idx.add
ret <8 x float> %insert ret <8 x float> %insert
} }
define amdgpu_ps void @dyn_insertelement_v8f64_s_s_s_add_1(<8 x double> inreg %vec, double inreg %val, i32 inreg %idx) { define amdgpu_ps void @dyn_insertelement_v8f64_s_s_s_add_1(<8 x double> inreg %vec, double inreg %val, i32 inreg %idx) {
▲ Show 20 Lines • Show All 1,414 Lines • ▼ Show 20 Lines
entry: entry:
%insert = insertelement <16 x double> %vec, double %val, i32 %idx %insert = insertelement <16 x double> %vec, double %val, i32 %idx
ret <16 x double> %insert ret <16 x double> %insert
} }
define amdgpu_ps <7 x i32> @dyn_insertelement_v7i32_s_s_s(<7 x i32> inreg %vec, i32 inreg %val, i32 inreg %idx) { define amdgpu_ps <7 x i32> @dyn_insertelement_v7i32_s_s_s(<7 x i32> inreg %vec, i32 inreg %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v7i32_s_s_s: ; GPRIDX-LABEL: dyn_insertelement_v7i32_s_s_s:
; GPRIDX: ; %bb.0: ; %entry ; GPRIDX: ; %bb.0: ; %entry
; GPRIDX-NEXT: s_mov_b32 s0, s2 ; GPRIDX-NEXT: s_cmp_eq_u32 s10, 0
; GPRIDX-NEXT: s_mov_b32 s1, s3 ; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: s_mov_b32 s2, s4 ; GPRIDX-NEXT: s_and_b32 s0, s0, 1
; GPRIDX-NEXT: s_mov_b32 s3, s5 ; GPRIDX-NEXT: s_cmp_lg_u32 s0, 0
; GPRIDX-NEXT: s_mov_b32 s4, s6 ; GPRIDX-NEXT: s_cselect_b32 s0, s9, s2
; GPRIDX-NEXT: s_mov_b32 s5, s7 ; GPRIDX-NEXT: s_cmp_eq_u32 s10, 1
; GPRIDX-NEXT: s_mov_b32 s6, s8 ; GPRIDX-NEXT: s_cselect_b32 s1, 1, 0
; GPRIDX-NEXT: s_mov_b32 m0, s10 ; GPRIDX-NEXT: s_and_b32 s1, s1, 1
; GPRIDX-NEXT: s_nop 0 ; GPRIDX-NEXT: s_cmp_lg_u32 s1, 0
; GPRIDX-NEXT: s_movreld_b32 s0, s9 ; GPRIDX-NEXT: s_cselect_b32 s1, s9, s3
; GPRIDX-NEXT: s_cmp_eq_u32 s10, 2
; GPRIDX-NEXT: s_cselect_b32 s2, 1, 0
; GPRIDX-NEXT: s_and_b32 s2, s2, 1
; GPRIDX-NEXT: s_cmp_lg_u32 s2, 0
; GPRIDX-NEXT: s_cselect_b32 s2, s9, s4
; GPRIDX-NEXT: s_cmp_eq_u32 s10, 3
; GPRIDX-NEXT: s_cselect_b32 s3, 1, 0
; GPRIDX-NEXT: s_and_b32 s3, s3, 1
; GPRIDX-NEXT: s_cmp_lg_u32 s3, 0
; GPRIDX-NEXT: s_cselect_b32 s3, s9, s5
; GPRIDX-NEXT: s_cmp_eq_u32 s10, 4
; GPRIDX-NEXT: s_cselect_b32 s4, 1, 0
; GPRIDX-NEXT: s_and_b32 s4, s4, 1
; GPRIDX-NEXT: s_cmp_lg_u32 s4, 0
; GPRIDX-NEXT: s_cselect_b32 s4, s9, s6
; GPRIDX-NEXT: s_cmp_eq_u32 s10, 5
; GPRIDX-NEXT: s_cselect_b32 s5, 1, 0
; GPRIDX-NEXT: s_and_b32 s5, s5, 1
; GPRIDX-NEXT: s_cmp_lg_u32 s5, 0
; GPRIDX-NEXT: s_cselect_b32 s5, s9, s7
; GPRIDX-NEXT: s_cmp_eq_u32 s10, 6
; GPRIDX-NEXT: s_cselect_b32 s6, 1, 0
; GPRIDX-NEXT: s_and_b32 s6, s6, 1
; GPRIDX-NEXT: s_cmp_lg_u32 s6, 0
; GPRIDX-NEXT: s_cselect_b32 s6, s9, s8
; GPRIDX-NEXT: ; return to shader part epilog ; GPRIDX-NEXT: ; return to shader part epilog
; ;
; MOVREL-LABEL: dyn_insertelement_v7i32_s_s_s: ; MOVREL-LABEL: dyn_insertelement_v7i32_s_s_s:
; MOVREL: ; %bb.0: ; %entry ; MOVREL: ; %bb.0: ; %entry
; MOVREL-NEXT: s_mov_b32 s0, s2 ; MOVREL-NEXT: s_cmp_eq_u32 s10, 0
; MOVREL-NEXT: s_mov_b32 m0, s10
; MOVREL-NEXT: s_mov_b32 s1, s3
; MOVREL-NEXT: s_mov_b32 s2, s4
; MOVREL-NEXT: s_mov_b32 s3, s5
; MOVREL-NEXT: s_mov_b32 s4, s6
; MOVREL-NEXT: s_mov_b32 s5, s7
; MOVREL-NEXT: s_mov_b32 s6, s8
; MOVREL-NEXT: s_movreld_b32 s0, s9
; MOVREL-NEXT: ; implicit-def: $vcc_hi ; MOVREL-NEXT: ; implicit-def: $vcc_hi
; MOVREL-NEXT: s_cselect_b32 s0, 1, 0
; MOVREL-NEXT: s_and_b32 s0, s0, 1
; MOVREL-NEXT: s_cmp_lg_u32 s0, 0
; MOVREL-NEXT: s_cselect_b32 s0, s9, s2
; MOVREL-NEXT: s_cmp_eq_u32 s10, 1
; MOVREL-NEXT: s_cselect_b32 s1, 1, 0
; MOVREL-NEXT: s_and_b32 s1, s1, 1
; MOVREL-NEXT: s_cmp_lg_u32 s1, 0
; MOVREL-NEXT: s_cselect_b32 s1, s9, s3
; MOVREL-NEXT: s_cmp_eq_u32 s10, 2
; MOVREL-NEXT: s_cselect_b32 s2, 1, 0
; MOVREL-NEXT: s_and_b32 s2, s2, 1
; MOVREL-NEXT: s_cmp_lg_u32 s2, 0
; MOVREL-NEXT: s_cselect_b32 s2, s9, s4
; MOVREL-NEXT: s_cmp_eq_u32 s10, 3
; MOVREL-NEXT: s_cselect_b32 s3, 1, 0
; MOVREL-NEXT: s_and_b32 s3, s3, 1
; MOVREL-NEXT: s_cmp_lg_u32 s3, 0
; MOVREL-NEXT: s_cselect_b32 s3, s9, s5
; MOVREL-NEXT: s_cmp_eq_u32 s10, 4
; MOVREL-NEXT: s_cselect_b32 s4, 1, 0
; MOVREL-NEXT: s_and_b32 s4, s4, 1
; MOVREL-NEXT: s_cmp_lg_u32 s4, 0
; MOVREL-NEXT: s_cselect_b32 s4, s9, s6
; MOVREL-NEXT: s_cmp_eq_u32 s10, 5
; MOVREL-NEXT: s_cselect_b32 s5, 1, 0
; MOVREL-NEXT: s_and_b32 s5, s5, 1
; MOVREL-NEXT: s_cmp_lg_u32 s5, 0
; MOVREL-NEXT: s_cselect_b32 s5, s9, s7
; MOVREL-NEXT: s_cmp_eq_u32 s10, 6
; MOVREL-NEXT: s_cselect_b32 s6, 1, 0
; MOVREL-NEXT: s_and_b32 s6, s6, 1
; MOVREL-NEXT: s_cmp_lg_u32 s6, 0
; MOVREL-NEXT: s_cselect_b32 s6, s9, s8
; MOVREL-NEXT: ; return to shader part epilog ; MOVREL-NEXT: ; return to shader part epilog
entry: entry:
%insert = insertelement <7 x i32> %vec, i32 %val, i32 %idx %insert = insertelement <7 x i32> %vec, i32 %val, i32 %idx
ret <7 x i32> %insert ret <7 x i32> %insert
} }
define amdgpu_ps <7 x i8 addrspace(3)*> @dyn_insertelement_v7p3i8_s_s_s(<7 x i8 addrspace(3)*> inreg %vec, i8 addrspace(3)* inreg %val, i32 inreg %idx) { define amdgpu_ps <7 x i8 addrspace(3)*> @dyn_insertelement_v7p3i8_s_s_s(<7 x i8 addrspace(3)*> inreg %vec, i8 addrspace(3)* inreg %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v7p3i8_s_s_s: ; GPRIDX-LABEL: dyn_insertelement_v7p3i8_s_s_s:
; GPRIDX: ; %bb.0: ; %entry ; GPRIDX: ; %bb.0: ; %entry
; GPRIDX-NEXT: s_mov_b32 s0, s2 ; GPRIDX-NEXT: s_cmp_eq_u32 s10, 0
; GPRIDX-NEXT: s_mov_b32 s1, s3 ; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: s_mov_b32 s2, s4 ; GPRIDX-NEXT: s_and_b32 s0, s0, 1
; GPRIDX-NEXT: s_mov_b32 s3, s5 ; GPRIDX-NEXT: s_cmp_lg_u32 s0, 0
; GPRIDX-NEXT: s_mov_b32 s4, s6 ; GPRIDX-NEXT: s_cselect_b32 s0, s9, s2
; GPRIDX-NEXT: s_mov_b32 s5, s7 ; GPRIDX-NEXT: s_cmp_eq_u32 s10, 1
; GPRIDX-NEXT: s_mov_b32 s6, s8 ; GPRIDX-NEXT: s_cselect_b32 s1, 1, 0
; GPRIDX-NEXT: s_mov_b32 m0, s10 ; GPRIDX-NEXT: s_and_b32 s1, s1, 1
; GPRIDX-NEXT: s_nop 0 ; GPRIDX-NEXT: s_cmp_lg_u32 s1, 0
; GPRIDX-NEXT: s_movreld_b32 s0, s9 ; GPRIDX-NEXT: s_cselect_b32 s1, s9, s3
; GPRIDX-NEXT: s_cmp_eq_u32 s10, 2
; GPRIDX-NEXT: s_cselect_b32 s2, 1, 0
; GPRIDX-NEXT: s_and_b32 s2, s2, 1
; GPRIDX-NEXT: s_cmp_lg_u32 s2, 0
; GPRIDX-NEXT: s_cselect_b32 s2, s9, s4
; GPRIDX-NEXT: s_cmp_eq_u32 s10, 3
; GPRIDX-NEXT: s_cselect_b32 s3, 1, 0
; GPRIDX-NEXT: s_and_b32 s3, s3, 1
; GPRIDX-NEXT: s_cmp_lg_u32 s3, 0
; GPRIDX-NEXT: s_cselect_b32 s3, s9, s5
; GPRIDX-NEXT: s_cmp_eq_u32 s10, 4
; GPRIDX-NEXT: s_cselect_b32 s4, 1, 0
; GPRIDX-NEXT: s_and_b32 s4, s4, 1
; GPRIDX-NEXT: s_cmp_lg_u32 s4, 0
; GPRIDX-NEXT: s_cselect_b32 s4, s9, s6
; GPRIDX-NEXT: s_cmp_eq_u32 s10, 5
; GPRIDX-NEXT: s_cselect_b32 s5, 1, 0
; GPRIDX-NEXT: s_and_b32 s5, s5, 1
; GPRIDX-NEXT: s_cmp_lg_u32 s5, 0
; GPRIDX-NEXT: s_cselect_b32 s5, s9, s7
; GPRIDX-NEXT: s_cmp_eq_u32 s10, 6
; GPRIDX-NEXT: s_cselect_b32 s6, 1, 0
; GPRIDX-NEXT: s_and_b32 s6, s6, 1
; GPRIDX-NEXT: s_cmp_lg_u32 s6, 0
; GPRIDX-NEXT: s_cselect_b32 s6, s9, s8
; GPRIDX-NEXT: ; return to shader part epilog ; GPRIDX-NEXT: ; return to shader part epilog
; ;
; MOVREL-LABEL: dyn_insertelement_v7p3i8_s_s_s: ; MOVREL-LABEL: dyn_insertelement_v7p3i8_s_s_s:
; MOVREL: ; %bb.0: ; %entry ; MOVREL: ; %bb.0: ; %entry
; MOVREL-NEXT: s_mov_b32 s0, s2 ; MOVREL-NEXT: s_cmp_eq_u32 s10, 0
; MOVREL-NEXT: s_mov_b32 m0, s10
; MOVREL-NEXT: s_mov_b32 s1, s3
; MOVREL-NEXT: s_mov_b32 s2, s4
; MOVREL-NEXT: s_mov_b32 s3, s5
; MOVREL-NEXT: s_mov_b32 s4, s6
; MOVREL-NEXT: s_mov_b32 s5, s7
; MOVREL-NEXT: s_mov_b32 s6, s8
; MOVREL-NEXT: s_movreld_b32 s0, s9
; MOVREL-NEXT: ; implicit-def: $vcc_hi ; MOVREL-NEXT: ; implicit-def: $vcc_hi
; MOVREL-NEXT: s_cselect_b32 s0, 1, 0
; MOVREL-NEXT: s_and_b32 s0, s0, 1
; MOVREL-NEXT: s_cmp_lg_u32 s0, 0
; MOVREL-NEXT: s_cselect_b32 s0, s9, s2
; MOVREL-NEXT: s_cmp_eq_u32 s10, 1
; MOVREL-NEXT: s_cselect_b32 s1, 1, 0
; MOVREL-NEXT: s_and_b32 s1, s1, 1
; MOVREL-NEXT: s_cmp_lg_u32 s1, 0
; MOVREL-NEXT: s_cselect_b32 s1, s9, s3
; MOVREL-NEXT: s_cmp_eq_u32 s10, 2
; MOVREL-NEXT: s_cselect_b32 s2, 1, 0
; MOVREL-NEXT: s_and_b32 s2, s2, 1
; MOVREL-NEXT: s_cmp_lg_u32 s2, 0
; MOVREL-NEXT: s_cselect_b32 s2, s9, s4
; MOVREL-NEXT: s_cmp_eq_u32 s10, 3
; MOVREL-NEXT: s_cselect_b32 s3, 1, 0
; MOVREL-NEXT: s_and_b32 s3, s3, 1
; MOVREL-NEXT: s_cmp_lg_u32 s3, 0
; MOVREL-NEXT: s_cselect_b32 s3, s9, s5
; MOVREL-NEXT: s_cmp_eq_u32 s10, 4
; MOVREL-NEXT: s_cselect_b32 s4, 1, 0
; MOVREL-NEXT: s_and_b32 s4, s4, 1
; MOVREL-NEXT: s_cmp_lg_u32 s4, 0
; MOVREL-NEXT: s_cselect_b32 s4, s9, s6
; MOVREL-NEXT: s_cmp_eq_u32 s10, 5
; MOVREL-NEXT: s_cselect_b32 s5, 1, 0
; MOVREL-NEXT: s_and_b32 s5, s5, 1
; MOVREL-NEXT: s_cmp_lg_u32 s5, 0
; MOVREL-NEXT: s_cselect_b32 s5, s9, s7
; MOVREL-NEXT: s_cmp_eq_u32 s10, 6
; MOVREL-NEXT: s_cselect_b32 s6, 1, 0
; MOVREL-NEXT: s_and_b32 s6, s6, 1
; MOVREL-NEXT: s_cmp_lg_u32 s6, 0
; MOVREL-NEXT: s_cselect_b32 s6, s9, s8
; MOVREL-NEXT: ; return to shader part epilog ; MOVREL-NEXT: ; return to shader part epilog
entry: entry:
%insert = insertelement <7 x i8 addrspace(3)*> %vec, i8 addrspace(3)* %val, i32 %idx %insert = insertelement <7 x i8 addrspace(3)*> %vec, i8 addrspace(3)* %val, i32 %idx
ret <7 x i8 addrspace(3)*> %insert ret <7 x i8 addrspace(3)*> %insert
} }
define amdgpu_ps <7 x float> @dyn_insertelement_v7f32_s_v_s(<7 x float> inreg %vec, float %val, i32 inreg %idx) { define amdgpu_ps <7 x float> @dyn_insertelement_v7f32_s_v_s(<7 x float> inreg %vec, float %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v7f32_s_v_s: ; GPRIDX-LABEL: dyn_insertelement_v7f32_s_v_s:
; GPRIDX: ; %bb.0: ; %entry ; GPRIDX: ; %bb.0: ; %entry
; GPRIDX-NEXT: s_mov_b32 s0, s2 ; GPRIDX-NEXT: s_cmp_eq_u32 s9, 0
; GPRIDX-NEXT: s_mov_b32 s1, s3 ; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: s_mov_b32 s2, s4 ; GPRIDX-NEXT: s_and_b32 s0, 1, s0
; GPRIDX-NEXT: s_mov_b32 s3, s5 ; GPRIDX-NEXT: s_cmp_eq_u32 s9, 1
; GPRIDX-NEXT: s_mov_b32 s4, s6 ; GPRIDX-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GPRIDX-NEXT: s_mov_b32 s5, s7 ; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: s_mov_b32 s6, s8 ; GPRIDX-NEXT: s_and_b32 s0, 1, s0
; GPRIDX-NEXT: v_mov_b32_e32 v8, v0 ; GPRIDX-NEXT: v_mov_b32_e32 v1, s2
; GPRIDX-NEXT: v_mov_b32_e32 v0, s0 ; GPRIDX-NEXT: s_cmp_eq_u32 s9, 2
; GPRIDX-NEXT: v_mov_b32_e32 v1, s1 ; GPRIDX-NEXT: v_cndmask_b32_e32 v7, v1, v0, vcc
; GPRIDX-NEXT: v_mov_b32_e32 v2, s2 ; GPRIDX-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GPRIDX-NEXT: v_mov_b32_e32 v3, s3 ; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: v_mov_b32_e32 v4, s4 ; GPRIDX-NEXT: s_and_b32 s0, 1, s0
; GPRIDX-NEXT: v_mov_b32_e32 v5, s5 ; GPRIDX-NEXT: v_mov_b32_e32 v1, s3
; GPRIDX-NEXT: v_mov_b32_e32 v6, s6 ; GPRIDX-NEXT: s_cmp_eq_u32 s9, 3
; GPRIDX-NEXT: v_mov_b32_e32 v7, s7 ; GPRIDX-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc
; GPRIDX-NEXT: s_set_gpr_idx_on s9, gpr_idx(DST) ; GPRIDX-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GPRIDX-NEXT: v_mov_b32_e32 v0, v8 ; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: s_set_gpr_idx_off ; GPRIDX-NEXT: s_and_b32 s0, 1, s0
; GPRIDX-NEXT: v_mov_b32_e32 v2, s4
; GPRIDX-NEXT: s_cmp_eq_u32 s9, 4
; GPRIDX-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
; GPRIDX-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: s_and_b32 s0, 1, s0
; GPRIDX-NEXT: v_mov_b32_e32 v3, s5
; GPRIDX-NEXT: s_cmp_eq_u32 s9, 5
; GPRIDX-NEXT: v_cndmask_b32_e32 v3, v3, v0, vcc
; GPRIDX-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: s_and_b32 s0, 1, s0
; GPRIDX-NEXT: v_mov_b32_e32 v4, s6
; GPRIDX-NEXT: s_cmp_eq_u32 s9, 6
; GPRIDX-NEXT: v_cndmask_b32_e32 v4, v4, v0, vcc
; GPRIDX-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: v_mov_b32_e32 v5, s7
; GPRIDX-NEXT: s_and_b32 s0, 1, s0
; GPRIDX-NEXT: v_cndmask_b32_e32 v5, v5, v0, vcc
; GPRIDX-NEXT: v_mov_b32_e32 v6, s8
; GPRIDX-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GPRIDX-NEXT: v_cndmask_b32_e32 v6, v6, v0, vcc
; GPRIDX-NEXT: v_mov_b32_e32 v0, v7
; GPRIDX-NEXT: ; return to shader part epilog ; GPRIDX-NEXT: ; return to shader part epilog
; ;
; MOVREL-LABEL: dyn_insertelement_v7f32_s_v_s: ; MOVREL-LABEL: dyn_insertelement_v7f32_s_v_s:
; MOVREL: ; %bb.0: ; %entry ; MOVREL: ; %bb.0: ; %entry
; MOVREL-NEXT: s_mov_b32 s0, s2 ; MOVREL-NEXT: s_cmp_eq_u32 s9, 0
; MOVREL-NEXT: s_mov_b32 s1, s3
; MOVREL-NEXT: s_mov_b32 s2, s4
; MOVREL-NEXT: s_mov_b32 s3, s5
; MOVREL-NEXT: s_mov_b32 s4, s6
; MOVREL-NEXT: s_mov_b32 s5, s7
; MOVREL-NEXT: s_mov_b32 s6, s8
; MOVREL-NEXT: v_mov_b32_e32 v8, v0
; MOVREL-NEXT: v_mov_b32_e32 v0, s0
; MOVREL-NEXT: s_mov_b32 m0, s9
; MOVREL-NEXT: v_mov_b32_e32 v1, s1
; MOVREL-NEXT: v_mov_b32_e32 v2, s2
; MOVREL-NEXT: v_mov_b32_e32 v3, s3
; MOVREL-NEXT: v_mov_b32_e32 v4, s4
; MOVREL-NEXT: v_mov_b32_e32 v5, s5
; MOVREL-NEXT: v_mov_b32_e32 v6, s6
; MOVREL-NEXT: v_mov_b32_e32 v7, s7
; MOVREL-NEXT: v_movreld_b32_e32 v0, v8
; MOVREL-NEXT: ; implicit-def: $vcc_hi ; MOVREL-NEXT: ; implicit-def: $vcc_hi
; MOVREL-NEXT: s_cselect_b32 s0, 1, 0
; MOVREL-NEXT: s_and_b32 s0, 1, s0
; MOVREL-NEXT: s_cmp_eq_u32 s9, 1
; MOVREL-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
; MOVREL-NEXT: s_cselect_b32 s1, 1, 0
; MOVREL-NEXT: v_cndmask_b32_e32 v7, s2, v0, vcc_lo
; MOVREL-NEXT: s_and_b32 s1, 1, s1
; MOVREL-NEXT: s_cmp_eq_u32 s9, 2
; MOVREL-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s1
; MOVREL-NEXT: s_cselect_b32 s10, 1, 0
; MOVREL-NEXT: v_cndmask_b32_e32 v1, s3, v0, vcc_lo
; MOVREL-NEXT: s_and_b32 s10, 1, s10
; MOVREL-NEXT: s_cmp_eq_u32 s9, 3
; MOVREL-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s10
; MOVREL-NEXT: s_cselect_b32 s11, 1, 0
; MOVREL-NEXT: v_cndmask_b32_e32 v2, s4, v0, vcc_lo
; MOVREL-NEXT: s_and_b32 s11, 1, s11
; MOVREL-NEXT: s_cmp_eq_u32 s9, 4
; MOVREL-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s11
; MOVREL-NEXT: s_cselect_b32 s12, 1, 0
; MOVREL-NEXT: v_cndmask_b32_e32 v3, s5, v0, vcc_lo
; MOVREL-NEXT: s_and_b32 s12, 1, s12
; MOVREL-NEXT: s_cmp_eq_u32 s9, 5
; MOVREL-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s12
; MOVREL-NEXT: s_cselect_b32 s13, 1, 0
; MOVREL-NEXT: v_cndmask_b32_e32 v4, s6, v0, vcc_lo
; MOVREL-NEXT: s_and_b32 s0, 1, s13
; MOVREL-NEXT: s_cmp_eq_u32 s9, 6
; MOVREL-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
; MOVREL-NEXT: s_cselect_b32 s1, 1, 0
; MOVREL-NEXT: v_cndmask_b32_e32 v5, s7, v0, vcc_lo
; MOVREL-NEXT: s_and_b32 s1, 1, s1
; MOVREL-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s1
; MOVREL-NEXT: v_cndmask_b32_e32 v6, s8, v0, vcc_lo
; MOVREL-NEXT: v_mov_b32_e32 v0, v7
; MOVREL-NEXT: ; return to shader part epilog ; MOVREL-NEXT: ; return to shader part epilog
entry: entry:
%insert = insertelement <7 x float> %vec, float %val, i32 %idx %insert = insertelement <7 x float> %vec, float %val, i32 %idx
ret <7 x float> %insert ret <7 x float> %insert
} }
define amdgpu_ps <7 x float> @dyn_insertelement_v7f32_s_v_v(<7 x float> inreg %vec, float %val, i32 %idx) { define amdgpu_ps <7 x float> @dyn_insertelement_v7f32_s_v_v(<7 x float> inreg %vec, float %val, i32 %idx) {
; GPRIDX-LABEL: dyn_insertelement_v7f32_s_v_v: ; GPRIDX-LABEL: dyn_insertelement_v7f32_s_v_v:
; GPRIDX: ; %bb.0: ; %entry ; GPRIDX: ; %bb.0: ; %entry
; GPRIDX-NEXT: s_mov_b32 s0, s2 ; GPRIDX-NEXT: v_mov_b32_e32 v2, s2
; GPRIDX-NEXT: s_mov_b32 s1, s3 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
; GPRIDX-NEXT: s_mov_b32 s2, s4 ; GPRIDX-NEXT: v_cndmask_b32_e32 v8, v2, v0, vcc
; GPRIDX-NEXT: s_mov_b32 s3, s5 ; GPRIDX-NEXT: v_mov_b32_e32 v2, s3
; GPRIDX-NEXT: s_mov_b32 s4, s6 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1
; GPRIDX-NEXT: s_mov_b32 s5, s7 ; GPRIDX-NEXT: v_cndmask_b32_e32 v7, v2, v0, vcc
; GPRIDX-NEXT: s_mov_b32 s6, s8 ; GPRIDX-NEXT: v_mov_b32_e32 v2, s4
; GPRIDX-NEXT: v_mov_b32_e32 v17, s7 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 2, v1
; GPRIDX-NEXT: v_mov_b32_e32 v8, v0 ; GPRIDX-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
; GPRIDX-NEXT: v_mov_b32_e32 v9, v1 ; GPRIDX-NEXT: v_mov_b32_e32 v3, s5
; GPRIDX-NEXT: v_mov_b32_e32 v16, s6 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 3, v1
; GPRIDX-NEXT: v_mov_b32_e32 v15, s5 ; GPRIDX-NEXT: v_cndmask_b32_e32 v3, v3, v0, vcc
; GPRIDX-NEXT: v_mov_b32_e32 v14, s4 ; GPRIDX-NEXT: v_mov_b32_e32 v4, s6
; GPRIDX-NEXT: v_mov_b32_e32 v13, s3 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 4, v1
; GPRIDX-NEXT: v_mov_b32_e32 v12, s2 ; GPRIDX-NEXT: v_cndmask_b32_e32 v4, v4, v0, vcc
; GPRIDX-NEXT: v_mov_b32_e32 v11, s1 ; GPRIDX-NEXT: v_mov_b32_e32 v5, s7
; GPRIDX-NEXT: v_mov_b32_e32 v10, s0 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 5, v1
; GPRIDX-NEXT: s_mov_b64 s[0:1], exec ; GPRIDX-NEXT: v_cndmask_b32_e32 v5, v5, v0, vcc
; GPRIDX-NEXT: BB46_1: ; =>This Inner Loop Header: Depth=1 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 6, v1
; GPRIDX-NEXT: v_readfirstlane_b32 s2, v9 ; GPRIDX-NEXT: v_mov_b32_e32 v6, s8
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, s2, v9 ; GPRIDX-NEXT: v_cndmask_b32_e32 v6, v6, v0, vcc
; GPRIDX-NEXT: s_set_gpr_idx_on s2, gpr_idx(DST)
; GPRIDX-NEXT: v_mov_b32_e32 v0, v10
; GPRIDX-NEXT: v_mov_b32_e32 v1, v11
; GPRIDX-NEXT: v_mov_b32_e32 v2, v12
; GPRIDX-NEXT: v_mov_b32_e32 v3, v13
; GPRIDX-NEXT: v_mov_b32_e32 v4, v14
; GPRIDX-NEXT: v_mov_b32_e32 v5, v15
; GPRIDX-NEXT: v_mov_b32_e32 v6, v16
; GPRIDX-NEXT: v_mov_b32_e32 v7, v17
; GPRIDX-NEXT: v_mov_b32_e32 v0, v8 ; GPRIDX-NEXT: v_mov_b32_e32 v0, v8
; GPRIDX-NEXT: s_set_gpr_idx_off ; GPRIDX-NEXT: v_mov_b32_e32 v1, v7
; GPRIDX-NEXT: s_and_saveexec_b64 vcc, vcc
; GPRIDX-NEXT: s_xor_b64 exec, exec, vcc
; GPRIDX-NEXT: s_cbranch_execnz BB46_1
; GPRIDX-NEXT: ; %bb.2:
; GPRIDX-NEXT: s_mov_b64 exec, s[0:1]
; GPRIDX-NEXT: ; return to shader part epilog ; GPRIDX-NEXT: ; return to shader part epilog
; ;
; MOVREL-LABEL: dyn_insertelement_v7f32_s_v_v: ; MOVREL-LABEL: dyn_insertelement_v7f32_s_v_v:
; MOVREL: ; %bb.0: ; %entry ; MOVREL: ; %bb.0: ; %entry
; MOVREL-NEXT: s_mov_b32 s0, s2 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
; MOVREL-NEXT: s_mov_b32 s1, s3
; MOVREL-NEXT: s_mov_b32 s2, s4
; MOVREL-NEXT: s_mov_b32 s3, s5
; MOVREL-NEXT: s_mov_b32 s4, s6
; MOVREL-NEXT: s_mov_b32 s5, s7
; MOVREL-NEXT: s_mov_b32 s6, s8
; MOVREL-NEXT: v_mov_b32_e32 v17, s7
; MOVREL-NEXT: v_mov_b32_e32 v13, s3
; MOVREL-NEXT: v_mov_b32_e32 v14, s4
; MOVREL-NEXT: v_mov_b32_e32 v15, s5
; MOVREL-NEXT: v_mov_b32_e32 v16, s6
; MOVREL-NEXT: v_mov_b32_e32 v12, s2
; MOVREL-NEXT: v_mov_b32_e32 v11, s1
; MOVREL-NEXT: v_mov_b32_e32 v10, s0
; MOVREL-NEXT: s_mov_b32 s0, exec_lo
; MOVREL-NEXT: ; implicit-def: $vcc_hi ; MOVREL-NEXT: ; implicit-def: $vcc_hi
; MOVREL-NEXT: BB46_1: ; =>This Inner Loop Header: Depth=1 ; MOVREL-NEXT: v_cndmask_b32_e32 v8, s2, v0, vcc_lo
; MOVREL-NEXT: v_readfirstlane_b32 s1, v1 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
; MOVREL-NEXT: v_mov_b32_e32 v2, v10 ; MOVREL-NEXT: v_cndmask_b32_e32 v7, s3, v0, vcc_lo
; MOVREL-NEXT: v_mov_b32_e32 v3, v11 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v1
; MOVREL-NEXT: v_mov_b32_e32 v4, v12 ; MOVREL-NEXT: v_cndmask_b32_e32 v2, s4, v0, vcc_lo
; MOVREL-NEXT: v_mov_b32_e32 v5, v13 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v1
; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, s1, v1 ; MOVREL-NEXT: v_cndmask_b32_e32 v3, s5, v0, vcc_lo
; MOVREL-NEXT: s_mov_b32 m0, s1 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v1
; MOVREL-NEXT: v_mov_b32_e32 v6, v14 ; MOVREL-NEXT: v_cndmask_b32_e32 v4, s6, v0, vcc_lo
; MOVREL-NEXT: v_mov_b32_e32 v7, v15 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v1
; MOVREL-NEXT: v_mov_b32_e32 v8, v16 ; MOVREL-NEXT: v_cndmask_b32_e32 v5, s7, v0, vcc_lo
; MOVREL-NEXT: v_mov_b32_e32 v9, v17 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v1
; MOVREL-NEXT: v_movreld_b32_e32 v2, v0 ; MOVREL-NEXT: v_mov_b32_e32 v1, v7
; MOVREL-NEXT: s_and_saveexec_b32 vcc_lo, vcc_lo ; MOVREL-NEXT: v_cndmask_b32_e32 v6, s8, v0, vcc_lo
; MOVREL-NEXT: s_xor_b32 exec_lo, exec_lo, vcc_lo ; MOVREL-NEXT: v_mov_b32_e32 v0, v8
; MOVREL-NEXT: s_cbranch_execnz BB46_1
; MOVREL-NEXT: ; %bb.2:
; MOVREL-NEXT: s_mov_b32 exec_lo, s0
; MOVREL-NEXT: v_mov_b32_e32 v0, v2
; MOVREL-NEXT: v_mov_b32_e32 v1, v3
; MOVREL-NEXT: v_mov_b32_e32 v2, v4
; MOVREL-NEXT: v_mov_b32_e32 v3, v5
; MOVREL-NEXT: v_mov_b32_e32 v4, v6
; MOVREL-NEXT: v_mov_b32_e32 v5, v7
; MOVREL-NEXT: v_mov_b32_e32 v6, v8
; MOVREL-NEXT: ; return to shader part epilog ; MOVREL-NEXT: ; return to shader part epilog
entry: entry:
%insert = insertelement <7 x float> %vec, float %val, i32 %idx %insert = insertelement <7 x float> %vec, float %val, i32 %idx
ret <7 x float> %insert ret <7 x float> %insert
} }
define amdgpu_ps <7 x float> @dyn_insertelement_v7f32_v_v_s(<7 x float> %vec, float %val, i32 inreg %idx) { define amdgpu_ps <7 x float> @dyn_insertelement_v7f32_v_v_s(<7 x float> %vec, float %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v7f32_v_v_s: ; GPRIDX-LABEL: dyn_insertelement_v7f32_v_v_s:
; GPRIDX: ; %bb.0: ; %entry ; GPRIDX: ; %bb.0: ; %entry
; GPRIDX-NEXT: s_set_gpr_idx_on s2, gpr_idx(DST) ; GPRIDX-NEXT: s_cmp_eq_u32 s2, 0
; GPRIDX-NEXT: v_mov_b32_e32 v0, v7 ; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: s_set_gpr_idx_off ; GPRIDX-NEXT: s_and_b32 s0, 1, s0
; GPRIDX-NEXT: s_cmp_eq_u32 s2, 1
; GPRIDX-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: s_and_b32 s0, 1, s0
; GPRIDX-NEXT: s_cmp_eq_u32 s2, 2
; GPRIDX-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc
; GPRIDX-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: s_and_b32 s0, 1, s0
; GPRIDX-NEXT: s_cmp_eq_u32 s2, 3
; GPRIDX-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
; GPRIDX-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: s_and_b32 s0, 1, s0
; GPRIDX-NEXT: s_cmp_eq_u32 s2, 4
; GPRIDX-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc
; GPRIDX-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: s_and_b32 s0, 1, s0
; GPRIDX-NEXT: s_cmp_eq_u32 s2, 5
; GPRIDX-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc
; GPRIDX-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: s_and_b32 s0, 1, s0
; GPRIDX-NEXT: s_cmp_eq_u32 s2, 6
; GPRIDX-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
; GPRIDX-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: s_and_b32 s0, 1, s0
; GPRIDX-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
; GPRIDX-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GPRIDX-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc
; GPRIDX-NEXT: ; return to shader part epilog ; GPRIDX-NEXT: ; return to shader part epilog
; ;
; MOVREL-LABEL: dyn_insertelement_v7f32_v_v_s: ; MOVREL-LABEL: dyn_insertelement_v7f32_v_v_s:
; MOVREL: ; %bb.0: ; %entry ; MOVREL: ; %bb.0: ; %entry
; MOVREL-NEXT: s_mov_b32 m0, s2 ; MOVREL-NEXT: s_cmp_eq_u32 s2, 0
; MOVREL-NEXT: ; implicit-def: $vcc_hi ; MOVREL-NEXT: ; implicit-def: $vcc_hi
; MOVREL-NEXT: v_movreld_b32_e32 v0, v7 ; MOVREL-NEXT: s_cselect_b32 s0, 1, 0
; MOVREL-NEXT: s_and_b32 s0, 1, s0
; MOVREL-NEXT: s_cmp_eq_u32 s2, 1
; MOVREL-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
; MOVREL-NEXT: s_cselect_b32 s1, 1, 0
; MOVREL-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc_lo
; MOVREL-NEXT: s_and_b32 s1, 1, s1
; MOVREL-NEXT: s_cmp_eq_u32 s2, 2
; MOVREL-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s1
; MOVREL-NEXT: s_cselect_b32 s3, 1, 0
; MOVREL-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc_lo
; MOVREL-NEXT: s_and_b32 s3, 1, s3
; MOVREL-NEXT: s_cmp_eq_u32 s2, 3
; MOVREL-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s3
; MOVREL-NEXT: s_cselect_b32 s4, 1, 0
; MOVREL-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
; MOVREL-NEXT: s_and_b32 s4, 1, s4
; MOVREL-NEXT: s_cmp_eq_u32 s2, 4
; MOVREL-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s4
; MOVREL-NEXT: s_cselect_b32 s5, 1, 0
; MOVREL-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo
; MOVREL-NEXT: s_and_b32 s5, 1, s5
; MOVREL-NEXT: s_cmp_eq_u32 s2, 5
; MOVREL-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s5
; MOVREL-NEXT: s_cselect_b32 s6, 1, 0
; MOVREL-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc_lo
; MOVREL-NEXT: s_and_b32 s0, 1, s6
; MOVREL-NEXT: s_cmp_eq_u32 s2, 6
; MOVREL-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
; MOVREL-NEXT: s_cselect_b32 s1, 1, 0
; MOVREL-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
; MOVREL-NEXT: s_and_b32 s1, 1, s1
; MOVREL-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s1
; MOVREL-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc_lo
; MOVREL-NEXT: ; return to shader part epilog ; MOVREL-NEXT: ; return to shader part epilog
entry: entry:
%insert = insertelement <7 x float> %vec, float %val, i32 %idx %insert = insertelement <7 x float> %vec, float %val, i32 %idx
ret <7 x float> %insert ret <7 x float> %insert
} }
define amdgpu_ps <7 x float> @dyn_insertelement_v7f32_v_v_v(<7 x float> %vec, float %val, i32 %idx) { define amdgpu_ps <7 x float> @dyn_insertelement_v7f32_v_v_v(<7 x float> %vec, float %val, i32 %idx) {
; GPRIDX-LABEL: dyn_insertelement_v7f32_v_v_v: ; GPRIDX-LABEL: dyn_insertelement_v7f32_v_v_v:
; GPRIDX: ; %bb.0: ; %entry ; GPRIDX: ; %bb.0: ; %entry
; GPRIDX-NEXT: s_mov_b64 s[0:1], exec ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 0, v8
; GPRIDX-NEXT: BB48_1: ; =>This Inner Loop Header: Depth=1 ; GPRIDX-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc
; GPRIDX-NEXT: v_readfirstlane_b32 s2, v8 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 1, v8
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, s2, v8 ; GPRIDX-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
; GPRIDX-NEXT: s_set_gpr_idx_on s2, gpr_idx(DST) ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 2, v8
; GPRIDX-NEXT: v_mov_b32_e32 v16, v7 ; GPRIDX-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc
; GPRIDX-NEXT: v_mov_b32_e32 v15, v6 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 3, v8
; GPRIDX-NEXT: v_mov_b32_e32 v14, v5 ; GPRIDX-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc
; GPRIDX-NEXT: v_mov_b32_e32 v13, v4 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 4, v8
; GPRIDX-NEXT: v_mov_b32_e32 v12, v3 ; GPRIDX-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
; GPRIDX-NEXT: v_mov_b32_e32 v11, v2 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 5, v8
; GPRIDX-NEXT: v_mov_b32_e32 v10, v1 ; GPRIDX-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
; GPRIDX-NEXT: v_mov_b32_e32 v9, v0 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 6, v8
; GPRIDX-NEXT: v_mov_b32_e32 v9, v7 ; GPRIDX-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc
; GPRIDX-NEXT: s_set_gpr_idx_off
; GPRIDX-NEXT: s_and_saveexec_b64 vcc, vcc
; GPRIDX-NEXT: s_xor_b64 exec, exec, vcc
; GPRIDX-NEXT: s_cbranch_execnz BB48_1
; GPRIDX-NEXT: ; %bb.2:
; GPRIDX-NEXT: s_mov_b64 exec, s[0:1]
; GPRIDX-NEXT: v_mov_b32_e32 v0, v9
; GPRIDX-NEXT: v_mov_b32_e32 v1, v10
; GPRIDX-NEXT: v_mov_b32_e32 v2, v11
; GPRIDX-NEXT: v_mov_b32_e32 v3, v12
; GPRIDX-NEXT: v_mov_b32_e32 v4, v13
; GPRIDX-NEXT: v_mov_b32_e32 v5, v14
; GPRIDX-NEXT: v_mov_b32_e32 v6, v15
; GPRIDX-NEXT: ; return to shader part epilog ; GPRIDX-NEXT: ; return to shader part epilog
; ;
; MOVREL-LABEL: dyn_insertelement_v7f32_v_v_v: ; MOVREL-LABEL: dyn_insertelement_v7f32_v_v_v:
; MOVREL: ; %bb.0: ; %entry ; MOVREL: ; %bb.0: ; %entry
; MOVREL-NEXT: s_mov_b32 s0, exec_lo ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v8
; MOVREL-NEXT: ; implicit-def: $vcc_hi ; MOVREL-NEXT: ; implicit-def: $vcc_hi
; MOVREL-NEXT: BB48_1: ; =>This Inner Loop Header: Depth=1 ; MOVREL-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc_lo
; MOVREL-NEXT: v_readfirstlane_b32 s1, v8 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v8
; MOVREL-NEXT: v_mov_b32_e32 v16, v7 ; MOVREL-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc_lo
; MOVREL-NEXT: v_mov_b32_e32 v9, v0 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v8
; MOVREL-NEXT: v_mov_b32_e32 v15, v6 ; MOVREL-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
; MOVREL-NEXT: v_mov_b32_e32 v14, v5 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v8
; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, s1, v8 ; MOVREL-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo
; MOVREL-NEXT: s_mov_b32 m0, s1 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v8
; MOVREL-NEXT: v_mov_b32_e32 v13, v4 ; MOVREL-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc_lo
; MOVREL-NEXT: v_mov_b32_e32 v12, v3 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v8
; MOVREL-NEXT: v_mov_b32_e32 v11, v2 ; MOVREL-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
; MOVREL-NEXT: v_mov_b32_e32 v10, v1 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v8
; MOVREL-NEXT: v_movreld_b32_e32 v9, v7 ; MOVREL-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc_lo
; MOVREL-NEXT: s_and_saveexec_b32 vcc_lo, vcc_lo
; MOVREL-NEXT: s_xor_b32 exec_lo, exec_lo, vcc_lo
; MOVREL-NEXT: s_cbranch_execnz BB48_1
; MOVREL-NEXT: ; %bb.2:
; MOVREL-NEXT: s_mov_b32 exec_lo, s0
; MOVREL-NEXT: v_mov_b32_e32 v0, v9
; MOVREL-NEXT: v_mov_b32_e32 v1, v10
; MOVREL-NEXT: v_mov_b32_e32 v2, v11
; MOVREL-NEXT: v_mov_b32_e32 v3, v12
; MOVREL-NEXT: v_mov_b32_e32 v4, v13
; MOVREL-NEXT: v_mov_b32_e32 v5, v14
; MOVREL-NEXT: v_mov_b32_e32 v6, v15
; MOVREL-NEXT: ; return to shader part epilog ; MOVREL-NEXT: ; return to shader part epilog
entry: entry:
%insert = insertelement <7 x float> %vec, float %val, i32 %idx %insert = insertelement <7 x float> %vec, float %val, i32 %idx
ret <7 x float> %insert ret <7 x float> %insert
} }
define amdgpu_ps <7 x double> @dyn_insertelement_v7f64_s_s_s(<7 x double> inreg %vec, double inreg %val, i32 inreg %idx) { define amdgpu_ps <7 x double> @dyn_insertelement_v7f64_s_s_s(<7 x double> inreg %vec, double inreg %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v7f64_s_s_s: ; GPRIDX-LABEL: dyn_insertelement_v7f64_s_s_s:
▲ Show 20 Lines • Show All 466 Lines • ▼ Show 20 Lines
entry: entry:
%insert = insertelement <7 x double> %vec, double %val, i32 %idx %insert = insertelement <7 x double> %vec, double %val, i32 %idx
ret <7 x double> %insert ret <7 x double> %insert
} }
define amdgpu_ps <5 x double> @dyn_insertelement_v5f64_s_s_s(<5 x double> inreg %vec, double inreg %val, i32 inreg %idx) { define amdgpu_ps <5 x double> @dyn_insertelement_v5f64_s_s_s(<5 x double> inreg %vec, double inreg %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v5f64_s_s_s: ; GPRIDX-LABEL: dyn_insertelement_v5f64_s_s_s:
; GPRIDX: ; %bb.0: ; %entry ; GPRIDX: ; %bb.0: ; %entry
; GPRIDX-NEXT: s_mov_b32 s0, s2 ; GPRIDX-NEXT: s_cmp_eq_u32 s14, 0
; GPRIDX-NEXT: s_mov_b32 s1, s3 ; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: s_mov_b32 s2, s4 ; GPRIDX-NEXT: s_and_b32 s0, s0, 1
; GPRIDX-NEXT: s_mov_b32 s3, s5 ; GPRIDX-NEXT: s_cmp_lg_u32 s0, 0
; GPRIDX-NEXT: s_mov_b32 s4, s6 ; GPRIDX-NEXT: s_cselect_b64 s[0:1], s[12:13], s[2:3]
; GPRIDX-NEXT: s_mov_b32 s5, s7 ; GPRIDX-NEXT: s_cmp_eq_u32 s14, 1
; GPRIDX-NEXT: s_mov_b32 s6, s8 ; GPRIDX-NEXT: s_cselect_b32 s2, 1, 0
; GPRIDX-NEXT: s_mov_b32 s7, s9 ; GPRIDX-NEXT: s_and_b32 s2, s2, 1
; GPRIDX-NEXT: s_mov_b32 s8, s10 ; GPRIDX-NEXT: s_cmp_lg_u32 s2, 0
; GPRIDX-NEXT: s_mov_b32 s9, s11 ; GPRIDX-NEXT: s_cselect_b64 s[2:3], s[12:13], s[4:5]
; GPRIDX-NEXT: s_mov_b32 m0, s14 ; GPRIDX-NEXT: s_cmp_eq_u32 s14, 2
; GPRIDX-NEXT: s_nop 0 ; GPRIDX-NEXT: s_cselect_b32 s4, 1, 0
; GPRIDX-NEXT: s_movreld_b64 s[0:1], s[12:13] ; GPRIDX-NEXT: s_and_b32 s4, s4, 1
; GPRIDX-NEXT: s_cmp_lg_u32 s4, 0
; GPRIDX-NEXT: s_cselect_b64 s[4:5], s[12:13], s[6:7]
; GPRIDX-NEXT: s_cmp_eq_u32 s14, 3
; GPRIDX-NEXT: s_cselect_b32 s6, 1, 0
; GPRIDX-NEXT: s_and_b32 s6, s6, 1
; GPRIDX-NEXT: s_cmp_lg_u32 s6, 0
; GPRIDX-NEXT: s_cselect_b64 s[6:7], s[12:13], s[8:9]
; GPRIDX-NEXT: s_cmp_eq_u32 s14, 4
; GPRIDX-NEXT: s_cselect_b32 s8, 1, 0
; GPRIDX-NEXT: s_and_b32 s8, s8, 1
; GPRIDX-NEXT: s_cmp_lg_u32 s8, 0
; GPRIDX-NEXT: s_cselect_b64 s[8:9], s[12:13], s[10:11]
; GPRIDX-NEXT: ; return to shader part epilog ; GPRIDX-NEXT: ; return to shader part epilog
; ;
; MOVREL-LABEL: dyn_insertelement_v5f64_s_s_s: ; MOVREL-LABEL: dyn_insertelement_v5f64_s_s_s:
; MOVREL: ; %bb.0: ; %entry ; MOVREL: ; %bb.0: ; %entry
; MOVREL-NEXT: s_mov_b32 s0, s2 ; MOVREL-NEXT: s_cmp_eq_u32 s14, 0
; MOVREL-NEXT: s_mov_b32 s1, s3
; MOVREL-NEXT: s_mov_b32 m0, s14
; MOVREL-NEXT: s_mov_b32 s2, s4
; MOVREL-NEXT: s_mov_b32 s3, s5
; MOVREL-NEXT: s_mov_b32 s4, s6
; MOVREL-NEXT: s_mov_b32 s5, s7
; MOVREL-NEXT: s_mov_b32 s6, s8
; MOVREL-NEXT: s_mov_b32 s7, s9
; MOVREL-NEXT: s_mov_b32 s8, s10
; MOVREL-NEXT: s_mov_b32 s9, s11
; MOVREL-NEXT: s_movreld_b64 s[0:1], s[12:13]
; MOVREL-NEXT: ; implicit-def: $vcc_hi ; MOVREL-NEXT: ; implicit-def: $vcc_hi
; MOVREL-NEXT: s_cselect_b32 s0, 1, 0
; MOVREL-NEXT: s_and_b32 s0, s0, 1
; MOVREL-NEXT: s_cmp_lg_u32 s0, 0
; MOVREL-NEXT: s_cselect_b64 s[0:1], s[12:13], s[2:3]
; MOVREL-NEXT: s_cmp_eq_u32 s14, 1
; MOVREL-NEXT: s_cselect_b32 s2, 1, 0
; MOVREL-NEXT: s_and_b32 s2, s2, 1
; MOVREL-NEXT: s_cmp_lg_u32 s2, 0
; MOVREL-NEXT: s_cselect_b64 s[2:3], s[12:13], s[4:5]
; MOVREL-NEXT: s_cmp_eq_u32 s14, 2
; MOVREL-NEXT: s_cselect_b32 s4, 1, 0
; MOVREL-NEXT: s_and_b32 s4, s4, 1
; MOVREL-NEXT: s_cmp_lg_u32 s4, 0
; MOVREL-NEXT: s_cselect_b64 s[4:5], s[12:13], s[6:7]
; MOVREL-NEXT: s_cmp_eq_u32 s14, 3
; MOVREL-NEXT: s_cselect_b32 s6, 1, 0
; MOVREL-NEXT: s_and_b32 s6, s6, 1
; MOVREL-NEXT: s_cmp_lg_u32 s6, 0
; MOVREL-NEXT: s_cselect_b64 s[6:7], s[12:13], s[8:9]
; MOVREL-NEXT: s_cmp_eq_u32 s14, 4
; MOVREL-NEXT: s_cselect_b32 s8, 1, 0
; MOVREL-NEXT: s_and_b32 s8, s8, 1
; MOVREL-NEXT: s_cmp_lg_u32 s8, 0
; MOVREL-NEXT: s_cselect_b64 s[8:9], s[12:13], s[10:11]
; MOVREL-NEXT: ; return to shader part epilog ; MOVREL-NEXT: ; return to shader part epilog
entry: entry:
%insert = insertelement <5 x double> %vec, double %val, i32 %idx %insert = insertelement <5 x double> %vec, double %val, i32 %idx
ret <5 x double> %insert ret <5 x double> %insert
} }
define amdgpu_ps <5 x double> @dyn_insertelement_v5f64_s_v_s(<5 x double> inreg %vec, double %val, i32 inreg %idx) { define amdgpu_ps <5 x double> @dyn_insertelement_v5f64_s_v_s(<5 x double> inreg %vec, double %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v5f64_s_v_s: ; GPRIDX-LABEL: dyn_insertelement_v5f64_s_v_s:
; GPRIDX: ; %bb.0: ; %entry ; GPRIDX: ; %bb.0: ; %entry
; GPRIDX-NEXT: s_mov_b32 s0, s2 ; GPRIDX-NEXT: s_cmp_eq_u32 s12, 0
; GPRIDX-NEXT: s_mov_b32 s1, s3 ; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: s_mov_b32 s2, s4 ; GPRIDX-NEXT: s_and_b32 s0, 1, s0
; GPRIDX-NEXT: s_mov_b32 s3, s5 ; GPRIDX-NEXT: s_cmp_eq_u32 s12, 1
; GPRIDX-NEXT: s_mov_b32 s4, s6 ; GPRIDX-NEXT: s_cselect_b32 s1, 1, 0
; GPRIDX-NEXT: s_mov_b32 s5, s7 ; GPRIDX-NEXT: v_mov_b32_e32 v2, s2
; GPRIDX-NEXT: s_mov_b32 s6, s8 ; GPRIDX-NEXT: s_and_b32 s2, 1, s1
; GPRIDX-NEXT: s_mov_b32 s7, s9 ; GPRIDX-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GPRIDX-NEXT: s_mov_b32 s8, s10 ; GPRIDX-NEXT: s_cmp_eq_u32 s12, 2
; GPRIDX-NEXT: s_mov_b32 s9, s11 ; GPRIDX-NEXT: v_mov_b32_e32 v3, s3
; GPRIDX-NEXT: v_mov_b32_e32 v17, s15 ; GPRIDX-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
; GPRIDX-NEXT: v_mov_b32_e32 v16, s14 ; GPRIDX-NEXT: s_cselect_b32 s3, 1, 0
; GPRIDX-NEXT: v_mov_b32_e32 v15, s13
; GPRIDX-NEXT: v_mov_b32_e32 v14, s12
; GPRIDX-NEXT: v_mov_b32_e32 v13, s11
; GPRIDX-NEXT: v_mov_b32_e32 v12, s10
; GPRIDX-NEXT: v_mov_b32_e32 v11, s9
; GPRIDX-NEXT: v_mov_b32_e32 v10, s8
; GPRIDX-NEXT: v_mov_b32_e32 v9, s7
; GPRIDX-NEXT: v_mov_b32_e32 v8, s6
; GPRIDX-NEXT: v_mov_b32_e32 v7, s5
; GPRIDX-NEXT: v_mov_b32_e32 v6, s4
; GPRIDX-NEXT: v_mov_b32_e32 v5, s3
; GPRIDX-NEXT: v_mov_b32_e32 v4, s2
; GPRIDX-NEXT: v_mov_b32_e32 v3, s1
; GPRIDX-NEXT: v_mov_b32_e32 v2, s0
; GPRIDX-NEXT: s_lshl_b32 s0, s12, 1
; GPRIDX-NEXT: s_set_gpr_idx_on s0, gpr_idx(DST)
; GPRIDX-NEXT: v_mov_b32_e32 v2, v0
; GPRIDX-NEXT: v_mov_b32_e32 v3, v1
; GPRIDX-NEXT: s_set_gpr_idx_off
; GPRIDX-NEXT: v_readfirstlane_b32 s0, v2 ; GPRIDX-NEXT: v_readfirstlane_b32 s0, v2
; GPRIDX-NEXT: v_readfirstlane_b32 s1, v3 ; GPRIDX-NEXT: v_cndmask_b32_e32 v2, v3, v1, vcc
; GPRIDX-NEXT: v_readfirstlane_b32 s2, v4 ; GPRIDX-NEXT: v_mov_b32_e32 v3, s4
; GPRIDX-NEXT: v_readfirstlane_b32 s3, v5 ; GPRIDX-NEXT: s_and_b32 s4, 1, s3
; GPRIDX-NEXT: v_readfirstlane_b32 s4, v6 ; GPRIDX-NEXT: v_cmp_ne_u32_e64 vcc, 0, s2
; GPRIDX-NEXT: v_readfirstlane_b32 s5, v7 ; GPRIDX-NEXT: s_cmp_eq_u32 s12, 3
; GPRIDX-NEXT: v_readfirstlane_b32 s6, v8 ; GPRIDX-NEXT: v_mov_b32_e32 v4, s5
; GPRIDX-NEXT: v_readfirstlane_b32 s7, v9 ; GPRIDX-NEXT: v_readfirstlane_b32 s1, v2
; GPRIDX-NEXT: v_readfirstlane_b32 s8, v10 ; GPRIDX-NEXT: v_cndmask_b32_e32 v2, v3, v0, vcc
; GPRIDX-NEXT: v_readfirstlane_b32 s9, v11 ; GPRIDX-NEXT: s_cselect_b32 s5, 1, 0
; GPRIDX-NEXT: v_readfirstlane_b32 s2, v2
; GPRIDX-NEXT: v_mov_b32_e32 v2, s6
; GPRIDX-NEXT: s_and_b32 s6, 1, s5
; GPRIDX-NEXT: s_cmp_eq_u32 s12, 4
; GPRIDX-NEXT: v_cndmask_b32_e32 v3, v4, v1, vcc
; GPRIDX-NEXT: v_mov_b32_e32 v5, s7
; GPRIDX-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4
; GPRIDX-NEXT: s_cselect_b32 s7, 1, 0
; GPRIDX-NEXT: v_cndmask_b32_e32 v4, v2, v0, vcc
; GPRIDX-NEXT: v_cndmask_b32_e32 v5, v5, v1, vcc
; GPRIDX-NEXT: v_readfirstlane_b32 s3, v3
; GPRIDX-NEXT: v_mov_b32_e32 v2, s8
; GPRIDX-NEXT: v_cmp_ne_u32_e64 vcc, 0, s6
; GPRIDX-NEXT: v_mov_b32_e32 v3, s9
; GPRIDX-NEXT: s_and_b32 s8, 1, s7
; GPRIDX-NEXT: v_cndmask_b32_e32 v6, v2, v0, vcc
; GPRIDX-NEXT: v_cndmask_b32_e32 v7, v3, v1, vcc
; GPRIDX-NEXT: v_mov_b32_e32 v2, s10
; GPRIDX-NEXT: v_cmp_ne_u32_e64 vcc, 0, s8
; GPRIDX-NEXT: v_mov_b32_e32 v3, s11
; GPRIDX-NEXT: v_cndmask_b32_e32 v8, v2, v0, vcc
; GPRIDX-NEXT: v_cndmask_b32_e32 v9, v3, v1, vcc
; GPRIDX-NEXT: v_readfirstlane_b32 s4, v4
; GPRIDX-NEXT: v_readfirstlane_b32 s5, v5
; GPRIDX-NEXT: v_readfirstlane_b32 s6, v6
; GPRIDX-NEXT: v_readfirstlane_b32 s7, v7
; GPRIDX-NEXT: v_readfirstlane_b32 s8, v8
; GPRIDX-NEXT: v_readfirstlane_b32 s9, v9
; GPRIDX-NEXT: ; return to shader part epilog ; GPRIDX-NEXT: ; return to shader part epilog
; ;
; MOVREL-LABEL: dyn_insertelement_v5f64_s_v_s: ; MOVREL-LABEL: dyn_insertelement_v5f64_s_v_s:
; MOVREL: ; %bb.0: ; %entry ; MOVREL: ; %bb.0: ; %entry
; MOVREL-NEXT: s_mov_b32 s0, s2 ; MOVREL-NEXT: s_cmp_eq_u32 s12, 0
; MOVREL-NEXT: s_mov_b32 s1, s3 ; MOVREL-NEXT: s_mov_b32 s14, s10
; MOVREL-NEXT: s_mov_b32 s2, s4 ; MOVREL-NEXT: s_mov_b32 s15, s11
; MOVREL-NEXT: s_mov_b32 s3, s5 ; MOVREL-NEXT: ; implicit-def: $vcc_hi
; MOVREL-NEXT: s_mov_b32 s4, s6 ; MOVREL-NEXT: s_cselect_b32 s0, 1, 0
; MOVREL-NEXT: s_mov_b32 s5, s7 ; MOVREL-NEXT: s_and_b32 s0, 1, s0
; MOVREL-NEXT: s_mov_b32 s6, s8 ; MOVREL-NEXT: s_cmp_eq_u32 s12, 1
; MOVREL-NEXT: s_mov_b32 s7, s9 ; MOVREL-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
; MOVREL-NEXT: s_mov_b32 s8, s10 ; MOVREL-NEXT: s_cselect_b32 s1, 1, 0
; MOVREL-NEXT: s_mov_b32 s9, s11 ; MOVREL-NEXT: v_cndmask_b32_e32 v2, s2, v0, vcc_lo
; MOVREL-NEXT: v_mov_b32_e32 v17, s15 ; MOVREL-NEXT: s_and_b32 s1, 1, s1
; MOVREL-NEXT: v_mov_b32_e32 v2, s0 ; MOVREL-NEXT: s_cmp_eq_u32 s12, 2
; MOVREL-NEXT: s_lshl_b32 m0, s12, 1 ; MOVREL-NEXT: v_cndmask_b32_e32 v3, s3, v1, vcc_lo
; MOVREL-NEXT: v_mov_b32_e32 v16, s14
; MOVREL-NEXT: v_mov_b32_e32 v15, s13
; MOVREL-NEXT: v_mov_b32_e32 v14, s12
; MOVREL-NEXT: v_mov_b32_e32 v13, s11
; MOVREL-NEXT: v_mov_b32_e32 v12, s10
; MOVREL-NEXT: v_mov_b32_e32 v11, s9
; MOVREL-NEXT: v_mov_b32_e32 v10, s8
; MOVREL-NEXT: v_mov_b32_e32 v9, s7
; MOVREL-NEXT: v_mov_b32_e32 v8, s6
; MOVREL-NEXT: v_mov_b32_e32 v7, s5
; MOVREL-NEXT: v_mov_b32_e32 v6, s4
; MOVREL-NEXT: v_mov_b32_e32 v5, s3
; MOVREL-NEXT: v_mov_b32_e32 v4, s2
; MOVREL-NEXT: v_mov_b32_e32 v3, s1
; MOVREL-NEXT: v_movreld_b32_e32 v2, v0
; MOVREL-NEXT: v_movreld_b32_e32 v3, v1
; MOVREL-NEXT: v_readfirstlane_b32 s0, v2 ; MOVREL-NEXT: v_readfirstlane_b32 s0, v2
; MOVREL-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s1
; MOVREL-NEXT: s_cselect_b32 s2, 1, 0
; MOVREL-NEXT: v_readfirstlane_b32 s1, v3 ; MOVREL-NEXT: v_readfirstlane_b32 s1, v3
; MOVREL-NEXT: v_readfirstlane_b32 s2, v4 ; MOVREL-NEXT: v_cndmask_b32_e32 v2, s4, v0, vcc_lo
; MOVREL-NEXT: v_readfirstlane_b32 s3, v5 ; MOVREL-NEXT: s_and_b32 s3, 1, s2
; MOVREL-NEXT: v_readfirstlane_b32 s4, v6 ; MOVREL-NEXT: s_cmp_eq_u32 s12, 3
; MOVREL-NEXT: v_readfirstlane_b32 s5, v7 ; MOVREL-NEXT: v_cndmask_b32_e32 v3, s5, v1, vcc_lo
; MOVREL-NEXT: v_readfirstlane_b32 s6, v8 ; MOVREL-NEXT: v_readfirstlane_b32 s2, v2
; MOVREL-NEXT: v_readfirstlane_b32 s7, v9 ; MOVREL-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s3
; MOVREL-NEXT: v_readfirstlane_b32 s8, v10 ; MOVREL-NEXT: s_cselect_b32 s4, 1, 0
; MOVREL-NEXT: v_readfirstlane_b32 s9, v11 ; MOVREL-NEXT: v_readfirstlane_b32 s3, v3
; MOVREL-NEXT: ; implicit-def: $vcc_hi ; MOVREL-NEXT: v_cndmask_b32_e32 v4, s6, v0, vcc_lo
; MOVREL-NEXT: s_and_b32 s5, 1, s4
; MOVREL-NEXT: s_cmp_eq_u32 s12, 4
; MOVREL-NEXT: v_cndmask_b32_e32 v5, s7, v1, vcc_lo
; MOVREL-NEXT: v_readfirstlane_b32 s4, v4
; MOVREL-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s5
; MOVREL-NEXT: s_cselect_b32 s6, 1, 0
; MOVREL-NEXT: v_readfirstlane_b32 s5, v5
; MOVREL-NEXT: v_cndmask_b32_e32 v7, s9, v1, vcc_lo
; MOVREL-NEXT: s_and_b32 s6, 1, s6
; MOVREL-NEXT: v_cndmask_b32_e32 v6, s8, v0, vcc_lo
; MOVREL-NEXT: v_readfirstlane_b32 s7, v7
; MOVREL-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s6
; MOVREL-NEXT: v_readfirstlane_b32 s6, v6
; MOVREL-NEXT: v_cndmask_b32_e32 v8, s14, v0, vcc_lo
; MOVREL-NEXT: v_cndmask_b32_e32 v9, s15, v1, vcc_lo
; MOVREL-NEXT: v_readfirstlane_b32 s8, v8
; MOVREL-NEXT: v_readfirstlane_b32 s9, v9
; MOVREL-NEXT: ; return to shader part epilog ; MOVREL-NEXT: ; return to shader part epilog
entry: entry:
%insert = insertelement <5 x double> %vec, double %val, i32 %idx %insert = insertelement <5 x double> %vec, double %val, i32 %idx
ret <5 x double> %insert ret <5 x double> %insert
} }
define amdgpu_ps <5 x double> @dyn_insertelement_v5f64_s_v_v(<5 x double> inreg %vec, double %val, i32 %idx) { define amdgpu_ps <5 x double> @dyn_insertelement_v5f64_s_v_v(<5 x double> inreg %vec, double %val, i32 %idx) {
; GPRIDX-LABEL: dyn_insertelement_v5f64_s_v_v: ; GPRIDX-LABEL: dyn_insertelement_v5f64_s_v_v:
; GPRIDX: ; %bb.0: ; %entry ; GPRIDX: ; %bb.0: ; %entry
; GPRIDX-NEXT: s_mov_b32 s0, s2 ; GPRIDX-NEXT: v_mov_b32_e32 v3, s2
; GPRIDX-NEXT: s_mov_b32 s1, s3 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GPRIDX-NEXT: s_mov_b32 s2, s4 ; GPRIDX-NEXT: v_cndmask_b32_e32 v3, v3, v0, vcc
; GPRIDX-NEXT: s_mov_b32 s3, s5 ; GPRIDX-NEXT: v_mov_b32_e32 v4, s3
; GPRIDX-NEXT: s_mov_b32 s4, s6
; GPRIDX-NEXT: s_mov_b32 s5, s7
; GPRIDX-NEXT: s_mov_b32 s6, s8
; GPRIDX-NEXT: s_mov_b32 s7, s9
; GPRIDX-NEXT: s_mov_b32 s8, s10
; GPRIDX-NEXT: s_mov_b32 s9, s11
; GPRIDX-NEXT: v_mov_b32_e32 v34, s15
; GPRIDX-NEXT: v_mov_b32_e32 v33, s14
; GPRIDX-NEXT: v_mov_b32_e32 v32, s13
; GPRIDX-NEXT: v_mov_b32_e32 v31, s12
; GPRIDX-NEXT: v_mov_b32_e32 v30, s11
; GPRIDX-NEXT: v_mov_b32_e32 v29, s10
; GPRIDX-NEXT: v_mov_b32_e32 v28, s9
; GPRIDX-NEXT: v_mov_b32_e32 v27, s8
; GPRIDX-NEXT: v_mov_b32_e32 v26, s7
; GPRIDX-NEXT: v_mov_b32_e32 v25, s6
; GPRIDX-NEXT: v_mov_b32_e32 v24, s5
; GPRIDX-NEXT: v_mov_b32_e32 v23, s4
; GPRIDX-NEXT: v_mov_b32_e32 v22, s3
; GPRIDX-NEXT: v_mov_b32_e32 v21, s2
; GPRIDX-NEXT: v_mov_b32_e32 v20, s1
; GPRIDX-NEXT: v_mov_b32_e32 v19, s0
; GPRIDX-NEXT: s_mov_b64 s[0:1], exec
; GPRIDX-NEXT: BB56_1: ; =>This Inner Loop Header: Depth=1
; GPRIDX-NEXT: v_readfirstlane_b32 s2, v2
; GPRIDX-NEXT: s_lshl_b32 s3, s2, 1
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, s2, v2
; GPRIDX-NEXT: s_set_gpr_idx_on s3, gpr_idx(DST)
; GPRIDX-NEXT: v_mov_b32_e32 v3, v19
; GPRIDX-NEXT: v_mov_b32_e32 v4, v20
; GPRIDX-NEXT: v_mov_b32_e32 v5, v21
; GPRIDX-NEXT: v_mov_b32_e32 v6, v22
; GPRIDX-NEXT: v_mov_b32_e32 v7, v23
; GPRIDX-NEXT: v_mov_b32_e32 v8, v24
; GPRIDX-NEXT: v_mov_b32_e32 v9, v25
; GPRIDX-NEXT: v_mov_b32_e32 v10, v26
; GPRIDX-NEXT: v_mov_b32_e32 v11, v27
; GPRIDX-NEXT: v_mov_b32_e32 v12, v28
; GPRIDX-NEXT: v_mov_b32_e32 v13, v29
; GPRIDX-NEXT: v_mov_b32_e32 v14, v30
; GPRIDX-NEXT: v_mov_b32_e32 v15, v31
; GPRIDX-NEXT: v_mov_b32_e32 v16, v32
; GPRIDX-NEXT: v_mov_b32_e32 v17, v33
; GPRIDX-NEXT: v_mov_b32_e32 v18, v34
; GPRIDX-NEXT: v_mov_b32_e32 v3, v0
; GPRIDX-NEXT: s_set_gpr_idx_off
; GPRIDX-NEXT: s_set_gpr_idx_on s3, gpr_idx(DST)
; GPRIDX-NEXT: v_mov_b32_e32 v4, v1
; GPRIDX-NEXT: s_set_gpr_idx_off
; GPRIDX-NEXT: s_and_saveexec_b64 vcc, vcc
; GPRIDX-NEXT: s_xor_b64 exec, exec, vcc
; GPRIDX-NEXT: s_cbranch_execnz BB56_1
; GPRIDX-NEXT: ; %bb.2:
; GPRIDX-NEXT: s_mov_b64 exec, s[0:1]
; GPRIDX-NEXT: v_readfirstlane_b32 s0, v3 ; GPRIDX-NEXT: v_readfirstlane_b32 s0, v3
; GPRIDX-NEXT: v_readfirstlane_b32 s1, v4 ; GPRIDX-NEXT: v_cndmask_b32_e32 v3, v4, v1, vcc
; GPRIDX-NEXT: v_readfirstlane_b32 s2, v5 ; GPRIDX-NEXT: v_mov_b32_e32 v4, s4
; GPRIDX-NEXT: v_readfirstlane_b32 s3, v6 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
; GPRIDX-NEXT: v_readfirstlane_b32 s4, v7 ; GPRIDX-NEXT: v_readfirstlane_b32 s1, v3
; GPRIDX-NEXT: v_readfirstlane_b32 s5, v8 ; GPRIDX-NEXT: v_cndmask_b32_e32 v3, v4, v0, vcc
; GPRIDX-NEXT: v_readfirstlane_b32 s6, v9 ; GPRIDX-NEXT: v_mov_b32_e32 v5, s5
; GPRIDX-NEXT: v_readfirstlane_b32 s7, v10 ; GPRIDX-NEXT: v_readfirstlane_b32 s2, v3
; GPRIDX-NEXT: v_readfirstlane_b32 s8, v11 ; GPRIDX-NEXT: v_cndmask_b32_e32 v3, v5, v1, vcc
; GPRIDX-NEXT: v_readfirstlane_b32 s9, v12 ; GPRIDX-NEXT: v_mov_b32_e32 v4, s6
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 2, v2
; GPRIDX-NEXT: v_readfirstlane_b32 s3, v3
; GPRIDX-NEXT: v_mov_b32_e32 v3, s7
; GPRIDX-NEXT: v_cndmask_b32_e32 v4, v4, v0, vcc
; GPRIDX-NEXT: v_cndmask_b32_e32 v5, v3, v1, vcc
; GPRIDX-NEXT: v_readfirstlane_b32 s4, v4
; GPRIDX-NEXT: v_mov_b32_e32 v3, s8
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 3, v2
; GPRIDX-NEXT: v_mov_b32_e32 v4, s9
; GPRIDX-NEXT: v_cndmask_b32_e32 v6, v3, v0, vcc
; GPRIDX-NEXT: v_cndmask_b32_e32 v7, v4, v1, vcc
; GPRIDX-NEXT: v_mov_b32_e32 v3, s10
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 4, v2
; GPRIDX-NEXT: v_mov_b32_e32 v4, s11
; GPRIDX-NEXT: v_cndmask_b32_e32 v8, v3, v0, vcc
; GPRIDX-NEXT: v_cndmask_b32_e32 v9, v4, v1, vcc
; GPRIDX-NEXT: v_readfirstlane_b32 s5, v5
; GPRIDX-NEXT: v_readfirstlane_b32 s6, v6
; GPRIDX-NEXT: v_readfirstlane_b32 s7, v7
; GPRIDX-NEXT: v_readfirstlane_b32 s8, v8
; GPRIDX-NEXT: v_readfirstlane_b32 s9, v9
; GPRIDX-NEXT: ; return to shader part epilog ; GPRIDX-NEXT: ; return to shader part epilog
; ;
; MOVREL-LABEL: dyn_insertelement_v5f64_s_v_v: ; MOVREL-LABEL: dyn_insertelement_v5f64_s_v_v:
; MOVREL: ; %bb.0: ; %entry ; MOVREL: ; %bb.0: ; %entry
; MOVREL-NEXT: s_mov_b32 s0, s2 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
; MOVREL-NEXT: s_mov_b32 s1, s3 ; MOVREL-NEXT: s_mov_b32 s14, s10
; MOVREL-NEXT: s_mov_b32 s2, s4 ; MOVREL-NEXT: s_mov_b32 s15, s11
; MOVREL-NEXT: s_mov_b32 s3, s5 ; MOVREL-NEXT: ; implicit-def: $vcc_hi
; MOVREL-NEXT: s_mov_b32 s4, s6 ; MOVREL-NEXT: v_cndmask_b32_e32 v3, s2, v0, vcc_lo
; MOVREL-NEXT: s_mov_b32 s5, s7 ; MOVREL-NEXT: v_cndmask_b32_e32 v4, s3, v1, vcc_lo
; MOVREL-NEXT: s_mov_b32 s6, s8 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
; MOVREL-NEXT: s_mov_b32 s7, s9
; MOVREL-NEXT: s_mov_b32 s8, s10
; MOVREL-NEXT: s_mov_b32 s9, s11
; MOVREL-NEXT: v_mov_b32_e32 v34, s15
; MOVREL-NEXT: v_mov_b32_e32 v33, s14
; MOVREL-NEXT: v_mov_b32_e32 v32, s13
; MOVREL-NEXT: v_mov_b32_e32 v31, s12
; MOVREL-NEXT: v_mov_b32_e32 v30, s11
; MOVREL-NEXT: v_mov_b32_e32 v29, s10
; MOVREL-NEXT: v_mov_b32_e32 v28, s9
; MOVREL-NEXT: v_mov_b32_e32 v27, s8
; MOVREL-NEXT: v_mov_b32_e32 v26, s7
; MOVREL-NEXT: v_mov_b32_e32 v25, s6
; MOVREL-NEXT: v_mov_b32_e32 v24, s5
; MOVREL-NEXT: v_mov_b32_e32 v23, s4
; MOVREL-NEXT: v_mov_b32_e32 v22, s3
; MOVREL-NEXT: v_mov_b32_e32 v21, s2
; MOVREL-NEXT: v_mov_b32_e32 v20, s1
; MOVREL-NEXT: v_mov_b32_e32 v19, s0
; MOVREL-NEXT: s_mov_b32 s0, exec_lo
; MOVREL-NEXT: ; implicit-def: $vcc_hi
; MOVREL-NEXT: BB56_1: ; =>This Inner Loop Header: Depth=1
; MOVREL-NEXT: v_readfirstlane_b32 s1, v2
; MOVREL-NEXT: v_mov_b32_e32 v3, v19
; MOVREL-NEXT: v_mov_b32_e32 v4, v20
; MOVREL-NEXT: v_mov_b32_e32 v5, v21
; MOVREL-NEXT: v_mov_b32_e32 v6, v22
; MOVREL-NEXT: s_lshl_b32 m0, s1, 1
; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, s1, v2
; MOVREL-NEXT: v_mov_b32_e32 v7, v23
; MOVREL-NEXT: v_mov_b32_e32 v8, v24
; MOVREL-NEXT: v_mov_b32_e32 v9, v25
; MOVREL-NEXT: v_mov_b32_e32 v10, v26
; MOVREL-NEXT: v_mov_b32_e32 v11, v27
; MOVREL-NEXT: v_mov_b32_e32 v12, v28
; MOVREL-NEXT: v_mov_b32_e32 v13, v29
; MOVREL-NEXT: v_mov_b32_e32 v14, v30
; MOVREL-NEXT: v_mov_b32_e32 v15, v31
; MOVREL-NEXT: v_mov_b32_e32 v16, v32
; MOVREL-NEXT: v_mov_b32_e32 v17, v33
; MOVREL-NEXT: v_mov_b32_e32 v18, v34
; MOVREL-NEXT: v_movreld_b32_e32 v3, v0
; MOVREL-NEXT: v_movreld_b32_e32 v4, v1
; MOVREL-NEXT: s_and_saveexec_b32 vcc_lo, vcc_lo
; MOVREL-NEXT: s_xor_b32 exec_lo, exec_lo, vcc_lo
; MOVREL-NEXT: s_cbranch_execnz BB56_1
; MOVREL-NEXT: ; %bb.2:
; MOVREL-NEXT: s_mov_b32 exec_lo, s0
; MOVREL-NEXT: v_readfirstlane_b32 s0, v3 ; MOVREL-NEXT: v_readfirstlane_b32 s0, v3
; MOVREL-NEXT: v_readfirstlane_b32 s1, v4 ; MOVREL-NEXT: v_readfirstlane_b32 s1, v4
; MOVREL-NEXT: v_readfirstlane_b32 s2, v5 ; MOVREL-NEXT: v_cndmask_b32_e32 v3, s4, v0, vcc_lo
; MOVREL-NEXT: v_readfirstlane_b32 s3, v6 ; MOVREL-NEXT: v_cndmask_b32_e32 v4, s5, v1, vcc_lo
; MOVREL-NEXT: v_readfirstlane_b32 s4, v7 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v2
; MOVREL-NEXT: v_readfirstlane_b32 s5, v8 ; MOVREL-NEXT: v_readfirstlane_b32 s2, v3
; MOVREL-NEXT: v_readfirstlane_b32 s6, v9 ; MOVREL-NEXT: v_readfirstlane_b32 s3, v4
; MOVREL-NEXT: v_readfirstlane_b32 s7, v10 ; MOVREL-NEXT: v_cndmask_b32_e32 v5, s6, v0, vcc_lo
; MOVREL-NEXT: v_readfirstlane_b32 s8, v11 ; MOVREL-NEXT: v_cndmask_b32_e32 v6, s7, v1, vcc_lo
; MOVREL-NEXT: v_readfirstlane_b32 s9, v12 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v2
; MOVREL-NEXT: v_readfirstlane_b32 s4, v5
; MOVREL-NEXT: v_readfirstlane_b32 s5, v6
; MOVREL-NEXT: v_cndmask_b32_e32 v7, s8, v0, vcc_lo
; MOVREL-NEXT: v_cndmask_b32_e32 v8, s9, v1, vcc_lo
; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v2
; MOVREL-NEXT: v_readfirstlane_b32 s6, v7
; MOVREL-NEXT: v_readfirstlane_b32 s7, v8
; MOVREL-NEXT: v_cndmask_b32_e32 v9, s14, v0, vcc_lo
; MOVREL-NEXT: v_cndmask_b32_e32 v10, s15, v1, vcc_lo
; MOVREL-NEXT: v_readfirstlane_b32 s8, v9
; MOVREL-NEXT: v_readfirstlane_b32 s9, v10
; MOVREL-NEXT: ; return to shader part epilog ; MOVREL-NEXT: ; return to shader part epilog
entry: entry:
%insert = insertelement <5 x double> %vec, double %val, i32 %idx %insert = insertelement <5 x double> %vec, double %val, i32 %idx
ret <5 x double> %insert ret <5 x double> %insert
} }
define amdgpu_ps <5 x double> @dyn_insertelement_v5f64_v_v_s(<5 x double> %vec, double %val, i32 inreg %idx) { define amdgpu_ps <5 x double> @dyn_insertelement_v5f64_v_v_s(<5 x double> %vec, double %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v5f64_v_v_s: ; GPRIDX-LABEL: dyn_insertelement_v5f64_v_v_s:
; GPRIDX: ; %bb.0: ; %entry ; GPRIDX: ; %bb.0: ; %entry
; GPRIDX-NEXT: s_lshl_b32 s0, s2, 1 ; GPRIDX-NEXT: s_cmp_eq_u32 s2, 0
; GPRIDX-NEXT: v_mov_b32_e32 v16, v11 ; GPRIDX-NEXT: s_cselect_b32 s0, 1, 0
; GPRIDX-NEXT: s_set_gpr_idx_on s0, gpr_idx(DST) ; GPRIDX-NEXT: s_and_b32 s0, 1, s0
; GPRIDX-NEXT: v_mov_b32_e32 v0, v10 ; GPRIDX-NEXT: s_cmp_eq_u32 s2, 1
; GPRIDX-NEXT: v_mov_b32_e32 v1, v16 ; GPRIDX-NEXT: s_cselect_b32 s3, 1, 0
; GPRIDX-NEXT: s_set_gpr_idx_off ; GPRIDX-NEXT: s_and_b32 s3, 1, s3
; GPRIDX-NEXT: s_cmp_eq_u32 s2, 2
; GPRIDX-NEXT: s_cselect_b32 s4, 1, 0
; GPRIDX-NEXT: s_and_b32 s4, 1, s4
; GPRIDX-NEXT: s_cmp_eq_u32 s2, 3
; GPRIDX-NEXT: s_cselect_b32 s6, 1, 0
; GPRIDX-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GPRIDX-NEXT: s_and_b32 s6, 1, s6
; GPRIDX-NEXT: s_cmp_eq_u32 s2, 4
; GPRIDX-NEXT: v_cndmask_b32_e32 v0, v0, v10, vcc
; GPRIDX-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc
; GPRIDX-NEXT: v_cmp_ne_u32_e64 vcc, 0, s3
; GPRIDX-NEXT: s_cselect_b32 s2, 1, 0
; GPRIDX-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc
; GPRIDX-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc
; GPRIDX-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4
; GPRIDX-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc
; GPRIDX-NEXT: v_cndmask_b32_e32 v5, v5, v11, vcc
; GPRIDX-NEXT: v_cmp_ne_u32_e64 vcc, 0, s6
; GPRIDX-NEXT: s_and_b32 s2, 1, s2
; GPRIDX-NEXT: v_cndmask_b32_e32 v6, v6, v10, vcc
; GPRIDX-NEXT: v_cndmask_b32_e32 v7, v7, v11, vcc
; GPRIDX-NEXT: v_cmp_ne_u32_e64 vcc, 0, s2
; GPRIDX-NEXT: v_readfirstlane_b32 s10, v2
; GPRIDX-NEXT: v_cndmask_b32_e32 v8, v8, v10, vcc
; GPRIDX-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc
; GPRIDX-NEXT: v_readfirstlane_b32 s0, v0 ; GPRIDX-NEXT: v_readfirstlane_b32 s0, v0
; GPRIDX-NEXT: v_readfirstlane_b32 s1, v1 ; GPRIDX-NEXT: v_readfirstlane_b32 s1, v1
; GPRIDX-NEXT: v_readfirstlane_b32 s2, v2
; GPRIDX-NEXT: v_readfirstlane_b32 s3, v3 ; GPRIDX-NEXT: v_readfirstlane_b32 s3, v3
; GPRIDX-NEXT: v_readfirstlane_b32 s4, v4 ; GPRIDX-NEXT: v_readfirstlane_b32 s4, v4
; GPRIDX-NEXT: v_readfirstlane_b32 s5, v5 ; GPRIDX-NEXT: v_readfirstlane_b32 s5, v5
; GPRIDX-NEXT: v_readfirstlane_b32 s6, v6 ; GPRIDX-NEXT: v_readfirstlane_b32 s6, v6
; GPRIDX-NEXT: v_readfirstlane_b32 s7, v7 ; GPRIDX-NEXT: v_readfirstlane_b32 s7, v7
; GPRIDX-NEXT: v_readfirstlane_b32 s8, v8 ; GPRIDX-NEXT: v_readfirstlane_b32 s8, v8
; GPRIDX-NEXT: v_readfirstlane_b32 s9, v9 ; GPRIDX-NEXT: v_readfirstlane_b32 s9, v9
; GPRIDX-NEXT: s_mov_b32 s2, s10
; GPRIDX-NEXT: ; return to shader part epilog ; GPRIDX-NEXT: ; return to shader part epilog
; ;
; MOVREL-LABEL: dyn_insertelement_v5f64_v_v_s: ; MOVREL-LABEL: dyn_insertelement_v5f64_v_v_s:
; MOVREL: ; %bb.0: ; %entry ; MOVREL: ; %bb.0: ; %entry
; MOVREL-NEXT: s_lshl_b32 m0, s2, 1 ; MOVREL-NEXT: s_cmp_eq_u32 s2, 0
; MOVREL-NEXT: v_mov_b32_e32 v16, v11 ; MOVREL-NEXT: v_mov_b32_e32 v15, v2
; MOVREL-NEXT: v_mov_b32_e32 v12, v3
; MOVREL-NEXT: v_mov_b32_e32 v19, v6
; MOVREL-NEXT: v_mov_b32_e32 v16, v7
; MOVREL-NEXT: s_cselect_b32 s0, 1, 0
; MOVREL-NEXT: ; implicit-def: $vcc_hi ; MOVREL-NEXT: ; implicit-def: $vcc_hi
; MOVREL-NEXT: v_movreld_b32_e32 v0, v10 ; MOVREL-NEXT: s_and_b32 s0, 1, s0
; MOVREL-NEXT: v_movreld_b32_e32 v1, v16 ; MOVREL-NEXT: s_cmp_eq_u32 s2, 1
; MOVREL-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
; MOVREL-NEXT: s_cselect_b32 s1, 1, 0
; MOVREL-NEXT: v_cndmask_b32_e32 v0, v0, v10, vcc_lo
; MOVREL-NEXT: s_and_b32 s3, 1, s1
; MOVREL-NEXT: s_cmp_eq_u32 s2, 2
; MOVREL-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc_lo
; MOVREL-NEXT: v_readfirstlane_b32 s0, v0 ; MOVREL-NEXT: v_readfirstlane_b32 s0, v0
; MOVREL-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s3
; MOVREL-NEXT: s_cselect_b32 s4, 1, 0
; MOVREL-NEXT: v_readfirstlane_b32 s1, v1 ; MOVREL-NEXT: v_readfirstlane_b32 s1, v1
; MOVREL-NEXT: v_readfirstlane_b32 s2, v2 ; MOVREL-NEXT: v_cndmask_b32_e32 v2, v15, v10, vcc_lo
; MOVREL-NEXT: s_and_b32 s3, 1, s4
; MOVREL-NEXT: s_cmp_eq_u32 s2, 3
; MOVREL-NEXT: v_cndmask_b32_e32 v3, v12, v11, vcc_lo
; MOVREL-NEXT: v_readfirstlane_b32 s10, v2
; MOVREL-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s3
; MOVREL-NEXT: s_cselect_b32 s4, 1, 0
; MOVREL-NEXT: v_readfirstlane_b32 s3, v3 ; MOVREL-NEXT: v_readfirstlane_b32 s3, v3
; MOVREL-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc_lo
; MOVREL-NEXT: s_and_b32 s5, 1, s4
; MOVREL-NEXT: s_cmp_eq_u32 s2, 4
; MOVREL-NEXT: v_cndmask_b32_e32 v5, v5, v11, vcc_lo
; MOVREL-NEXT: v_readfirstlane_b32 s4, v4 ; MOVREL-NEXT: v_readfirstlane_b32 s4, v4
; MOVREL-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s5
; MOVREL-NEXT: s_cselect_b32 s2, 1, 0
; MOVREL-NEXT: v_readfirstlane_b32 s5, v5 ; MOVREL-NEXT: v_readfirstlane_b32 s5, v5
; MOVREL-NEXT: v_cndmask_b32_e32 v6, v19, v10, vcc_lo
; MOVREL-NEXT: s_and_b32 s2, 1, s2
; MOVREL-NEXT: v_cndmask_b32_e32 v7, v16, v11, vcc_lo
; MOVREL-NEXT: v_readfirstlane_b32 s6, v6 ; MOVREL-NEXT: v_readfirstlane_b32 s6, v6
; MOVREL-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s2
; MOVREL-NEXT: v_readfirstlane_b32 s7, v7 ; MOVREL-NEXT: v_readfirstlane_b32 s7, v7
; MOVREL-NEXT: s_mov_b32 s2, s10
; MOVREL-NEXT: v_cndmask_b32_e32 v8, v8, v10, vcc_lo
; MOVREL-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc_lo
; MOVREL-NEXT: v_readfirstlane_b32 s8, v8 ; MOVREL-NEXT: v_readfirstlane_b32 s8, v8
; MOVREL-NEXT: v_readfirstlane_b32 s9, v9 ; MOVREL-NEXT: v_readfirstlane_b32 s9, v9
; MOVREL-NEXT: ; return to shader part epilog ; MOVREL-NEXT: ; return to shader part epilog
entry: entry:
%insert = insertelement <5 x double> %vec, double %val, i32 %idx %insert = insertelement <5 x double> %vec, double %val, i32 %idx
ret <5 x double> %insert ret <5 x double> %insert
} }
define amdgpu_ps <5 x double> @dyn_insertelement_v5f64_v_v_v(<5 x double> %vec, double %val, i32 %idx) { define amdgpu_ps <5 x double> @dyn_insertelement_v5f64_v_v_v(<5 x double> %vec, double %val, i32 %idx) {
; GPRIDX-LABEL: dyn_insertelement_v5f64_v_v_v: ; GPRIDX-LABEL: dyn_insertelement_v5f64_v_v_v:
; GPRIDX: ; %bb.0: ; %entry ; GPRIDX: ; %bb.0: ; %entry
; GPRIDX-NEXT: s_mov_b64 s[0:1], exec ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 0, v12
; GPRIDX-NEXT: BB58_1: ; =>This Inner Loop Header: Depth=1 ; GPRIDX-NEXT: v_cndmask_b32_e32 v0, v0, v10, vcc
; GPRIDX-NEXT: v_readfirstlane_b32 s2, v12 ; GPRIDX-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc
; GPRIDX-NEXT: s_lshl_b32 s3, s2, 1 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 1, v12
; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, s2, v12 ; GPRIDX-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc
; GPRIDX-NEXT: s_set_gpr_idx_on s3, gpr_idx(DST) ; GPRIDX-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc
; GPRIDX-NEXT: v_mov_b32_e32 v28, v15 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 2, v12
; GPRIDX-NEXT: v_mov_b32_e32 v27, v14 ; GPRIDX-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc
; GPRIDX-NEXT: v_mov_b32_e32 v26, v13 ; GPRIDX-NEXT: v_cndmask_b32_e32 v5, v5, v11, vcc
; GPRIDX-NEXT: v_mov_b32_e32 v25, v12 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 3, v12
; GPRIDX-NEXT: v_mov_b32_e32 v24, v11 ; GPRIDX-NEXT: v_cndmask_b32_e32 v6, v6, v10, vcc
; GPRIDX-NEXT: v_mov_b32_e32 v23, v10 ; GPRIDX-NEXT: v_cndmask_b32_e32 v7, v7, v11, vcc
; GPRIDX-NEXT: v_mov_b32_e32 v22, v9 ; GPRIDX-NEXT: v_cmp_eq_u32_e32 vcc, 4, v12
; GPRIDX-NEXT: v_mov_b32_e32 v21, v8 ; GPRIDX-NEXT: v_cndmask_b32_e32 v8, v8, v10, vcc
; GPRIDX-NEXT: v_mov_b32_e32 v20, v7 ; GPRIDX-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc
; GPRIDX-NEXT: v_mov_b32_e32 v19, v6 ; GPRIDX-NEXT: v_readfirstlane_b32 s0, v0
; GPRIDX-NEXT: v_mov_b32_e32 v18, v5 ; GPRIDX-NEXT: v_readfirstlane_b32 s1, v1
; GPRIDX-NEXT: v_mov_b32_e32 v17, v4 ; GPRIDX-NEXT: v_readfirstlane_b32 s2, v2
; GPRIDX-NEXT: v_mov_b32_e32 v16, v3 ; GPRIDX-NEXT: v_readfirstlane_b32 s3, v3
; GPRIDX-NEXT: v_mov_b32_e32 v15, v2 ; GPRIDX-NEXT: v_readfirstlane_b32 s4, v4
; GPRIDX-NEXT: v_mov_b32_e32 v14, v1 ; GPRIDX-NEXT: v_readfirstlane_b32 s5, v5
; GPRIDX-NEXT: v_mov_b32_e32 v13, v0 ; GPRIDX-NEXT: v_readfirstlane_b32 s6, v6
; GPRIDX-NEXT: v_mov_b32_e32 v13, v10 ; GPRIDX-NEXT: v_readfirstlane_b32 s7, v7
; GPRIDX-NEXT: s_set_gpr_idx_off ; GPRIDX-NEXT: v_readfirstlane_b32 s8, v8
; GPRIDX-NEXT: s_set_gpr_idx_on s3, gpr_idx(DST) ; GPRIDX-NEXT: v_readfirstlane_b32 s9, v9
; GPRIDX-NEXT: v_mov_b32_e32 v14, v11
; GPRIDX-NEXT: s_set_gpr_idx_off
; GPRIDX-NEXT: s_and_saveexec_b64 vcc, vcc
; GPRIDX-NEXT: s_xor_b64 exec, exec, vcc
; GPRIDX-NEXT: s_cbranch_execnz BB58_1
; GPRIDX-NEXT: ; %bb.2:
; GPRIDX-NEXT: s_mov_b64 exec, s[0:1]
; GPRIDX-NEXT: v_readfirstlane_b32 s0, v13
; GPRIDX-NEXT: v_readfirstlane_b32 s1, v14
; GPRIDX-NEXT: v_readfirstlane_b32 s2, v15
; GPRIDX-NEXT: v_readfirstlane_b32 s3, v16
; GPRIDX-NEXT: v_readfirstlane_b32 s4, v17
; GPRIDX-NEXT: v_readfirstlane_b32 s5, v18
; GPRIDX-NEXT: v_readfirstlane_b32 s6, v19
; GPRIDX-NEXT: v_readfirstlane_b32 s7, v20
; GPRIDX-NEXT: v_readfirstlane_b32 s8, v21
; GPRIDX-NEXT: v_readfirstlane_b32 s9, v22
; GPRIDX-NEXT: ; return to shader part epilog ; GPRIDX-NEXT: ; return to shader part epilog
; ;
; MOVREL-LABEL: dyn_insertelement_v5f64_v_v_v: ; MOVREL-LABEL: dyn_insertelement_v5f64_v_v_v:
; MOVREL: ; %bb.0: ; %entry ; MOVREL: ; %bb.0: ; %entry
; MOVREL-NEXT: s_mov_b32 s0, exec_lo ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v12
; MOVREL-NEXT: ; implicit-def: $vcc_hi
; MOVREL-NEXT: BB58_1: ; =>This Inner Loop Header: Depth=1
; MOVREL-NEXT: v_readfirstlane_b32 s1, v12
; MOVREL-NEXT: v_mov_b32_e32 v28, v15
; MOVREL-NEXT: v_mov_b32_e32 v27, v14
; MOVREL-NEXT: v_mov_b32_e32 v26, v13
; MOVREL-NEXT: v_mov_b32_e32 v25, v12
; MOVREL-NEXT: v_mov_b32_e32 v24, v11
; MOVREL-NEXT: v_mov_b32_e32 v23, v10
; MOVREL-NEXT: v_mov_b32_e32 v22, v9
; MOVREL-NEXT: v_mov_b32_e32 v21, v8
; MOVREL-NEXT: v_mov_b32_e32 v20, v7
; MOVREL-NEXT: v_mov_b32_e32 v19, v6
; MOVREL-NEXT: v_mov_b32_e32 v18, v5
; MOVREL-NEXT: v_mov_b32_e32 v17, v4
; MOVREL-NEXT: v_mov_b32_e32 v16, v3
; MOVREL-NEXT: v_mov_b32_e32 v15, v2 ; MOVREL-NEXT: v_mov_b32_e32 v15, v2
; MOVREL-NEXT: v_mov_b32_e32 v14, v1 ; MOVREL-NEXT: v_mov_b32_e32 v16, v3
; MOVREL-NEXT: v_mov_b32_e32 v13, v0 ; MOVREL-NEXT: v_mov_b32_e32 v19, v6
; MOVREL-NEXT: s_lshl_b32 m0, s1, 1 ; MOVREL-NEXT: v_mov_b32_e32 v20, v7
; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, s1, v12 ; MOVREL-NEXT: v_cndmask_b32_e32 v0, v0, v10, vcc_lo
; MOVREL-NEXT: v_movreld_b32_e32 v13, v10 ; MOVREL-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc_lo
; MOVREL-NEXT: v_movreld_b32_e32 v14, v11 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v12
; MOVREL-NEXT: s_and_saveexec_b32 vcc_lo, vcc_lo ; MOVREL-NEXT: ; implicit-def: $vcc_hi
; MOVREL-NEXT: s_xor_b32 exec_lo, exec_lo, vcc_lo ; MOVREL-NEXT: v_readfirstlane_b32 s0, v0
; MOVREL-NEXT: s_cbranch_execnz BB58_1 ; MOVREL-NEXT: v_readfirstlane_b32 s1, v1
; MOVREL-NEXT: ; %bb.2: ; MOVREL-NEXT: v_cndmask_b32_e32 v2, v15, v10, vcc_lo
; MOVREL-NEXT: s_mov_b32 exec_lo, s0 ; MOVREL-NEXT: v_cndmask_b32_e32 v3, v16, v11, vcc_lo
; MOVREL-NEXT: v_readfirstlane_b32 s0, v13 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v12
; MOVREL-NEXT: v_readfirstlane_b32 s1, v14 ; MOVREL-NEXT: v_readfirstlane_b32 s2, v2
; MOVREL-NEXT: v_readfirstlane_b32 s2, v15 ; MOVREL-NEXT: v_readfirstlane_b32 s3, v3
; MOVREL-NEXT: v_readfirstlane_b32 s3, v16 ; MOVREL-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc_lo
; MOVREL-NEXT: v_readfirstlane_b32 s4, v17 ; MOVREL-NEXT: v_cndmask_b32_e32 v5, v5, v11, vcc_lo
; MOVREL-NEXT: v_readfirstlane_b32 s5, v18 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v12
; MOVREL-NEXT: v_readfirstlane_b32 s6, v19 ; MOVREL-NEXT: v_readfirstlane_b32 s4, v4
; MOVREL-NEXT: v_readfirstlane_b32 s7, v20 ; MOVREL-NEXT: v_readfirstlane_b32 s5, v5
; MOVREL-NEXT: v_readfirstlane_b32 s8, v21 ; MOVREL-NEXT: v_cndmask_b32_e32 v6, v19, v10, vcc_lo
; MOVREL-NEXT: v_readfirstlane_b32 s9, v22 ; MOVREL-NEXT: v_cndmask_b32_e32 v7, v20, v11, vcc_lo
; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v12
; MOVREL-NEXT: v_readfirstlane_b32 s6, v6
; MOVREL-NEXT: v_readfirstlane_b32 s7, v7
; MOVREL-NEXT: v_cndmask_b32_e32 v8, v8, v10, vcc_lo
; MOVREL-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc_lo
; MOVREL-NEXT: v_readfirstlane_b32 s8, v8
; MOVREL-NEXT: v_readfirstlane_b32 s9, v9
; MOVREL-NEXT: ; return to shader part epilog ; MOVREL-NEXT: ; return to shader part epilog
entry: entry:
%insert = insertelement <5 x double> %vec, double %val, i32 %idx %insert = insertelement <5 x double> %vec, double %val, i32 %idx
ret <5 x double> %insert ret <5 x double> %insert
} }