[PowerPC] Convert vec_splats functions to macros

[vddvss]

Summary

This commit converts the vec_splats functions in altivec.h to macros, solving an issue where vec_splats calls could not assign to variables of static storage duration, such as:

static vector int x = vec_splats(1);

Since vec_splats was implemented as a function, code such as in this example would result in a compile-time error in clang. This differs from gcc, which allows this construct.

This updates tests accordingly, and fixes PR44276 and PR44455. Sorry for the delay in getting this to you.

[steven.zhang]

clang/lib/Headers/altivec.h

13670

I am not sure if this is by intention. It is not semantics the same with this change. Before the change, if VSX is off, and POWER8_VECTOR && powerpc64 is on, vector signed/unsigned long long, signed/unsigned __int128 is not a valid candidate of vec_splats. But with this patch, they are.

[vddvss]

clang/lib/Headers/altivec.h

13670

No intention to change semantics. But AFICT, we throw an error if POWER8_VECTOR is on and VSX is off: https://github.com/llvm/llvm-project/blob/master/clang/lib/Basic/Targets/PPC.cpp#L222

[steven.zhang]

clang/lib/Headers/altivec.h

13670

Hmm, we are making assumption that, POWER8_VECTOR enables the VSX, and it is true. Thank you for pointing out this.

clang/test/CodeGen/pr44276.c

3

The assembly output is not your test point. How about doing it as this:

// RUN: %clang_cc1 -S -emit-llvm -triple powerpc64-unknown-unknown -target-cpu pwr8 %s
// expected-no-diagnostics

[vddvss]

Updated revision to address @steven.zhang's good suggestion on the test case.

This also does clang-format on altivec.h to address the harbormaster failure, although I am inclined to do /* clang-format off */, since it is a lot less readable after running clang-format.

[steven.zhang]

It LGTM now except one comment on the test. And it seems that, we still have many other builtins implementation that didn't use the _Generic.

clang/test/CodeGen/ppc-emmintrin.c

1

So, why this line of comments is removed ? It seems that, the old test was generated by the script while the new one isn't. I expect both should generate by script.

clang/lib/Headers/altivec.h

 static __inline__ vector float __ATTRS_o_ai vec_promote(float __a, int __b) {
   vector float __res = (vector float)(0);
   __res[__b] = __a;
   return __res;
 }
 
 /* vec_splats */
 
-static __inline__ vector signed char __ATTRS_o_ai vec_splats(signed char __a) {
-  return (vector signed char)(__a);
-}
-
-static __inline__ vector unsigned char __ATTRS_o_ai
-vec_splats(unsigned char __a) {
-  return (vector unsigned char)(__a);
-}
-
-static __inline__ vector short __ATTRS_o_ai vec_splats(short __a) {
-  return (vector short)(__a);
-}
-
-static __inline__ vector unsigned short __ATTRS_o_ai
-vec_splats(unsigned short __a) {
-  return (vector unsigned short)(__a);
-}
-
-static __inline__ vector int __ATTRS_o_ai vec_splats(int __a) {
-  return (vector int)(__a);
-}
-
-static __inline__ vector unsigned int __ATTRS_o_ai
-vec_splats(unsigned int __a) {
-  return (vector unsigned int)(__a);
-}
-
-#ifdef __VSX__
-static __inline__ vector signed long long __ATTRS_o_ai
-vec_splats(signed long long __a) {
-  return (vector signed long long)(__a);
-}
-
-static __inline__ vector unsigned long long __ATTRS_o_ai
-vec_splats(unsigned long long __a) {
-  return (vector unsigned long long)(__a);
-}
-
 #if defined(__POWER8_VECTOR__) && defined(__powerpc64__)
-static __inline__ vector signed __int128 __ATTRS_o_ai
-vec_splats(signed __int128 __a) {
-  return (vector signed __int128)(__a);
-}
-
-static __inline__ vector unsigned __int128 __ATTRS_o_ai
-vec_splats(unsigned __int128 __a) {
-  return (vector unsigned __int128)(__a);
-}
-
+#define vec_splats(N)                                     \
+  _Generic((N),                                           \
+    unsigned char:      ((vector unsigned char)(N)),      \
+    signed char:        ((vector signed char)(N)),        \
+    unsigned short:     ((vector unsigned short)(N)),     \
+    signed short:       ((vector signed short)(N)),       \
+    unsigned int:       ((vector unsigned int)(N)),       \
+    signed int:         ((vector signed int)(N)),         \
+    unsigned long long: ((vector unsigned long long)(N)), \
+    signed long long:   ((vector signed long long)(N)),   \
+    unsigned __int128:  ((vector unsigned __int128)(N)),  \
+    signed __int128:    ((vector signed __int128)(N)),    \
+    float:              ((vector float)(N)),              \
+    double:             ((vector double)(N))              \
+  )
+#elif defined(__VSX__)
+#define vec_splats(N)                                     \
+  _Generic((N),                                           \
+    unsigned char:      ((vector unsigned char)(N)),      \
+    signed char:        ((vector signed char)(N)),        \
+    unsigned short:     ((vector unsigned short)(N)),     \
+    signed short:       ((vector signed short)(N)),       \
+    unsigned int:       ((vector unsigned int)(N)),       \
+    signed int:         ((vector signed int)(N)),         \
+    unsigned long long: ((vector unsigned long long)(N)), \
+    signed long long:   ((vector signed long long)(N)),   \
+    float:              ((vector float)(N)),              \
+    double:             ((vector double)(N))              \
+  )
+#else
+#define vec_splats(N)                                     \
+  _Generic((N),                                           \
+    unsigned char:      ((vector unsigned char)(N)),      \
+    signed char:        ((vector signed char)(N)),        \
+    unsigned short:     ((vector unsigned short)(N)),     \
+    signed short:       ((vector signed short)(N)),       \
+    unsigned int:       ((vector unsigned int)(N)),       \
+    signed int:         ((vector signed int)(N)),         \
+    float:              ((vector float)(N))               \
+  )
 #endif
 
-static __inline__ vector double __ATTRS_o_ai vec_splats(double __a) {
-  return (vector double)(__a);
-}
-#endif
-
-static __inline__ vector float __ATTRS_o_ai vec_splats(float __a) {
-  return (vector float)(__a);
-}
-
 /* ----------------------------- predicates --------------------------------- */
 
 /* vec_all_eq */
 
 static __inline__ int __ATTRS_o_ai vec_all_eq(vector signed char __a,
                                               vector signed char __b) {
   return __builtin_altivec_vcmpequb_p(__CR6_LT, (vector char)__a,
                                       (vector char)__b);

clang/test/CodeGen/ppc-emmintrin.c

-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // REQUIRES: powerpc-registered-target
 
 // RUN: %clang -S -emit-llvm -target powerpc64-unknown-linux-gnu -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \
 // RUN:  -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-BE
 // RUN: %clang -S -emit-llvm -target powerpc64le-unknown-linux-gnu -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \
 // RUN:   -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-LE
 
 // CHECK-BE-DAG: @_mm_movemask_pd.perm_mask = internal constant <4 x i32> <i32 -2139062144, i32 -2139062144, i32 -2139062144, i32 -2139078656>, align 16

 // CHECK-LE-NEXT: [[REG155:[0-9a-zA-Z_%.]+]] = sub nsw i32 16, [[REG154]]
 // CHECK-LE-NEXT: [[REG156:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_sld(unsigned char vector[16], unsigned char vector[16], unsigned int)(<16 x i8> zeroinitializer, <16 x i8> [[REG153]], i32 zeroext [[REG155]])
 // CHECK-LE-NEXT: store <16 x i8> [[REG156]], <16 x i8>* [[REG157:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-LE-NEXT: br label %[[REG158:[0-9a-zA-Z_%.]+]]
 // CHECK-LE: [[REG151]]:
 // CHECK-LE: [[REG159:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG144]], align 4
 // CHECK-LE-NEXT: [[REG160:[0-9a-zA-Z_%.]+]] = mul nsw i32 [[REG159]], 8
 // CHECK-LE-NEXT: [[REG161:[0-9a-zA-Z_%.]+]] = trunc i32 [[REG160]] to i8
-// CHECK-LE-NEXT: [[REG162:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_splats(unsigned char)(i8 zeroext [[REG161]])
+// CHECK-LE-NEXT: [[REG162A:[0-9a-zA-Z_%.]+]] = insertelement <16 x i8> undef, i8 [[REG161]], i32 0
+// CHECK-LE-NEXT: [[REG162:[0-9a-zA-Z_%.]+]]  = shufflevector <16 x i8> [[REG162A]], <16 x i8> undef, <16 x i32> zeroinitializer
 // CHECK-LE-NEXT: store <16 x i8> [[REG162]], <16 x i8>* [[REG163:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-LE-NEXT: [[REG164:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG143]], align 16
 // CHECK-LE-NEXT: [[REG165:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG164]] to <16 x i8>
 // CHECK-LE-NEXT: [[REG166:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG163]], align 16
 // CHECK-LE-NEXT: [[REG167:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_sro(unsigned char vector[16], unsigned char vector[16])(<16 x i8> [[REG165]], <16 x i8> [[REG166]])
 // CHECK-LE-NEXT: store <16 x i8> [[REG167]], <16 x i8>* [[REG157]], align 16
 // CHECK-LE-NEXT: br label %[[REG158:[0-9a-zA-Z_%.]+]]
 // CHECK-LE: [[REG158]]:
 // CHECK-LE: br label %[[REG168:[0-9a-zA-Z_%.]+]]
 // CHECK-LE: [[REG149]]:
 // CHECK-LE: store <16 x i8> zeroinitializer, <16 x i8>* [[REG157]], align 16
 // CHECK-LE-NEXT: br label %[[REG168:[0-9a-zA-Z_%.]+]]
 // CHECK-LE: [[REG168]]:
 // CHECK-LE: [[REG169:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG157]], align 16
 // CHECK-LE-NEXT: [[REG170:[0-9a-zA-Z_%.]+]] = bitcast <16 x i8> [[REG169]] to <2 x i64>
 // CHECK-LE-NEXT: ret <2 x i64> [[REG170]]
 
 // CHECK-BE: [[REG171:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG144]], align 4
 // CHECK-BE-NEXT: [[REG172:[0-9a-zA-Z_%.]+]] = mul nsw i32 [[REG171]], 8
 // CHECK-BE-NEXT: [[REG173:[0-9a-zA-Z_%.]+]] = trunc i32 [[REG172]] to i8
-// CHECK-BE-NEXT: [[REG174:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_splats(unsigned char)(i8 zeroext [[REG173]])
+// CHECK-BE-NEXT: [[REG174A:[0-9a-zA-Z_%.]+]] = insertelement <16 x i8> undef, i8 [[REG173]], i32 0
+// CHECK-BE-NEXT: [[REG174:[0-9a-zA-Z_%.]+]]  = shufflevector <16 x i8> [[REG174A]], <16 x i8> undef, <16 x i32> zeroinitializer
 // CHECK-BE-NEXT: store <16 x i8> [[REG174]], <16 x i8>* [[REG175:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-BE-NEXT: [[REG176:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG143]], align 16
 // CHECK-BE-NEXT: [[REG177:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG176]] to <16 x i8>
 // CHECK-BE-NEXT: [[REG178:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG175]], align 16
 // CHECK-BE-NEXT: [[REG179:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_slo(unsigned char vector[16], unsigned char vector[16])(<16 x i8> [[REG177]], <16 x i8> [[REG178]])
 // CHECK-BE-NEXT: store <16 x i8> [[REG179]], <16 x i8>* [[REG180:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-BE-NEXT: br label %[[REG181:[0-9a-zA-Z_%.]+]]
 // CHECK-BE: [[REG149]]:

 // CHECK-NEXT: [[REG227:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG226]] to <2 x double>
 // CHECK-NEXT: ret <2 x double> [[REG227]]
 
 // CHECK: define available_externally <2 x double> @_mm_cmpeq_sd(<2 x double> [[REG228:[0-9a-zA-Z_%.]+]], <2 x double> [[REG229:[0-9a-zA-Z_%.]+]])
 // CHECK: store <2 x double> [[REG228]], <2 x double>* [[REG230:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: store <2 x double> [[REG229]], <2 x double>* [[REG231:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG232:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG230]], align 16
 // CHECK-NEXT: [[REG233:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG232]], i32 0
-// CHECK-NEXT: [[REG234:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG233]])
+// CHECK-NEXT: [[REG234A:[0-9a-zA-Z_%.]+]] = insertelement <2 x double> undef, double [[REG233]], i32 0
+// CHECK-NEXT: [[REG234:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x double> [[REG234A]], <2 x double> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: store <2 x double> [[REG234]], <2 x double>* [[REG235:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG236:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG231]], align 16
 // CHECK-NEXT: [[REG237:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG236]], i32 0
-// CHECK-NEXT: [[REG238:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG237]])
+// CHECK-NEXT: [[REG238A:[0-9a-zA-Z_%.]+]] = insertelement <2 x double> undef, double [[REG237]], i32 0
+// CHECK-NEXT: [[REG238:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x double> [[REG238A]], <2 x double> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: store <2 x double> [[REG238]], <2 x double>* [[REG239:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG240:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG235]], align 16
 // CHECK-NEXT: [[REG241:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG239]], align 16
 // CHECK-NEXT: [[REG242:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_cmpeq(double vector[2], double vector[2])(<2 x double> [[REG240]], <2 x double> [[REG241]])
 // CHECK-NEXT: [[REG243:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG242]] to <2 x double>
 // CHECK-NEXT: store <2 x double> [[REG243]], <2 x double>* [[REG244:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG245:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG244]], align 16
 // CHECK-NEXT: [[REG246:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG245]], i32 0
 // CHECK-NEXT: [[REG247:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG230]], align 16
 // CHECK-NEXT: [[REG248:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG247]], i32 1
 // CHECK-NEXT: [[REG249:[0-9a-zA-Z_%.]+]] = call <2 x double> @_mm_setr_pd(double [[REG246]], double [[REG248]])
 // CHECK-NEXT: ret <2 x double> [[REG249]]
 
 // CHECK: define available_externally <2 x double> @_mm_cmpge_pd
 // CHECK: [[REG250:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_cmpge(double vector[2], double vector[2])
 // CHECK-NEXT: [[REG251:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG250]] to <2 x double>
 // CHECK-NEXT: ret <2 x double> [[REG251]]
 
 // CHECK: define available_externally <2 x double> @_mm_cmpge_sd(<2 x double> [[REG252:[0-9a-zA-Z_%.]+]], <2 x double> [[REG253:[0-9a-zA-Z_%.]+]])
 // CHECK: store <2 x double> [[REG252]], <2 x double>* [[REG254:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: store <2 x double> [[REG253]], <2 x double>* [[REG255:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG256:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG254]], align 16
 // CHECK-NEXT: [[REG257:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG256]], i32 0
-// CHECK-NEXT: [[REG258:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG257]])
+// CHECK-NEXT: [[REG258A:[0-9a-zA-Z_%.]+]] = insertelement <2 x double> undef, double [[REG257]], i32 0
+// CHECK-NEXT: [[REG258:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x double> [[REG258A]], <2 x double> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: store <2 x double> [[REG258]], <2 x double>* [[REG259:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG260:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG255]], align 16
 // CHECK-NEXT: [[REG261:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG260]], i32 0
-// CHECK-NEXT: [[REG262:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG261]])
+// CHECK-NEXT: [[REG262A:[0-9a-zA-Z_%.]+]] = insertelement <2 x double> undef, double [[REG261]], i32 0
+// CHECK-NEXT: [[REG262:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x double> [[REG262A]], <2 x double> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: store <2 x double> [[REG262]], <2 x double>* [[REG263:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG264:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG259]], align 16
 // CHECK-NEXT: [[REG265:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG263]], align 16
 // CHECK-NEXT: [[REG266:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_cmpge(double vector[2], double vector[2])(<2 x double> [[REG264]], <2 x double> [[REG265]])
 // CHECK-NEXT: [[REG267:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG266]] to <2 x double>
 // CHECK-NEXT: store <2 x double> [[REG267]], <2 x double>* [[REG268:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG269:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG268]], align 16
 // CHECK-NEXT: [[REG270:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG269]], i32 0
 // CHECK-NEXT: [[REG271:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG254]], align 16
 // CHECK-NEXT: [[REG272:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG271]], i32 1
 // CHECK-NEXT: [[REG273:[0-9a-zA-Z_%.]+]] = call <2 x double> @_mm_setr_pd(double [[REG270]], double [[REG272]])
 // CHECK-NEXT: ret <2 x double> [[REG273]]
 
 // CHECK: define available_externally <2 x double> @_mm_cmpgt_pd
 // CHECK: [[REG274:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_cmpgt(double vector[2], double vector[2])
 // CHECK-NEXT: [[REG275:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG274]] to <2 x double>
 // CHECK-NEXT: ret <2 x double> [[REG275]]
 
 // CHECK: define available_externally <2 x double> @_mm_cmpgt_sd(<2 x double> [[REG276:[0-9a-zA-Z_%.]+]], <2 x double> [[REG277:[0-9a-zA-Z_%.]+]])
 // CHECK: store <2 x double> [[REG276]], <2 x double>* [[REG278:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: store <2 x double> [[REG277]], <2 x double>* [[REG279:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG280:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG278]], align 16
 // CHECK-NEXT: [[REG281:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG280]], i32 0
-// CHECK-NEXT: [[REG282:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG281]])
+// CHECK-NEXT: [[REG282A:[0-9a-zA-Z_%.]+]] = insertelement <2 x double> undef, double [[REG281]], i32 0
+// CHECK-NEXT: [[REG282:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x double> [[REG282A]], <2 x double> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: store <2 x double> [[REG282]], <2 x double>* [[REG283:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG284:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG279]], align 16
 // CHECK-NEXT: [[REG285:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG284]], i32 0
-// CHECK-NEXT: [[REG286:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG285]])
+// CHECK-NEXT: [[REG286A:[0-9a-zA-Z_%.]+]] = insertelement <2 x double> undef, double [[REG285]], i32 0
+// CHECK-NEXT: [[REG286:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x double> [[REG286A]], <2 x double> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: store <2 x double> [[REG286]], <2 x double>* [[REG287:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG288:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG283]], align 16
 // CHECK-NEXT: [[REG289:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG287]], align 16
 // CHECK-NEXT: [[REG290:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_cmpgt(double vector[2], double vector[2])(<2 x double> [[REG288]], <2 x double> [[REG289]])
 // CHECK-NEXT: [[REG291:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG290]] to <2 x double>
 // CHECK-NEXT: store <2 x double> [[REG291]], <2 x double>* [[REG292:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG293:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG292]], align 16
 // CHECK-NEXT: [[REG294:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG293]], i32 0
 // CHECK-NEXT: [[REG295:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG278]], align 16
 // CHECK-NEXT: [[REG296:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG295]], i32 1
 // CHECK-NEXT: [[REG297:[0-9a-zA-Z_%.]+]] = call <2 x double> @_mm_setr_pd(double [[REG294]], double [[REG296]])
 // CHECK-NEXT: ret <2 x double> [[REG297]]
 
 // CHECK: define available_externally <2 x double> @_mm_cmple_pd
 // CHECK: [[REG298:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_cmple(double vector[2], double vector[2])
 // CHECK-NEXT: [[REG299:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG298]] to <2 x double>
 // CHECK-NEXT: ret <2 x double> [[REG299]]
 
 // CHECK: define available_externally <2 x double> @_mm_cmple_sd(<2 x double> [[REG300:[0-9a-zA-Z_%.]+]], <2 x double> [[REG301:[0-9a-zA-Z_%.]+]])
 // CHECK: store <2 x double> [[REG300]], <2 x double>* [[REG302:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: store <2 x double> [[REG301]], <2 x double>* [[REG303:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG304:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG302]], align 16
 // CHECK-NEXT: [[REG305:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG304]], i32 0
-// CHECK-NEXT: [[REG306:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG305]])
+// CHECK-NEXT: [[REG306A:[0-9a-zA-Z_%.]+]] = insertelement <2 x double> undef, double [[REG305]], i32 0
+// CHECK-NEXT: [[REG306:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x double> [[REG306A]], <2 x double> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: store <2 x double> [[REG306]], <2 x double>* [[REG307:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG308:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG303]], align 16
 // CHECK-NEXT: [[REG309:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG308]], i32 0
-// CHECK-NEXT: [[REG310:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG309]])
+// CHECK-NEXT: [[REG310A:[0-9a-zA-Z_%.]+]] = insertelement <2 x double> undef, double [[REG309]], i32 0
+// CHECK-NEXT: [[REG310:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x double> [[REG310A]], <2 x double> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: store <2 x double> [[REG310]], <2 x double>* [[REG311:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG312:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG307]], align 16
 // CHECK-NEXT: [[REG313:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG311]], align 16
 // CHECK-NEXT: [[REG314:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_cmple(double vector[2], double vector[2])(<2 x double> [[REG312]], <2 x double> [[REG313]])
 // CHECK-NEXT: [[REG315:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG314]] to <2 x double>
 // CHECK-NEXT: store <2 x double> [[REG315]], <2 x double>* [[REG316:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG317:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG316]], align 16
 // CHECK-NEXT: [[REG318:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG317]], i32 0
 // CHECK-NEXT: [[REG319:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG302]], align 16
 // CHECK-NEXT: [[REG320:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG319]], i32 1
 // CHECK-NEXT: [[REG321:[0-9a-zA-Z_%.]+]] = call <2 x double> @_mm_setr_pd(double [[REG318]], double [[REG320]])
 // CHECK-NEXT: ret <2 x double> [[REG321]]
 
 // CHECK: define available_externally <2 x double> @_mm_cmplt_pd
 // CHECK: [[REG322:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_cmplt(double vector[2], double vector[2])
 // CHECK-NEXT: [[REG323:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG322]] to <2 x double>
 // CHECK-NEXT: ret <2 x double> [[REG323]]
 
 // CHECK: define available_externally <2 x double> @_mm_cmplt_sd(<2 x double> [[REG324:[0-9a-zA-Z_%.]+]], <2 x double> [[REG325:[0-9a-zA-Z_%.]+]])
 // CHECK: store <2 x double> [[REG324]], <2 x double>* [[REG326:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: store <2 x double> [[REG325]], <2 x double>* [[REG327:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG328:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG326]], align 16
 // CHECK-NEXT: [[REG329:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG328]], i32 0
-// CHECK-NEXT: [[REG330:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG329]])
+// CHECK-NEXT: [[REG330A:[0-9a-zA-Z_%.]+]] = insertelement <2 x double> undef, double [[REG329]], i32 0
+// CHECK-NEXT: [[REG330:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x double> [[REG330A]], <2 x double> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: store <2 x double> [[REG330]], <2 x double>* [[REG331:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG332:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG327]], align 16
 // CHECK-NEXT: [[REG333:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG332]], i32 0
-// CHECK-NEXT: [[REG334:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG333]])
+// CHECK-NEXT: [[REG334A:[0-9a-zA-Z_%.]+]] = insertelement <2 x double> undef, double [[REG333]], i32 0
+// CHECK-NEXT: [[REG334:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x double> [[REG334A]], <2 x double> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: store <2 x double> [[REG334]], <2 x double>* [[REG335:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG336:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG331]], align 16
 // CHECK-NEXT: [[REG337:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG335]], align 16
 // CHECK-NEXT: [[REG338:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_cmplt(double vector[2], double vector[2])(<2 x double> [[REG336]], <2 x double> [[REG337]])
 // CHECK-NEXT: [[REG339:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG338]] to <2 x double>
 // CHECK-NEXT: store <2 x double> [[REG339]], <2 x double>* [[REG340:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG341:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG340]], align 16
 // CHECK-NEXT: [[REG342:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG341]], i32 0

 // CHECK-NEXT: [[REG357:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_nor(double vector[2], double vector[2])(<2 x double> [[REG355]], <2 x double> [[REG356]])
 // CHECK-NEXT: ret <2 x double> [[REG357]]
 
 // CHECK: define available_externally <2 x double> @_mm_cmpneq_sd(<2 x double> [[REG358:[0-9a-zA-Z_%.]+]], <2 x double> [[REG359:[0-9a-zA-Z_%.]+]])
 // CHECK: store <2 x double> [[REG358]], <2 x double>* [[REG360:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: store <2 x double> [[REG359]], <2 x double>* [[REG361:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG362:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG360]], align 16
 // CHECK-NEXT: [[REG363:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG362]], i32 0
-// CHECK-NEXT: [[REG364:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG363]])
+// CHECK-NEXT: [[REG364A:[0-9a-zA-Z_%.]+]] = insertelement <2 x double> undef, double [[REG363]], i32 0
+// CHECK-NEXT: [[REG364:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x double> [[REG364A]], <2 x double> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: store <2 x double> [[REG364]], <2 x double>* [[REG365:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG366:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG361]], align 16
 // CHECK-NEXT: [[REG367:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG366]], i32 0
-// CHECK-NEXT: [[REG368:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG367]])
+// CHECK-NEXT: [[REG368A:[0-9a-zA-Z_%.]+]] = insertelement <2 x double> undef, double [[REG367]], i32 0
+// CHECK-NEXT: [[REG368:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x double> [[REG368A]], <2 x double> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: store <2 x double> [[REG368]], <2 x double>* [[REG369:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG370:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG365]], align 16
 // CHECK-NEXT: [[REG371:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG369]], align 16
 // CHECK-NEXT: [[REG372:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_cmpeq(double vector[2], double vector[2])(<2 x double> [[REG370]], <2 x double> [[REG371]])
 // CHECK-NEXT: [[REG373:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG372]] to <2 x double>
 // CHECK-NEXT: store <2 x double> [[REG373]], <2 x double>* [[REG374:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG375:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG374]], align 16
 // CHECK-NEXT: [[REG376:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG374]], align 16

 // CHECK-NEXT: [[REG384:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG383]] to <2 x double>
 // CHECK-NEXT: ret <2 x double> [[REG384]]
 
 // CHECK: define available_externally <2 x double> @_mm_cmpnge_sd(<2 x double> [[REG385:[0-9a-zA-Z_%.]+]], <2 x double> [[REG386:[0-9a-zA-Z_%.]+]])
 // CHECK: store <2 x double> [[REG385]], <2 x double>* [[REG387:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: store <2 x double> [[REG386]], <2 x double>* [[REG388:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG389:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG387]], align 16
 // CHECK-NEXT: [[REG390:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG389]], i32 0
-// CHECK-NEXT: [[REG391:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG390]])
+// CHECK-NEXT: [[REG391A:[0-9a-zA-Z_%.]+]] = insertelement <2 x double> undef, double [[REG390]], i32 0
+// CHECK-NEXT: [[REG391:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x double> [[REG391A]], <2 x double> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: store <2 x double> [[REG391]], <2 x double>* [[REG392:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG393:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG388]], align 16
 // CHECK-NEXT: [[REG394:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG393]], i32 0
-// CHECK-NEXT: [[REG395:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG394]])
+// CHECK-NEXT: [[REG395A:[0-9a-zA-Z_%.]+]] = insertelement <2 x double> undef, double [[REG394]], i32 0
+// CHECK-NEXT: [[REG395:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x double> [[REG395A]], <2 x double> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: store <2 x double> [[REG395]], <2 x double>* [[REG396:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG397:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG392]], align 16
 // CHECK-NEXT: [[REG398:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG396]], align 16
 // CHECK-NEXT: [[REG399:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_cmplt(double vector[2], double vector[2])(<2 x double> [[REG397]], <2 x double> [[REG398]])
 // CHECK-NEXT: [[REG400:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG399]] to <2 x double>
 // CHECK-NEXT: store <2 x double> [[REG400]], <2 x double>* [[REG401:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG402:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG401]], align 16
 // CHECK-NEXT: [[REG403:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG402]], i32 0

 // CHECK-NEXT: [[REG414:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG413]] to <2 x double>
 // CHECK-NEXT: ret <2 x double> [[REG414]]
 
 // CHECK: define available_externally <2 x double> @_mm_cmpngt_sd(<2 x double> [[REG415:[0-9a-zA-Z_%.]+]], <2 x double> [[REG416:[0-9a-zA-Z_%.]+]])
 // CHECK: store <2 x double> [[REG415]], <2 x double>* [[REG417:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: store <2 x double> [[REG416]], <2 x double>* [[REG418:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG419:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG417]], align 16
 // CHECK-NEXT: [[REG420:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG419]], i32 0
-// CHECK-NEXT: [[REG421:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG420]])
+// CHECK-NEXT: [[REG421A:[0-9a-zA-Z_%.]+]] = insertelement <2 x double> undef, double [[REG420]], i32 0
+// CHECK-NEXT: [[REG421:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x double> [[REG421A]], <2 x double> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: store <2 x double> [[REG421]], <2 x double>* [[REG422:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG423:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG418]], align 16
 // CHECK-NEXT: [[REG424:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG423]], i32 0
-// CHECK-NEXT: [[REG425:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG424]])
+// CHECK-NEXT: [[REG425A:[0-9a-zA-Z_%.]+]] = insertelement <2 x double> undef, double [[REG424]], i32 0
+// CHECK-NEXT: [[REG425:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x double> [[REG425A]], <2 x double> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: store <2 x double> [[REG425]], <2 x double>* [[REG426:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG427:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG422]], align 16
 // CHECK-NEXT: [[REG428:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG426]], align 16
 // CHECK-NEXT: [[REG429:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_cmple(double vector[2], double vector[2])(<2 x double> [[REG427]], <2 x double> [[REG428]])
 // CHECK-NEXT: [[REG430:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG429]] to <2 x double>
 // CHECK-NEXT: store <2 x double> [[REG430]], <2 x double>* [[REG431:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG432:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG431]], align 16
 // CHECK-NEXT: [[REG433:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG432]], i32 0
 // CHECK-NEXT: [[REG434:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG417]], align 16
 // CHECK-NEXT: [[REG435:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG434]], i32 1
 // CHECK-NEXT: [[REG436:[0-9a-zA-Z_%.]+]] = call <2 x double> @_mm_setr_pd(double [[REG433]], double [[REG435]])
 // CHECK-NEXT: ret <2 x double> [[REG436]]
 
 // CHECK: define available_externally <2 x double> @_mm_cmpnle_pd
 // CHECK: [[REG437:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_cmpgt(double vector[2], double vector[2])
 // CHECK-NEXT: [[REG438:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG437]] to <2 x double>
 // CHECK-NEXT: ret <2 x double> [[REG438]]
 
 // CHECK: define available_externally <2 x double> @_mm_cmpnle_sd(<2 x double> [[REG439:[0-9a-zA-Z_%.]+]], <2 x double> [[REG440:[0-9a-zA-Z_%.]+]])
 // CHECK: store <2 x double> [[REG439]], <2 x double>* [[REG441:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: store <2 x double> [[REG440]], <2 x double>* [[REG442:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG443:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG441]], align 16
 // CHECK-NEXT: [[REG444:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG443]], i32 0
-// CHECK-NEXT: [[REG445:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG444]])
+// CHECK-NEXT: [[REG445A:[0-9a-zA-Z_%.]+]] = insertelement <2 x double> undef, double [[REG444]], i32 0
+// CHECK-NEXT: [[REG445:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x double> [[REG445A]], <2 x double> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: store <2 x double> [[REG445]], <2 x double>* [[REG446:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG447:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG442]], align 16
 // CHECK-NEXT: [[REG448:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG447]], i32 0
-// CHECK-NEXT: [[REG449:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG448]])
+// CHECK-NEXT: [[REG449A:[0-9a-zA-Z_%.]+]] = insertelement <2 x double> undef, double [[REG448]], i32 0
+// CHECK-NEXT: [[REG449:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x double> [[REG449A]], <2 x double> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: store <2 x double> [[REG449]], <2 x double>* [[REG450:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG451:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG446]], align 16
 // CHECK-NEXT: [[REG452:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG450]], align 16
 // CHECK-NEXT: [[REG453:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_cmpge(double vector[2], double vector[2])(<2 x double> [[REG451]], <2 x double> [[REG452]])
 // CHECK-NEXT: [[REG454:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG453]] to <2 x double>
 // CHECK-NEXT: store <2 x double> [[REG454]], <2 x double>* [[REG455:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG456:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG455]], align 16
 // CHECK-NEXT: [[REG457:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG456]], i32 0
 // CHECK-NEXT: [[REG458:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG441]], align 16
 // CHECK-NEXT: [[REG459:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG458]], i32 1
 // CHECK-NEXT: [[REG460:[0-9a-zA-Z_%.]+]] = call <2 x double> @_mm_setr_pd(double [[REG457]], double [[REG459]])
 // CHECK-NEXT: ret <2 x double> [[REG460]]
 
 // CHECK: define available_externally <2 x double> @_mm_cmpnlt_pd
 // CHECK: [[REG461:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_cmpge(double vector[2], double vector[2])
 // CHECK-NEXT: [[REG462:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG461]] to <2 x double>
 // CHECK-NEXT: ret <2 x double> [[REG462]]
 
 // CHECK: define available_externally <2 x double> @_mm_cmpnlt_sd(<2 x double> [[REG463:[0-9a-zA-Z_%.]+]], <2 x double> [[REG464:[0-9a-zA-Z_%.]+]])
 // CHECK: store <2 x double> [[REG463]], <2 x double>* [[REG465:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: store <2 x double> [[REG464]], <2 x double>* [[REG466:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG467:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG465]], align 16
 // CHECK-NEXT: [[REG468:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG467]], i32 0
-// CHECK-NEXT: [[REG469:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG468]])
+// CHECK-NEXT: [[REG469A:[0-9a-zA-Z_%.]+]] = insertelement <2 x double> undef, double [[REG468]], i32 0
+// CHECK-NEXT: [[REG469:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x double> [[REG469A]], <2 x double> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: store <2 x double> [[REG469]], <2 x double>* [[REG470:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG471:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG466]], align 16
 // CHECK-NEXT: [[REG472:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG471]], i32 0
-// CHECK-NEXT: [[REG473:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG472]])
+// CHECK-NEXT: [[REG473A:[0-9a-zA-Z_%.]+]] = insertelement <2 x double> undef, double [[REG472]], i32 0
+// CHECK-NEXT: [[REG473:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x double> [[REG473A]], <2 x double> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: store <2 x double> [[REG473]], <2 x double>* [[REG474:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG475:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG470]], align 16
 // CHECK-NEXT: [[REG476:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG474]], align 16
 // CHECK-NEXT: [[REG477:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_cmpge(double vector[2], double vector[2])(<2 x double> [[REG475]], <2 x double> [[REG476]])
 // CHECK-NEXT: [[REG478:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG477]] to <2 x double>
 // CHECK-NEXT: store <2 x double> [[REG478]], <2 x double>* [[REG479:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG480:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG479]], align 16
 // CHECK-NEXT: [[REG481:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG480]], i32 0

 // CHECK-NEXT: [[REG500:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG499]] to <2 x double>
 // CHECK-NEXT: ret <2 x double> [[REG500]]
 
 // CHECK: define available_externally <2 x double> @_mm_cmpord_sd(<2 x double> [[REG501:[0-9a-zA-Z_%.]+]], <2 x double> [[REG502:[0-9a-zA-Z_%.]+]])
 // CHECK: store <2 x double> [[REG501]], <2 x double>* [[REG503:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: store <2 x double> [[REG502]], <2 x double>* [[REG504:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG505:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG503]], align 16
 // CHECK-NEXT: [[REG506:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG505]], i32 0
-// CHECK-NEXT: [[REG507:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG506]])
+// CHECK-NEXT: [[REG507A:[0-9a-zA-Z_%.]+]] = insertelement <2 x double> undef, double [[REG506]], i32 0
+// CHECK-NEXT: [[REG507:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x double> [[REG507A]], <2 x double> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG508:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG504]], align 16
 // CHECK-NEXT: [[REG509:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG508]], i32 0
-// CHECK-NEXT: [[REG510:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG509]])
+// CHECK-NEXT: [[REG510A:[0-9a-zA-Z_%.]+]] = insertelement <2 x double> undef, double [[REG509]], i32 0
+// CHECK-NEXT: [[REG510:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x double> [[REG510A]], <2 x double> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG511:[0-9a-zA-Z_%.]+]] = call <2 x double> @_mm_cmpord_pd(<2 x double> [[REG507]], <2 x double> [[REG510]])
 // CHECK-NEXT: store <2 x double> [[REG511]], <2 x double>* [[REG512:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG513:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG512]], align 16
 // CHECK-NEXT: [[REG514:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG513]], i32 0
 // CHECK-NEXT: [[REG515:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG503]], align 16
 // CHECK-NEXT: [[REG516:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG515]], i32 1
 // CHECK-NEXT: [[REG517:[0-9a-zA-Z_%.]+]] = call <2 x double> @_mm_setr_pd(double [[REG514]], double [[REG516]])
 // CHECK-NEXT: ret <2 x double> [[REG517]]

 // CHECK-NEXT: [[REG536:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG535]] to <2 x double>
 // CHECK-NEXT: ret <2 x double> [[REG536]]
 
 // CHECK: define available_externally <2 x double> @_mm_cmpunord_sd(<2 x double> [[REG537:[0-9a-zA-Z_%.]+]], <2 x double> [[REG538:[0-9a-zA-Z_%.]+]])
 // CHECK: store <2 x double> [[REG537]], <2 x double>* [[REG539:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: store <2 x double> [[REG538]], <2 x double>* [[REG540:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG541:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG539]], align 16
 // CHECK-NEXT: [[REG542:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG541]], i32 0
-// CHECK-NEXT: [[REG543:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG542]])
+// CHECK-NEXT: [[REG543A:[0-9a-zA-Z_%.]+]] = insertelement <2 x double> undef, double [[REG542]], i32 0
+// CHECK-NEXT: [[REG543:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x double> [[REG543A]], <2 x double> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG544:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG540]], align 16
 // CHECK-NEXT: [[REG545:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG544]], i32 0
-// CHECK-NEXT: [[REG546:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG545]])
+// CHECK-NEXT: [[REG546A:[0-9a-zA-Z_%.]+]] = insertelement <2 x double> undef, double [[REG545]], i32 0
+// CHECK-NEXT: [[REG546:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x double> [[REG546A]], <2 x double> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG547:[0-9a-zA-Z_%.]+]] = call <2 x double> @_mm_cmpunord_pd(<2 x double> [[REG543]], <2 x double> [[REG546]])
 // CHECK-NEXT: store <2 x double> [[REG547]], <2 x double>* [[REG548:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG549:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG548]], align 16
 // CHECK-NEXT: [[REG550:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG549]], i32 0
 // CHECK-NEXT: [[REG551:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG539]], align 16
 // CHECK-NEXT: [[REG552:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG551]], i32 1
 // CHECK-NEXT: [[REG553:[0-9a-zA-Z_%.]+]] = call <2 x double> @_mm_setr_pd(double [[REG550]], double [[REG552]])
 // CHECK-NEXT: ret <2 x double> [[REG553]]

 // CHECK-NEXT: [[REG630:[0-9a-zA-Z_%.]+]] = bitcast <4 x i32> [[REG629]] to <4 x float>
 // CHECK-NEXT: store <4 x float> [[REG630]], <4 x float>* [[REG631:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG632:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG631]], align 16
 // CHECK-NEXT: ret <4 x float> [[REG632]]
 
 // CHECK: define available_externally <2 x double> @_mm_cvtpi32_pd(i64 [[REG633:[0-9a-zA-Z_%.]+]])
 // CHECK: store i64 [[REG633]], i64* [[REG634:[0-9a-zA-Z_%.]+]], align 8
 // CHECK-NEXT: [[REG635:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG634]], align 8
-// CHECK-NEXT: [[REG636:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 [[REG635]])
+// CHECK-NEXT: [[REG636A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 [[REG635]], i32 0
+// CHECK-NEXT: [[REG636:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG636A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG637:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG636]] to <4 x i32>
 // CHECK-NEXT: store <4 x i32> [[REG637]], <4 x i32>* [[REG638:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG639:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG638]], align 16
 // CHECK-NEXT: [[REG640:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_unpackl(int vector[4])(<4 x i32> [[REG639]])
 // CHECK-NEXT: store <2 x i64> [[REG640]], <2 x i64>* [[REG641:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG642:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG641]], align 16
 // CHECK-NEXT: [[REG643:[0-9a-zA-Z_%.]+]] = sitofp <2 x i64> [[REG642]] to <2 x double>
 // CHECK-NEXT: [[REG644:[0-9a-zA-Z_%.]+]] = fmul <2 x double> [[REG643]], <double 1.000000e+00, double 1.000000e+00>

 // CHECK-NEXT: [[REG934:[0-9a-zA-Z_%.]+]] = load <2 x i64>*, <2 x i64>** [[REG933]], align 8
 // CHECK-NEXT: [[REG935:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG934]], align 16
 // CHECK-NEXT: ret <2 x i64> [[REG935]]
 
 // CHECK: define available_externally <2 x double> @_mm_load1_pd(double* [[REG936:[0-9a-zA-Z_%.]+]])
 // CHECK: store double* [[REG936]], double** [[REG937:[0-9a-zA-Z_%.]+]], align 8
 // CHECK-NEXT: [[REG938:[0-9a-zA-Z_%.]+]] = load double*, double** [[REG937]], align 8
 // CHECK-NEXT: [[REG939:[0-9a-zA-Z_%.]+]] = load double, double* [[REG938]], align 8
-// CHECK-NEXT: [[REG940:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG939]])
+// CHECK-NEXT: [[REG940A:[0-9a-zA-Z_%.]+]] = insertelement <2 x double> undef, double [[REG939]], i32 0
+// CHECK-NEXT: [[REG940:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x double> [[REG940A]], <2 x double> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: ret <2 x double> [[REG940]]
 
 // CHECK: define available_externally <2 x double> @_mm_loadh_pd(<2 x double> [[REG941:[0-9a-zA-Z_%.]+]], double* [[REG942:[0-9a-zA-Z_%.]+]])
 // CHECK: store <2 x double> [[REG941]], <2 x double>* [[REG943:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: store double* [[REG942]], double** [[REG944:[0-9a-zA-Z_%.]+]], align 8
 // CHECK-NEXT: [[REG945:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG943]], align 16
 // CHECK-NEXT: store <2 x double> [[REG945]], <2 x double>* [[REG946:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG947:[0-9a-zA-Z_%.]+]] = load double*, double** [[REG944]], align 8

 // CHECK: [[REG1050:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_max(double vector[2], double vector[2])
 // CHECK-NEXT: ret <2 x double> [[REG1050]]
 
 // CHECK: define available_externally <2 x double> @_mm_max_sd(<2 x double> [[REG1051:[0-9a-zA-Z_%.]+]], <2 x double> [[REG1052:[0-9a-zA-Z_%.]+]])
 // CHECK: store <2 x double> [[REG1051]], <2 x double>* [[REG1053:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: store <2 x double> [[REG1052]], <2 x double>* [[REG1054:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG1055:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG1053]], align 16
 // CHECK-NEXT: [[REG1056:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG1055]], i32 0
-// CHECK-NEXT: [[REG1057:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG1056]])
+// CHECK-NEXT: [[REG1057A:[0-9a-zA-Z_%.]+]] = insertelement <2 x double> undef, double [[REG1056]], i32 0
+// CHECK-NEXT: [[REG1057:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x double> [[REG1057A]], <2 x double> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: store <2 x double> [[REG1057]], <2 x double>* [[REG1058:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG1059:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG1054]], align 16
 // CHECK-NEXT: [[REG1060:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG1059]], i32 0
-// CHECK-NEXT: [[REG1061:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG1060]])
+// CHECK-NEXT: [[REG1061A:[0-9a-zA-Z_%.]+]] = insertelement <2 x double> undef, double [[REG1060]], i32 0
+// CHECK-NEXT: [[REG1061:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x double> [[REG1061A]], <2 x double> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: store <2 x double> [[REG1061]], <2 x double>* [[REG1062:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG1063:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG1058]], align 16
 // CHECK-NEXT: [[REG1064:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG1062]], align 16
 // CHECK-NEXT: [[REG1065:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_max(double vector[2], double vector[2])(<2 x double> [[REG1063]], <2 x double> [[REG1064]])
 // CHECK-NEXT: store <2 x double> [[REG1065]], <2 x double>* [[REG1066:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG1067:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG1066]], align 16
 // CHECK-NEXT: [[REG1068:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG1067]], i32 0
 // CHECK-NEXT: [[REG1069:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG1053]], align 16

 // CHECK: [[REG1076:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_min(double vector[2], double vector[2])
 // CHECK-NEXT: ret <2 x double> [[REG1076]]
 
 // CHECK: define available_externally <2 x double> @_mm_min_sd(<2 x double> [[REG1077:[0-9a-zA-Z_%.]+]], <2 x double> [[REG1078:[0-9a-zA-Z_%.]+]])
 // CHECK: store <2 x double> [[REG1077]], <2 x double>* [[REG1079:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: store <2 x double> [[REG1078]], <2 x double>* [[REG1080:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG1081:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG1079]], align 16
 // CHECK-NEXT: [[REG1082:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG1081]], i32 0
-// CHECK-NEXT: [[REG1083:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG1082]])
+// CHECK-NEXT: [[REG1083A:[0-9a-zA-Z_%.]+]] = insertelement <2 x double> undef, double [[REG1082]], i32 0
+// CHECK-NEXT: [[REG1083:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x double> [[REG1083A]], <2 x double> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: store <2 x double> [[REG1083]], <2 x double>* [[REG1084:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG1085:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG1080]], align 16
 // CHECK-NEXT: [[REG1086:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG1085]], i32 0
-// CHECK-NEXT: [[REG1087:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG1086]])
+// CHECK-NEXT: [[REG1087A:[0-9a-zA-Z_%.]+]] = insertelement <2 x double> undef, double [[REG1086]], i32 0
+// CHECK-NEXT: [[REG1087:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x double> [[REG1087A]], <2 x double> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: store <2 x double> [[REG1087]], <2 x double>* [[REG1088:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG1089:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG1084]], align 16
 // CHECK-NEXT: [[REG1090:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG1088]], align 16
 // CHECK-NEXT: [[REG1091:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_min(double vector[2], double vector[2])(<2 x double> [[REG1089]], <2 x double> [[REG1090]])
 // CHECK-NEXT: store <2 x double> [[REG1091]], <2 x double>* [[REG1092:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG1093:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG1092]], align 16
 // CHECK-NEXT: [[REG1094:[0-9a-zA-Z_%.]+]] = extractelement <2 x double> [[REG1093]], i32 0
 // CHECK-NEXT: [[REG1095:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG1079]], align 16

 // CHECK-NEXT: [[REG1365:[0-9a-zA-Z_%.]+]] = insertelement <2 x double> undef, double [[REG1364]], i32 0
 // CHECK-NEXT: [[REG1366:[0-9a-zA-Z_%.]+]] = load double, double* [[REG1363]], align 8
 // CHECK-NEXT: [[REG1367:[0-9a-zA-Z_%.]+]] = insertelement <2 x double> [[REG1365]], double [[REG1366]], i32 1
 // CHECK-NEXT: store <2 x double> [[REG1367]], <2 x double>* [[REG1368:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG1369:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG1368]], align 16
 // CHECK-NEXT: ret <2 x double> [[REG1369]]
 
 // CHECK: define available_externally <2 x double> @_mm_setzero_pd()
-// CHECK: [[REG1370:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splats(int)(i32 signext 0)
-// CHECK-NEXT: [[REG1371:[0-9a-zA-Z_%.]+]] = bitcast <4 x i32> [[REG1370]] to <2 x double>
-// CHECK-NEXT: ret <2 x double> [[REG1371]]
+// CHECK: ret <2 x double> zeroinitializer
 
 // CHECK: define available_externally <2 x i64> @_mm_setzero_si128()
 // CHECK: store <4 x i32> zeroinitializer, <4 x i32>* [[REG1372:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG1373:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG1372]], align 16
 // CHECK-NEXT: [[REG1374:[0-9a-zA-Z_%.]+]] = bitcast <4 x i32> [[REG1373]] to <2 x i64>
 // CHECK-NEXT: ret <2 x i64> [[REG1374]]
 
 void __attribute__((noinline))

 // CHECK-NEXT: [[REG1564:[0-9a-zA-Z_%.]+]] = trunc i32 [[REG1563]] to i8
 // CHECK-NEXT: [[REG1565:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_splat_s16(signed char)(i8 signext [[REG1564]])
 // CHECK-NEXT: store <8 x i16> [[REG1565]], <8 x i16>* [[REG1566:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: br label %[[REG1567:[0-9a-zA-Z_%.]+]]
 
 // CHECK: [[REG1562]]:
 // CHECK-NEXT: [[REG1568:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG1552]], align 4
 // CHECK-NEXT: [[REG1569:[0-9a-zA-Z_%.]+]] = trunc i32 [[REG1568]] to i16
-// CHECK-NEXT: [[REG1570:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_splats(unsigned short)(i16 zeroext [[REG1569]])
+// CHECK-NEXT: [[REG1570A:[0-9a-zA-Z_%.]+]] = insertelement <8 x i16> undef, i16 [[REG1569]], i32 0
+// CHECK-NEXT: [[REG1570:[0-9a-zA-Z_%.]+]]  = shufflevector <8 x i16> [[REG1570A]], <8 x i16> undef, <8 x i32> zeroinitializer
 // CHECK-NEXT: store <8 x i16> [[REG1570]], <8 x i16>* [[REG1566]], align 16
 // CHECK-NEXT: br label %[[REG1567:[0-9a-zA-Z_%.]+]]
 
 // CHECK: [[REG1567]]:
 // CHECK-NEXT: [[REG1571:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1551]], align 16
 // CHECK-NEXT: [[REG1572:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG1571]] to <8 x i16>
 // CHECK-NEXT: [[REG1573:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG1566]], align 16
 // CHECK-NEXT: [[REG1574:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_sl(short vector[8], unsigned short vector[8])(<8 x i16> [[REG1572]], <8 x i16> [[REG1573]])

 // CHECK-NEXT: [[REG1594:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG1580]], align 4
 // CHECK-NEXT: [[REG1595:[0-9a-zA-Z_%.]+]] = trunc i32 [[REG1594]] to i8
 // CHECK-NEXT: [[REG1596:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splat_s32(signed char)(i8 signext [[REG1595]])
 // CHECK-NEXT: store <4 x i32> [[REG1596]], <4 x i32>* [[REG1597:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: br label %[[REG1598:[0-9a-zA-Z_%.]+]]
 
 // CHECK: [[REG1590]]:
 // CHECK-NEXT: [[REG1599:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG1580]], align 4
-// CHECK-NEXT: [[REG1600:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splats(unsigned int)(i32 zeroext [[REG1599]])
+// CHECK-NEXT: [[REG1600A:[0-9a-zA-Z_%.]+]] = insertelement <4 x i32> undef, i32 [[REG1599]], i32 0
+// CHECK-NEXT: [[REG1600:[0-9a-zA-Z_%.]+]]  = shufflevector <4 x i32> [[REG1600A]], <4 x i32> undef, <4 x i32> zeroinitializer
 // CHECK-NEXT: store <4 x i32> [[REG1600]], <4 x i32>* [[REG1597]], align 16
 // CHECK-NEXT: br label %[[REG1598:[0-9a-zA-Z_%.]+]]
 
 // CHECK: [[REG1598]]:
 // CHECK-NEXT: [[REG1601:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1579]], align 16
 // CHECK-NEXT: [[REG1602:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG1601]] to <4 x i32>
 // CHECK-NEXT: [[REG1603:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG1597]], align 16
 // CHECK-NEXT: [[REG1604:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sl(int vector[4], unsigned int vector[4])(<4 x i32> [[REG1602]], <4 x i32> [[REG1603]])

 // CHECK-NEXT: [[REG1625:[0-9a-zA-Z_%.]+]] = trunc i32 [[REG1624]] to i8
 // CHECK-NEXT: [[REG1626:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splat_s32(signed char)(i8 signext [[REG1625]])
 // CHECK-NEXT: [[REG1627:[0-9a-zA-Z_%.]+]] = bitcast <4 x i32> [[REG1626]] to <2 x i64>
 // CHECK-NEXT: store <2 x i64> [[REG1627]], <2 x i64>* [[REG1628:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: br label %[[REG1629:[0-9a-zA-Z_%.]+]]
 
 // CHECK: [[REG1620]]:
 // CHECK-NEXT: [[REG1630:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG1610]], align 4
-// CHECK-NEXT: [[REG1631:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splats(unsigned int)(i32 zeroext [[REG1630]])
+// CHECK-NEXT: [[REG1631A:[0-9a-zA-Z_%.]+]] = insertelement <4 x i32> undef, i32 [[REG1630]], i32 0
+// CHECK-NEXT: [[REG1631:[0-9a-zA-Z_%.]+]]  = shufflevector <4 x i32> [[REG1631A]], <4 x i32> undef, <4 x i32> zeroinitializer
 // CHECK-NEXT: [[REG1632:[0-9a-zA-Z_%.]+]] = bitcast <4 x i32> [[REG1631]] to <2 x i64>
 // CHECK-NEXT: store <2 x i64> [[REG1632]], <2 x i64>* [[REG1628]], align 16
 // CHECK-NEXT: br label %[[REG1629:[0-9a-zA-Z_%.]+]]
 
 // CHECK: [[REG1629]]:
 // CHECK-NEXT: [[REG1633:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1609]], align 16
 // CHECK-NEXT: [[REG1634:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1628]], align 16
 // CHECK-NEXT: [[REG1635:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_sl(long long vector[2], unsigned long long vector[2])(<2 x i64> [[REG1633]], <2 x i64> [[REG1634]])

 // CHECK-NEXT: [[REG1718:[0-9a-zA-Z_%.]+]] = trunc i32 [[REG1717]] to i8
 // CHECK-NEXT: [[REG1719:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_splat_s16(signed char)(i8 signext [[REG1718]])
 // CHECK-NEXT: store <8 x i16> [[REG1719]], <8 x i16>* [[REG1710]], align 16
 // CHECK-NEXT: br label %[[REG1720:[0-9a-zA-Z_%.]+]]
 
 // CHECK: [[REG1716]]:
 // CHECK-NEXT: [[REG1721:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG1709]], align 4
 // CHECK-NEXT: [[REG1722:[0-9a-zA-Z_%.]+]] = trunc i32 [[REG1721]] to i16
-// CHECK-NEXT: [[REG1723:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_splats(unsigned short)(i16 zeroext [[REG1722]])
+// CHECK-NEXT: [[REG1723A:[0-9a-zA-Z_%.]+]] = insertelement <8 x i16> undef, i16 [[REG1722]], i32 0
+// CHECK-NEXT: [[REG1723:[0-9a-zA-Z_%.]+]]  = shufflevector <8 x i16> [[REG1723A]], <8 x i16> undef, <8 x i32> zeroinitializer
 // CHECK-NEXT: store <8 x i16> [[REG1723]], <8 x i16>* [[REG1710]], align 16
 // CHECK-NEXT: br label %[[REG1720:[0-9a-zA-Z_%.]+]]
 
 // CHECK: [[REG1720]]:
 // CHECK-NEXT: br label %[[REG1714:[0-9a-zA-Z_%.]+]]
 
 // CHECK: [[REG1714]]:
 // CHECK-NEXT: [[REG1724:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1708]], align 16

 // CHECK-NEXT: [[REG1746:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG1734]], align 4
 // CHECK-NEXT: [[REG1747:[0-9a-zA-Z_%.]+]] = trunc i32 [[REG1746]] to i8
 // CHECK-NEXT: [[REG1748:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splat_s32(signed char)(i8 signext [[REG1747]])
 // CHECK-NEXT: store <4 x i32> [[REG1748]], <4 x i32>* [[REG1735]], align 16
 // CHECK-NEXT: br label %[[REG1749:[0-9a-zA-Z_%.]+]]
 
 // CHECK: [[REG1745]]:
 // CHECK-NEXT: [[REG1750:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG1734]], align 4
-// CHECK-NEXT: [[REG1751:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splats(unsigned int)(i32 zeroext [[REG1750]])
+// CHECK-NEXT: [[REG1751A:[0-9a-zA-Z_%.]+]] = insertelement <4 x i32> undef, i32 [[REG1750]], i32 0
+// CHECK-NEXT: [[REG1751:[0-9a-zA-Z_%.]+]]  = shufflevector <4 x i32> [[REG1751A]], <4 x i32> undef, <4 x i32> zeroinitializer
 // CHECK-NEXT: store <4 x i32> [[REG1751]], <4 x i32>* [[REG1735]], align 16
 // CHECK-NEXT: br label %[[REG1749:[0-9a-zA-Z_%.]+]]
 
 // CHECK: [[REG1749]]:
 // CHECK-NEXT: br label %[[REG1752:[0-9a-zA-Z_%.]+]]
 
 // CHECK: [[REG1741]]:
 // CHECK-NEXT: [[REG1753:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG1734]], align 4
-// CHECK-NEXT: [[REG1754:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splats(unsigned int)(i32 zeroext [[REG1753]])
+// CHECK-NEXT: [[REG1754A:[0-9a-zA-Z_%.]+]] = insertelement <4 x i32> undef, i32 [[REG1753]], i32 0
+// CHECK-NEXT: [[REG1754:[0-9a-zA-Z_%.]+]]  = shufflevector <4 x i32> [[REG1754A]], <4 x i32> undef, <4 x i32> zeroinitializer
 // CHECK-NEXT: store <4 x i32> [[REG1754]], <4 x i32>* [[REG1735]], align 16
 // CHECK-NEXT: br label %[[REG1752:[0-9a-zA-Z_%.]+]]
 
 // CHECK: [[REG1752]]:
 // CHECK-NEXT: br label %[[REG1739:[0-9a-zA-Z_%.]+]]
 
 // CHECK: [[REG1739]]:
 // CHECK-NEXT: [[REG1755:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1733]], align 16

 // CHECK-NEXT: [[REG1842:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG1834]], align 4
 // CHECK-NEXT: [[REG1843:[0-9a-zA-Z_%.]+]] = trunc i32 [[REG1842]] to i8
 // CHECK-NEXT: [[REG1844:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_splat_s16(signed char)(i8 signext [[REG1843]])
 // CHECK-NEXT: store <8 x i16> [[REG1844]], <8 x i16>* [[REG1845:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: br label %[[REG1846:[0-9a-zA-Z_%.]+]]
 // CHECK: [[REG1841]]:
 // CHECK-NEXT: [[REG1847:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG1834]], align 4
 // CHECK-NEXT: [[REG1848:[0-9a-zA-Z_%.]+]] = trunc i32 [[REG1847]] to i16
-// CHECK-NEXT: [[REG1849:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_splats(unsigned short)(i16 zeroext [[REG1848]])
+// CHECK-NEXT: [[REG1849A:[0-9a-zA-Z_%.]+]] = insertelement <8 x i16> undef, i16 [[REG1848]], i32 0
+// CHECK-NEXT: [[REG1849:[0-9a-zA-Z_%.]+]]  = shufflevector <8 x i16> [[REG1849A]], <8 x i16> undef, <8 x i32> zeroinitializer
 // CHECK-NEXT: store <8 x i16> [[REG1849]], <8 x i16>* [[REG1845]], align 16
 // CHECK-NEXT: br label %[[REG1846:[0-9a-zA-Z_%.]+]]
 // CHECK: [[REG1846]]:
 // CHECK-NEXT: [[REG1850:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1833]], align 16
 // CHECK-NEXT: [[REG1851:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG1850]] to <8 x i16>
 // CHECK-NEXT: [[REG1852:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG1845]], align 16
 // CHECK-NEXT: [[REG1853:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_sr(short vector[8], unsigned short vector[8])(<8 x i16> [[REG1851]], <8 x i16> [[REG1852]])
 // CHECK-NEXT: store <8 x i16> [[REG1853]], <8 x i16>* [[REG1835]], align 16

 // CHECK-NEXT: [[REG1871:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG1859]], align 4
 // CHECK-NEXT: [[REG1872:[0-9a-zA-Z_%.]+]] = trunc i32 [[REG1871]] to i8
 // CHECK-NEXT: [[REG1873:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splat_s32(signed char)(i8 signext [[REG1872]])
 // CHECK-NEXT: store <4 x i32> [[REG1873]], <4 x i32>* [[REG1874:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: br label %[[REG1875:[0-9a-zA-Z_%.]+]]
 
 // CHECK: [[REG1870]]:
 // CHECK-NEXT: [[REG1876:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG1859]], align 4
-// CHECK-NEXT: [[REG1877:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splats(unsigned int)(i32 zeroext [[REG1876]])
+// CHECK-NEXT: [[REG1877A:[0-9a-zA-Z_%.]+]] = insertelement <4 x i32> undef, i32 [[REG1876]], i32 0
+// CHECK-NEXT: [[REG1877:[0-9a-zA-Z_%.]+]]  = shufflevector <4 x i32> [[REG1877A]], <4 x i32> undef, <4 x i32> zeroinitializer
 // CHECK-NEXT: store <4 x i32> [[REG1877]], <4 x i32>* [[REG1874]], align 16
 // CHECK-NEXT: br label %[[REG1875:[0-9a-zA-Z_%.]+]]
 
 // CHECK: [[REG1875]]:
 // CHECK-NEXT: br label %[[REG1878:[0-9a-zA-Z_%.]+]]
 
 // CHECK: [[REG1866]]:
 // CHECK-NEXT: [[REG1879:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG1859]], align 4
-// CHECK-NEXT: [[REG1880:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splats(unsigned int)(i32 zeroext [[REG1879]])
+// CHECK-NEXT: [[REG1880A:[0-9a-zA-Z_%.]+]] = insertelement <4 x i32> undef, i32 [[REG1879]], i32 0
+// CHECK-NEXT: [[REG1880:[0-9a-zA-Z_%.]+]]  = shufflevector <4 x i32> [[REG1880A]], <4 x i32> undef, <4 x i32> zeroinitializer
 // CHECK-NEXT: store <4 x i32> [[REG1880]], <4 x i32>* [[REG1874]], align 16
 // CHECK-NEXT: br label %[[REG1878:[0-9a-zA-Z_%.]+]]
 
 // CHECK: [[REG1878]]:
 // CHECK-NEXT: [[REG1881:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1858]], align 16
 // CHECK-NEXT: [[REG1882:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG1881]] to <4 x i32>
 // CHECK-NEXT: [[REG1883:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG1874]], align 16
 // CHECK-NEXT: [[REG1884:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sr(int vector[4], unsigned int vector[4])(<4 x i32> [[REG1882]], <4 x i32> [[REG1883]])

 // CHECK-NEXT: [[REG1904:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splat_s32(signed char)(i8 signext [[REG1903]])
 // CHECK-NEXT: [[REG1905:[0-9a-zA-Z_%.]+]] = bitcast <4 x i32> [[REG1904]] to <2 x i64>
 // CHECK-NEXT: store <2 x i64> [[REG1905]], <2 x i64>* [[REG1906:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: br label %[[REG1907:[0-9a-zA-Z_%.]+]]
 
 // CHECK: [[REG1901]]:
 // CHECK-NEXT: [[REG1908:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG1890]], align 4
 // CHECK-NEXT: [[REG1909:[0-9a-zA-Z_%.]+]] = sext i32 [[REG1908]] to i64
-// CHECK-NEXT: [[REG1910:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 [[REG1909]])
+// CHECK-NEXT: [[REG1910A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 [[REG1909]], i32 0
+// CHECK-NEXT: [[REG1910:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG1910A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: store <2 x i64> [[REG1910]], <2 x i64>* [[REG1906]], align 16
 // CHECK-NEXT: br label %[[REG1907:[0-9a-zA-Z_%.]+]]
 
 // CHECK: [[REG1907]]:
 // CHECK-NEXT: br label %[[REG1911:[0-9a-zA-Z_%.]+]]
 
 // CHECK: [[REG1897]]:
 // CHECK-NEXT: [[REG1912:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG1890]], align 4
-// CHECK-NEXT: [[REG1913:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splats(unsigned int)(i32 zeroext [[REG1912]])
+// CHECK-NEXT: [[REG1913A:[0-9a-zA-Z_%.]+]] = insertelement <4 x i32> undef, i32 [[REG1912]], i32 0
+// CHECK-NEXT: [[REG1913:[0-9a-zA-Z_%.]+]]  = shufflevector <4 x i32> [[REG1913A]], <4 x i32> undef, <4 x i32> zeroinitializer
 // CHECK-NEXT: [[REG1914:[0-9a-zA-Z_%.]+]] = bitcast <4 x i32> [[REG1913]] to <2 x i64>
 // CHECK-NEXT: store <2 x i64> [[REG1914]], <2 x i64>* [[REG1906]], align 16
 // CHECK-NEXT: br label %[[REG1911:[0-9a-zA-Z_%.]+]]
 
 // CHECK: [[REG1911]]:
 // CHECK-NEXT: [[REG1915:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1889]], align 16
 // CHECK-NEXT: [[REG1916:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG1906]], align 16
 // CHECK-NEXT: [[REG1917:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_sr(long long vector[2], unsigned long long vector[2])(<2 x i64> [[REG1915]], <2 x i64> [[REG1916]])

clang/test/CodeGen/ppc-mmintrin.c

-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // REQUIRES: powerpc-registered-target
 
 // RUN: %clang -S -emit-llvm -target powerpc64-unknown-linux-gnu -mcpu=pwr8 -DNO_WARN_X86_INTRINSICS %s \
 // RUN:   -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK-P8,CHECK,CHECK-BE
 // RUN: %clang -S -emit-llvm -target powerpc64le-unknown-linux-gnu -mcpu=pwr8 -DNO_WARN_X86_INTRINSICS %s \
 // RUN:   -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK-P8,CHECK,CHECK-LE
 // RUN: %clang -S -emit-llvm -target powerpc64-unknown-linux-gnu -mcpu=pwr9 -DNO_WARN_X86_INTRINSICS %s \
 // RUN:   -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK-P9,CHECK,CHECK-BE
test_add() {
   res = _mm_adds_pi16(m1, m2);
   res = _mm_adds_pi8(m1, m2);
 }
 
 // CHECK-LABEL: @test_add
 
 // CHECK: define available_externally i64 @_mm_add_pi32
 
-// CHECK-P9: [[REG1:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)
+// CHECK-P9: [[REG1A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0
+// CHECK-P9-NEXT: [[REG1:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG1A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-P9-NEXT: [[REG2:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG1]] to <4 x i32>
 // CHECK-P9-NEXT: store <4 x i32> [[REG2]], <4 x i32>* [[REG3:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-P9-NEXT: [[REG4:[0-9a-zA-Z_%.]+]] = load i64, i64* {{[0-9a-zA-Z_%.]+}}, align 8
-// CHECK-P9-NEXT: [[REG5:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)
+// CHECK-P9-NEXT: [[REG5A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0
+// CHECK-P9-NEXT: [[REG5:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG5A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-P9-NEXT: [[REG6:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG5]] to <4 x i32>
 // CHECK-P9-NEXT: store <4 x i32> [[REG6]], <4 x i32>* [[REG7:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-P9-NEXT: [[REG8:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG3]], align 16
 // CHECK-P9-NEXT: [[REG9:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG7]], align 16
 // CHECK-P9-NEXT: [[REG10:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_add(int vector[4], int vector[4])(<4 x i32> [[REG8]], <4 x i32> [[REG9]])
 // CHECK-P9-NEXT: store <4 x i32> [[REG10]], <4 x i32>* [[REG11:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-P9-NEXT: [[REG12:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG11]], align 16
 // CHECK-P9-NEXT: [[REG13:[0-9a-zA-Z_%.]+]] = bitcast <4 x i32> %6 to <2 x i64>
 // CHECK-P9-NEXT: [[REG14:[0-9a-zA-Z_%.]+]] = extractelement <2 x i64> [[REG13]], i32 0
 // CHECK-P9-NEXT: ret i64 [[REG14]]
 
 // CHECK-P8: [[REG15:[0-9a-zA-Z_%.]+]] = getelementptr inbounds [2 x i32], [2 x i32]* {{[0-9a-zA-Z_%.]+}}, i64 0, i64 0
 // CHECK-P8-NEXT: [[REG16:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG15]]
 // CHECK-P8: [[REG17:[0-9a-zA-Z_%.]+]] = getelementptr inbounds [2 x i32], [2 x i32]* {{[0-9a-zA-Z_%.]+}}, i64 0, i64 0
 // CHECK-P8-NEXT: [[REG18:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG17]]
 // CHECK-P8-NEXT: add nsw i32 [[REG16]], [[REG18]]
 // CHECK-P8: [[REG19:[0-9a-zA-Z_%.]+]] = getelementptr inbounds [2 x i32], [2 x i32]* {{[0-9a-zA-Z_%.]+}}, i64 0, i64 1
 // CHECK-P8-NEXT: [[REG20:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG19]]
 // CHECK-P8: [[REG21:[0-9a-zA-Z_%.]+]] = getelementptr inbounds [2 x i32], [2 x i32]* {{[0-9a-zA-Z_%.]+}}, i64 0, i64 1
 // CHECK-P8-NEXT: [[REG22:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG21]]
 // CHECK-P8-NEXT: add nsw i32 [[REG20]], [[REG22]]
 
 // CHECK: define available_externally i64 @_mm_add_pi16
-// CHECK: [[REG23:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats
+// CHECK: [[REG23A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0
+// CHECK-NEXT: [[REG23:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG23A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG24:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG23]] to <8 x i16>
 // CHECK-NEXT: store <8 x i16> [[REG24]], <8 x i16>* [[REG25:[0-9a-zA-Z_%.]+]]
-// CHECK: [[REG26:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats
+// CHECK: [[REG26A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0
+// CHECK-NEXT: [[REG26:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG26A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG27:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG26]] to <8 x i16>
 // CHECK-NEXT: store <8 x i16> [[REG27]], <8 x i16>* [[REG28:[0-9a-zA-Z_%.]+]]
 // CHECK-NEXT: [[REG29:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG25]], align 16
 // CHECK-NEXT: [[REG30:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG28]], align 16
 // CHECK-NEXT: call <8 x i16> @vec_add(short vector[8], short vector[8])(<8 x i16> [[REG29]], <8 x i16> [[REG30]])
 
 // CHECK: define available_externally i64 @_mm_add_pi8
-// CHECK: [[REG31:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats
+// CHECK: [[REG31A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0
+// CHECK-NEXT: [[REG31:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG31A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG32:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG31]] to <16 x i8>
 // CHECK-NEXT: store <16 x i8> [[REG32]], <16 x i8>* [[REG33:[0-9a-zA-Z_%.]+]]
-// CHECK: [[REG34:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats
+// CHECK: [[REG34A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0
+// CHECK-NEXT: [[REG34:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG34A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG35:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG34]] to <16 x i8>
 // CHECK-NEXT: store <16 x i8> [[REG35]], <16 x i8>* [[REG36:[0-9a-zA-Z_%.]+]]
 // CHECK-NEXT: [[REG37:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG33]], align 16
 // CHECK-NEXT: [[REG38:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG36]], align 16
 // CHECK-NEXT: call <16 x i8> @vec_add(signed char vector[16], signed char vector[16])(<16 x i8> [[REG37]], <16 x i8> [[REG38]])
 
 // CHECK: define available_externally i64 @_mm_adds_pu16
-// CHECK: [[REG39:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats
+// CHECK: [[REG39A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0
+// CHECK-NEXT: [[REG39:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG39A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG40:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG39]] to <8 x i16>
 // CHECK-NEXT: store <8 x i16> [[REG40]], <8 x i16>* [[REG41:[0-9a-zA-Z_%.]+]]
-// CHECK: [[REG42:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats
+// CHECK: [[REG42A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0
+// CHECK-NEXT: [[REG42:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG42A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG43:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG42]] to <8 x i16>
 // CHECK-NEXT: store <8 x i16> [[REG43]], <8 x i16>* [[REG44:[0-9a-zA-Z_%.]+]]
 // CHECK-NEXT: [[REG45:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG41]], align 16
 // CHECK-NEXT: [[REG46:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG44]], align 16
 // CHECK-NEXT: call <8 x i16> @vec_adds(unsigned short vector[8], unsigned short vector[8])(<8 x i16> [[REG45]], <8 x i16> [[REG46]])
 
 // CHECK: define available_externally i64 @_mm_adds_pu8
-// CHECK: [[REG47:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats
+// CHECK: [[REG47A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0
+// CHECK-NEXT: [[REG47:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG47A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG48:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG47]] to <16 x i8>
 // CHECK-NEXT: store <16 x i8> [[REG48]], <16 x i8>* [[REG49:[0-9a-zA-Z_%.]+]]
-// CHECK: [[REG50:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats
+// CHECK: [[REG50A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0
+// CHECK-NEXT: [[REG50:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG50A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG51:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG50]] to <16 x i8>
 // CHECK-NEXT: store <16 x i8> [[REG51]], <16 x i8>* [[REG52:[0-9a-zA-Z_%.]+]]
 // CHECK-NEXT: [[REG53:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG49]], align 16
 // CHECK-NEXT: [[REG54:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG52]], align 16
 // CHECK-NEXT: call <16 x i8> @vec_adds(unsigned char vector[16], unsigned char vector[16])(<16 x i8> [[REG53]], <16 x i8> [[REG54]])
 
 // CHECK: define available_externally i64 @_mm_adds_pi16
-// CHECK: [[REG55:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats
+// CHECK: [[REG55A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0
+// CHECK-NEXT: [[REG55:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG55A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG56:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG55]] to <8 x i16>
 // CHECK-NEXT: store <8 x i16> [[REG56]], <8 x i16>* [[REG57:[0-9a-zA-Z_%.]+]]
-// CHECK: [[REG58:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats
+// CHECK: [[REG58A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0
+// CHECK-NEXT: [[REG58:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG58A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG59:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG58]] to <8 x i16>
 // CHECK-NEXT: store <8 x i16> [[REG59]], <8 x i16>* [[REG60:[0-9a-zA-Z_%.]+]]
 // CHECK-NEXT: [[REG61:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG57]], align 16
 // CHECK-NEXT: [[REG62:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG60]], align 16
 // CHECK-NEXT: call <8 x i16> @vec_adds(short vector[8], short vector[8])(<8 x i16> [[REG61]], <8 x i16> [[REG62]])
 
 // CHECK: define available_externally i64 @_mm_adds_pi8
-// CHECK: [[REG63:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats
+// CHECK: [[REG63A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0
+// CHECK-NEXT: [[REG63:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG63A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG64:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG63]] to <16 x i8>
 // CHECK-NEXT: store <16 x i8> [[REG64]], <16 x i8>* [[REG65:[0-9a-zA-Z_%.]+]]
-// CHECK: [[REG66:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats
+// CHECK: [[REG66A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0
+// CHECK-NEXT: [[REG66:[0-9a-zA-Z_%.]+]] = shufflevector <2 x i64> [[REG66A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG67:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG66]] to <16 x i8>
 // CHECK-NEXT: store <16 x i8> [[REG67]], <16 x i8>* [[REG68:[0-9a-zA-Z_%.]+]]
 // CHECK-NEXT: [[REG69:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG65]], align 16
 // CHECK-NEXT: [[REG70:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG68]], align 16
 // CHECK-NEXT: call <16 x i8> @vec_adds(signed char vector[16], signed char vector[16])(<16 x i8> [[REG69]], <16 x i8> [[REG70]])
 
 void __attribute__((noinline))
 test_alt_name_add() {
test_cmp() {
   res = _mm_cmpgt_pi16(m1, m2);
   res = _mm_cmpgt_pi8(m1, m2);
 }
 
 // CHECK-LABEL: @test_cmp
 
 // CHECK: define available_externally i64 @_mm_cmpeq_pi32
 
-// CHECK-P9: [[REG78:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)
+// CHECK-P9: [[REG78A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0
+// CHECK-P9-NEXT: [[REG78:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG78A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-P9-NEXT: [[REG79:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG78]] to <4 x i32>
 // CHECK-P9-NEXT: store <4 x i32> [[REG79]], <4 x i32>* [[REG80:[0-9a-zA-Z_%.]+]]
-// CHECK-P9: [[REG81:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)
+// CHECK-P9: [[REG81A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0
+// CHECK-P9-NEXT: [[REG81:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG81A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-P9-NEXT: [[REG82:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG81]] to <4 x i32>
 // CHECK-P9-NEXT: store <4 x i32> [[REG82]], <4 x i32>* [[REG83:[0-9a-zA-Z_%.]+]]
 // CHECK-P9-NEXT: [[REG84:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG80]]
 // CHECK-P9-NEXT: [[REG85:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG83]]
 // CHECK-P9-NEXT: call <4 x i32> @vec_cmpeq(int vector[4], int vector[4])(<4 x i32> [[REG84]], <4 x i32> [[REG85]])
 
 // CHECK-P8-COUNT-2: {{[0-9a-zA-Z_%.]+}} = getelementptr inbounds [2 x i32], [2 x i32]* {{[0-9a-zA-Z_%.]+}}
 // CHECK-P8: [[REG86:[0-9a-zA-Z_%.]+]] = icmp eq i32 {{[0-9a-zA-Z_%.]+}}, {{[0-9a-zA-Z_%.]+}}
 // CHECK-P8: [[REG87:[0-9a-zA-Z_%.]+]] = select i1 [[REG86]], i32 -1, i32 0
 // CHECK-P8: {{[0-9a-zA-Z_%.]+}} = getelementptr inbounds [2 x i32], [2 x i32]* {{[0-9a-zA-Z_%.]+}}
 // CHECK-P8-NEXT: store i32 [[REG87]], i32* {{[0-9a-zA-Z_%.]+}}
 // CHECK-P8-COUNT-2: {{[0-9a-zA-Z_%.]+}} = getelementptr inbounds [2 x i32], [2 x i32]* {{[0-9a-zA-Z_%.]+}}
 // CHECK-P8: store i32 {{[0-9a-zA-Z_%.]+}}, i32* {{[0-9a-zA-Z_%.]+}}
 
 // CHECK: define available_externally i64 @_mm_cmpeq_pi16
-// CHECK: [[REG88:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)
+// CHECK: [[REG88A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0
+// CHECK-NEXT: [[REG88:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG88A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG89:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG88]] to <8 x i16>
 // CHECK-NEXT: store <8 x i16> [[REG89]], <8 x i16>* [[REG90:[0-9a-zA-Z_%.]+]]
-// CHECK: [[REG91:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)
+// CHECK: [[REG91A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0
+// CHECK-NEXT: [[REG91:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG91A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG92:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG91]] to <8 x i16>
 // CHECK-NEXT: store <8 x i16> [[REG92]], <8 x i16>* [[REG93:[0-9a-zA-Z_%.]+]]
 // CHECK-NEXT: [[REG94:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG90]], align 16
 // CHECK-NEXT: [[REG95:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG93]], align 16
 // CHECK-NEXT: call <8 x i16> @vec_cmpeq(short vector[8], short vector[8])(<8 x i16> [[REG94]], <8 x i16> [[REG95]])
 
 // CHECK: define available_externally i64 @_mm_cmpeq_pi8
 // CHECK: call i64 asm "cmpb $0,$1,$2;\0A", "=r,r,r"
 // CHECK-NEXT: store i64 {{[0-9a-zA-Z_%.]+}}, i64* [[REG96:[0-9a-zA-Z_%.]+]], align 8
 // CHECK-NEXT: [[REG97:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG96]], align 8
 // CHECK-NEXT: ret i64 [[REG97]]
 
 // CHECK: define available_externally i64 @_mm_cmpgt_pi32
 
-// CHECK-P9: [[REG98:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)
+// CHECK-P9: [[REG98A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0
+// CHECK-P9-NEXT: [[REG98:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG98A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-P9-NEXT: [[REG99:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG98]] to <4 x i32>
 // CHECK-P9-NEXT: store <4 x i32> [[REG99]], <4 x i32>* [[REG100:[0-9a-zA-Z_%.]+]]
-// CHECK-P9: [[REG101:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)
+// CHECK-P9: [[REG101A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0
+// CHECK-P9-NEXT: [[REG101:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG101A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-P9-NEXT: [[REG102:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG101]] to <4 x i32>
 // CHECK-P9-NEXT: store <4 x i32> [[REG102]], <4 x i32>* [[REG103:[0-9a-zA-Z_%.]+]]
 // CHECK-P9-NEXT: [[REG104:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG100]]
 // CHECK-P9-NEXT: [[REG105:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG103]]
 // CHECK-P9-NEXT: call <4 x i32> @vec_cmpgt(int vector[4], int vector[4])(<4 x i32> [[REG104]], <4 x i32> [[REG85]])
 
 // CHECK-P8-COUNT-2: {{[0-9a-zA-Z_%.]+}} = getelementptr inbounds [2 x i32], [2 x i32]* {{[0-9a-zA-Z_%.]+}}
 // CHECK-P8: [[REG106:[0-9a-zA-Z_%.]+]] = icmp sgt i32 {{[0-9a-zA-Z_%.]+}}, {{[0-9a-zA-Z_%.]+}}
 // CHECK-P8: [[REG107:[0-9a-zA-Z_%.]+]] = select i1 [[REG106]], i32 -1, i32 0
 // CHECK-P8: {{[0-9a-zA-Z_%.]+}} = getelementptr inbounds [2 x i32], [2 x i32]* {{[0-9a-zA-Z_%.]+}}
 // CHECK-P8-NEXT: store i32 [[REG107]], i32* {{[0-9a-zA-Z_%.]+}}
 // CHECK-P8-COUNT-2: {{[0-9a-zA-Z_%.]+}} = getelementptr inbounds [2 x i32], [2 x i32]* {{[0-9a-zA-Z_%.]+}}
 // CHECK-P8: store i32 {{[0-9a-zA-Z_%.]+}}, i32* {{[0-9a-zA-Z_%.]+}}
 
 // CHECK: define available_externally i64 @_mm_cmpgt_pi16
-// CHECK: [[REG108:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)
+// CHECK: [[REG108A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0
+// CHECK-NEXT: [[REG108:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG108A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG109:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG108]] to <8 x i16>
 // CHECK-NEXT: store <8 x i16> [[REG109]], <8 x i16>* [[REG110:[0-9a-zA-Z_%.]+]]
-// CHECK: [[REG111:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)
+// CHECK: [[REG111A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0
+// CHECK-NEXT: [[REG111:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG111A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG112:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG111]] to <8 x i16>
 // CHECK-NEXT: store <8 x i16> [[REG112]], <8 x i16>* [[REG113:[0-9a-zA-Z_%.]+]]
 // CHECK-NEXT: [[REG114:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG110]]
 // CHECK-NEXT: [[REG115:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG113]]
 // CHECK-NEXT: call <8 x i16> @vec_cmpgt(short vector[8], short vector[8])(<8 x i16> [[REG114]], <8 x i16> [[REG115]])
 
 // CHECK: define available_externally i64 @_mm_cmpgt_pi8
-// CHECK: [[REG116:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)
+// CHECK: [[REG116A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0
+// CHECK-NEXT: [[REG116:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG116A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG117:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG116]] to <16 x i8>
 // CHECK-NEXT: store <16 x i8> [[REG117]], <16 x i8>* [[REG118:[0-9a-zA-Z_%.]+]]
-// CHECK: [[REG119:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)
+// CHECK: [[REG119A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0
+// CHECK-NEXT: [[REG119:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG119A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG120:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG119]] to <16 x i8>
 // CHECK-NEXT: store <16 x i8> [[REG120]], <16 x i8>* [[REG121:[0-9a-zA-Z_%.]+]]
 // CHECK-NEXT: [[REG122:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG118]]
 // CHECK-NEXT: [[REG123:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG121]]
 // CHECK-NEXT: call <16 x i8> @vec_cmpgt(signed char vector[16], signed char vector[16])(<16 x i8> [[REG122]], <16 x i8> [[REG123]])
 
 void __attribute__((noinline))
 test_alt_name_cmp() {
test_madd() {
   res = _mm_madd_pi16(m1, m2);
   res = _m_pmaddwd(m1, m2);
 }
 
 // CHECK-LABEL: @test_madd
 
 // CHECK: define available_externally i64 @_mm_madd_pi16
 // CHECK: store <4 x i32> zeroinitializer, <4 x i32>* [[REG149:[0-9a-zA-Z_%.]+]], align 16
-// CHECK: [[REG150:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 {{[0-9a-zA-Z_%.]+}})
+// CHECK: [[REG150A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0
+// CHECK-NEXT: [[REG150:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG150A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG151:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG150]] to <8 x i16>
 // CHECK-NEXT: store <8 x i16> [[REG151]], <8 x i16>* [[REG152:[0-9a-zA-Z_%.]+]], align 16
-// CHECK: [[REG153:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 {{[0-9a-zA-Z_%.]+}})
+// CHECK: [[REG153A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0
+// CHECK-NEXT: [[REG153:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG153A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG154:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG153]] to <8 x i16>
 // CHECK-NEXT: store <8 x i16> [[REG154]], <8 x i16>* [[REG155:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG156:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG152]], align 16
 // CHECK-NEXT: [[REG157:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG155]], align 16
 // CHECK-NEXT: [[REG158:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG149]], align 16
 // CHECK-NEXT: [[REG159:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_vmsumshm(<8 x i16> [[REG156]], <8 x i16> [[REG157]], <4 x i32> [[REG158]])
 // CHECK-NEXT: store <4 x i32> [[REG159]], <4 x i32>* {{[0-9a-zA-Z_%.]+}}, align 16
 
 // CHECK: define available_externally i64 @_m_pmaddwd
 // CHECK: [[REG160:[0-9a-zA-Z_%.]+]] = call i64 @_mm_madd_pi16
 // CHECK-NEXT: ret i64 [[REG160]]
 
 void __attribute__((noinline))
 test_mul() {
   res = _mm_mulhi_pi16(m1, m2);
   res = _mm_mullo_pi16(m1, m2);
 }
 
 // CHECK-LABEL: @test_mul
 
 // CHECK: define available_externally i64 @_mm_mulhi_pi16
 // CHECK-BE: store <16 x i8> <i8 0, i8 1, i8 16, i8 17, i8 4, i8 5, i8 20, i8 21, i8 0, i8 1, i8 16, i8 17, i8 4, i8 5, i8 20, i8 21>, <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-LE: store <16 x i8> <i8 2, i8 3, i8 18, i8 19, i8 6, i8 7, i8 22, i8 23, i8 10, i8 11, i8 26, i8 27, i8 14, i8 15, i8 30, i8 31>, <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16
-// CHECK: [[REG161:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)
+// CHECK: [[REG161A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0
+// CHECK-NEXT: [[REG161:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG161A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK: store <8 x i16> {{[0-9a-zA-Z_%.]+}}, <8 x i16>* [[REG162:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG163:[0-9a-zA-Z_%.]+]] = load i64, i64* {{[0-9a-zA-Z_%.]+}}, align 8
-// CHECK-NEXT: [[REG164:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)
+// CHECK-NEXT: [[REG164A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0
+// CHECK-NEXT: [[REG164:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG164A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG165:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG164]] to <8 x i16>
 // CHECK-NEXT: store <8 x i16> [[REG165]], <8 x i16>* [[REG166:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG167:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG162]], align 16
 // CHECK-NEXT: [[REG168:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG166]], align 16
 // CHECK-NEXT: [[REG169:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_vmulesh(<8 x i16> [[REG167]], <8 x i16> [[REG168]])
 // CHECK-NEXT: store <4 x i32> [[REG169]], <4 x i32>* [[REG170:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG171:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG162]], align 16
 // CHECK-NEXT: [[REG172:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG166]], align 16
 // CHECK-NEXT: [[REG173:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_vmulosh(<8 x i16> [[REG171]], <8 x i16> [[REG172]])
 // CHECK-NEXT: store <4 x i32> [[REG173]], <4 x i32>* [[REG174:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG175:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG170]], align 16
 // CHECK-NEXT: [[REG176:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG174]], align 16
 // CHECK-NEXT: [[REG177:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: call <4 x i32> @vec_perm(int vector[4], int vector[4], unsigned char vector[16])(<4 x i32> [[REG175]], <4 x i32> [[REG176]], <16 x i8> [[REG177]])
 
 // CHECK: define available_externally i64 @_mm_mullo_pi16
-// CHECK: [[REG178:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)
+// CHECK: [[REG178A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0
+// CHECK-NEXT: [[REG178:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG178A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG179:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG178]] to <8 x i16>
 // CHECK-NEXT: store <8 x i16> [[REG179]], <8 x i16>* [[REG180:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG181:[0-9a-zA-Z_%.]+]] = load i64, i64* {{[0-9a-zA-Z_%.]+}}, align 8
-// CHECK-NEXT: [[REG182:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)
+// CHECK-NEXT: [[REG182A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0
+// CHECK-NEXT: [[REG182:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG182A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG183:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG182]] to <8 x i16>
 // CHECK-NEXT: store <8 x i16> [[REG183]], <8 x i16>* [[REG184:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG185:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG180]], align 16
 // CHECK-NEXT: [[REG186:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG184]], align 16
 // CHECK-NEXT: [[REG187:[0-9a-zA-Z_%.]+]] = mul <8 x i16> [[REG185]], [[REG186]]
 // CHECK-NEXT: store <8 x i16> [[REG187]], <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16
 
 void __attribute__((noinline))

 // CHECK-NEXT: store i32 {{[0-9a-zA-Z_%.]+}}, i32* [[REG244]], align 8
 // CHECK-NEXT: [[REG245:[0-9a-zA-Z_%.]+]] = load i32, i32* {{[0-9a-zA-Z_%.]+}}, align 4
 // CHECK: [[REG246:[0-9a-zA-Z_%.]+]] = getelementptr inbounds [2 x i32], [2 x i32]* {{[0-9a-zA-Z_%.]+}}, i64 0, i64 1
 // CHECK-NEXT: store i32 {{[0-9a-zA-Z_%.]+}}, i32* [[REG246]], align 4
 
 // CHECK: define available_externally i64 @_mm_set1_pi16
 
 // CHECK-P9: [[REG247:[0-9a-zA-Z_%.]+]] = load i16, i16* {{[0-9a-zA-Z_%.]+}}, align 2
-// CHECK-P9-NEXT: [[REG248:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_splats(short)(i16 signext [[REG247]])
-// CHECK-P9-NEXT: store <8 x i16> %call, <8 x i16>* [[REG249:[0-9a-zA-Z_%.]+]], align 16
+// CHECK-P9-NEXT: [[REG248A:[0-9a-zA-Z_%.]+]] = insertelement <8 x i16> undef, i16 [[REG247]], i32 0
+// CHECK-P9-NEXT: [[REG248:[0-9a-zA-Z_%.]+]]  = shufflevector <8 x i16> [[REG248A]], <8 x i16> undef, <8 x i32> zeroinitializer
+// CHECK-P9-NEXT: store <8 x i16> [[REG248]], <8 x i16>* [[REG249:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-P9-NEXT: [[REG250:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG249:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-P9-NEXT: [[REG251:[0-9a-zA-Z_%.]+]] = bitcast <8 x i16> [[REG250]] to <2 x i64>
 // CHECK-P9-NEXT: [[REG252:[0-9a-zA-Z_%.]+]] = extractelement <2 x i64> [[REG251]], i32 0
 // CHECK-P9-NEXT: ret i64 [[REG252]]
 
 // CHECK-P8: [[REG253:[0-9a-zA-Z_%.]+]] = load i16, i16* [[REG254:[0-9a-zA-Z_%.]+]], align 2
 // CHECK-P8: [[REG255:[0-9a-zA-Z_%.]+]] = getelementptr inbounds [4 x i16], [4 x i16]* {{[0-9a-zA-Z_%.]+}}, i64 0, i64 0
 // CHECK-P8-NEXT: store i16 [[REG253]], i16* [[REG255]], align 8
 // CHECK-P8-NEXT: [[REG250:[0-9a-zA-Z_%.]+]] = load i16, i16* [[REG254]], align 2
 // CHECK-P8: [[REG256:[0-9a-zA-Z_%.]+]] = getelementptr inbounds [4 x i16], [4 x i16]* {{[0-9a-zA-Z_%.]+}}, i64 0, i64 1
 // CHECK-P8-NEXT: store i16 [[REG250]], i16* [[REG256]], align 2
 // CHECK-P8-NEXT: [[REG251:[0-9a-zA-Z_%.]+]] = load i16, i16* [[REG254]], align 2
 // CHECK-P8: [[REG257:[0-9a-zA-Z_%.]+]] = getelementptr inbounds [4 x i16], [4 x i16]* {{[0-9a-zA-Z_%.]+}}, i64 0, i64 2
 // CHECK-P8-NEXT: store i16 [[REG251]], i16* [[REG257]], align 4
 // CHECK-P8-NEXT: [[REG258:[0-9a-zA-Z_%.]+]] = load i16, i16* [[REG254]], align 2
 // CHECK-P8: [[REG259:[0-9a-zA-Z_%.]+]] = getelementptr inbounds [4 x i16], [4 x i16]* {{[0-9a-zA-Z_%.]+}}, i64 0, i64 3
 // CHECK-P8-NEXT: store i16 [[REG258]], i16* [[REG259]], align 2
 
 // CHECK: define available_externally i64 @_mm_set1_pi8
-// CHECK: [[REG260:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_splats(signed char)(i8 signext {{[0-9a-zA-Z_%.]+}})
+// CHECK: [[REG260A:[0-9a-zA-Z_%.]+]] = insertelement <16 x i8> undef, i8 {{[0-9a-zA-Z_%.]+}}, i32 0
+// CHECK-NEXT: [[REG260:[0-9a-zA-Z_%.]+]]  = shufflevector <16 x i8> [[REG260A]], <16 x i8> undef, <16 x i32> zeroinitializer
 // CHECK-NEXT: store <16 x i8> [[REG260]], <16 x i8>* [[REG261:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG262:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG261:[0-9a-zA-Z_%.]+]], align 16
-// CHECK-NEXT: [[REG263:[0-9a-zA-Z_%.]+]] = bitcast <16 x i8> %1 to <2 x i64>
+// CHECK-NEXT: [[REG263:[0-9a-zA-Z_%.]+]] = bitcast <16 x i8> {{[0-9a-zA-Z_%.]+}} to <2 x i64>
 // CHECK-NEXT: [[REG264:[0-9a-zA-Z_%.]+]] = extractelement <2 x i64> [[REG263]], i32 0
 // CHECK-NEXT: ret i64 [[REG264]]
 
 void __attribute__((noinline))
 test_setr() {
   res = _mm_setr_pi32(i1, i2);
   res = _mm_setr_pi16(s[0], s[1], s[2], s[3]);
   res = _mm_setr_pi8(c[0], c[1], c[2], c[3], c[4], c[5], c[6], c[7]);

 }
 
 // CHECK-LABEL: @test_sll
 
 // CHECK: define available_externally i64 @_mm_sll_pi16
 // CHECK: [[REG271:[0-9a-zA-Z_%.]+]] = icmp ule i64 {{[0-9a-zA-Z_%.]+}}, 15
 // CHECK-NEXT: br i1 [[REG271]], label %[[REG272:[0-9a-zA-Z_.]+]], label %[[REG273:[0-9a-zA-Z_.]+]]
 // CHECK: [[REG272]]
-// CHECK: call <2 x i64> @vec_splats(unsigned long long)
+// CHECK: insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0
 // CHECK: trunc i64 {{[0-9a-zA-Z_%.]+}} to i16
-// CHECK-NEXT: call <8 x i16> @vec_splats(unsigned short)
+// CHECK-NEXT: insertelement <8 x i16> undef, i16 {{[0-9a-zA-Z_%.]+}}, i32 0
 // CHECK: call <8 x i16> @vec_sl(short vector[8], unsigned short vector[8])
 // CHECK: store i64 [[REG274:[0-9a-zA-Z_%.]+]], i64* [[REG275:[0-9a-zA-Z_%.]+]], align 8
 // CHECK-NEXT: br label %[[REG276:[0-9a-zA-Z_%.]+]]
 // CHECK: [[REG273]]
 // CHECK-NEXT: store i64 0, i64* [[REG275]], align 8
 // CHECK-NEXT: br label %[[REG276]]
 // CHECK: [[REG276]]
 // CHECK-NEXT: [[REG277:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG275]], align 8

 // CHECK-NEXT: [[REG311:[0-9a-zA-Z_%.]+]] = ashr i32 [[REG308]], [[REG310]]
 // CHECK: [[REG312:[0-9a-zA-Z_%.]+]] = getelementptr inbounds [2 x i32], [2 x i32]* {{[0-9a-zA-Z_%.]+}}, i64 0, i64 1
 // CHECK-NEXT: store i32 [[REG311]], i32* [[REG312]], align 4
 
 // CHECK: define available_externally i64 @_mm_sra_pi16
 // CHECK: [[REG313:[0-9a-zA-Z_%.]+]] = icmp ule i64 {{[0-9a-zA-Z_%.]+}}, 15
 // CHECK-NEXT: br i1 [[REG313]], label %[[REG314:[0-9a-zA-Z_%.]+]], label %[[REG315:[0-9a-zA-Z_%.]+]]
 // CHECK: [[REG314]]
-// CHECK: [[REG316:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 {{[0-9a-zA-Z_%.]+}})
+// CHECK: [[REG316A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0
+// CHECK-NEXT: [[REG316:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG316A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG317:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG316]] to <8 x i16>
 // CHECK-NEXT: store <8 x i16> [[REG317]], <8 x i16>* [[REG318:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG319:[0-9a-zA-Z_%.]+]] = load i64, i64* {{[0-9a-zA-Z_%.]+}}, align 8
 // CHECK-NEXT: [[REG320:[0-9a-zA-Z_%.]+]] = trunc i64 [[REG319]] to i16
-// CHECK-NEXT: [[REG321:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_splats(unsigned short)(i16 zeroext [[REG320]])
+// CHECK-NEXT: [[REG321A:[0-9a-zA-Z_%.]+]] = insertelement <8 x i16> undef, i16 [[REG320]], i32 0
+// CHECK-NEXT: [[REG321:[0-9a-zA-Z_%.]+]]  = shufflevector <8 x i16> [[REG321A]], <8 x i16> undef, <8 x i32> zeroinitializer
 // CHECK-NEXT: store <8 x i16> [[REG321]], <8 x i16>* [[REG322:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG323:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG318]], align 16
 // CHECK-NEXT: [[REG324:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG322]], align 16
 // CHECK-NEXT: call <8 x i16> @vec_sra(short vector[8], unsigned short vector[8])(<8 x i16> [[REG323]], <8 x i16> [[REG324]])
 // CHECK: store i64 {{[0-9a-zA-Z_%.]+}}, i64* [[REG325:[0-9a-zA-Z_%.]+]], align 8
 // CHECK-NEXT: br label %[[REG326:[0-9a-zA-Z_%.]+]]
 // CHECK: [[REG315]]
 // CHECK-NEXT: store i64 0, i64* [[REG325]], align 8

 // CHECK-NEXT: [[REG347:[0-9a-zA-Z_%.]+]] = lshr i32 [[REG344]], [[REG346]]
 // CHECK: [[REG348:[0-9a-zA-Z_%.]+]] = getelementptr inbounds [2 x i32], [2 x i32]* {{[0-9a-zA-Z_%.]+}}, i64 0, i64 1
 // CHECK-NEXT: store i32 [[REG347]], i32* [[REG348]], align 4
 
 // CHECK: define available_externally i64 @_mm_srl_pi16
 // CHECK: [[REG349:[0-9a-zA-Z_%.]+]] = icmp ule i64 {{[0-9a-zA-Z_%.]+}}, 15
 // CHECK-NEXT: br i1 [[REG349]], label %[[REG350:[0-9a-zA-Z_%.]+]], label %[[REG351:[0-9a-zA-Z_%.]+]]
 // CHECK: [[REG350]]
-// CHECK: [[REG352:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 {{[0-9a-zA-Z_%.]+}})
+// CHECK: [[REG352A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0
+// CHECK-NEXT: [[REG352:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG352A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG353:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG352]] to <8 x i16>
 // CHECK-NEXT: store <8 x i16> [[REG353]], <8 x i16>* [[REG354:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG355:[0-9a-zA-Z_%.]+]] = load i64, i64* {{[0-9a-zA-Z_%.]+}}, align 8
 // CHECK-NEXT: [[REG356:[0-9a-zA-Z_%.]+]] = trunc i64 [[REG355]] to i16
-// CHECK-NEXT: [[REG357:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_splats(unsigned short)(i16 zeroext [[REG356]])
+// CHECK-NEXT: [[REG357A:[0-9a-zA-Z_%.]+]] = insertelement <8 x i16> undef, i16 [[REG356]], i32 0
+// CHECK-NEXT: [[REG357:[0-9a-zA-Z_%.]+]]  = shufflevector <8 x i16> [[REG357A]], <8 x i16> undef, <8 x i32> zeroinitializer
 // CHECK-NEXT: store <8 x i16> [[REG357]], <8 x i16>* [[REG358:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG359:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG354]], align 16
 // CHECK-NEXT: [[REG360:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG358]], align 16
 // CHECK-NEXT: call <8 x i16> @vec_sr(unsigned short vector[8], unsigned short vector[8])(<8 x i16> [[REG359]], <8 x i16> [[REG360]])
 // CHECK: store i64 {{[0-9a-zA-Z_%.]+}}, i64* [[REG361:[0-9a-zA-Z_%.]+]], align 8
 // CHECK-NEXT: br label %[[REG362:[0-9a-zA-Z_%.]+]]
 // CHECK: [[REG351]]
 // CHECK-NEXT: store i64 0, i64* {{[0-9a-zA-Z_%.]+}}, align 8

 // CHECK-P8-NEXT: [[REG378:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG377]], align 8
 // CHECK-P8-NEXT: sub nsw i32 [[REG376]], [[REG378]]
 // CHECK-P8: [[REG379:[0-9a-zA-Z_%.]+]] = getelementptr inbounds [2 x i32], [2 x i32]* {{[0-9a-zA-Z_%.]+}}, i64 0, i64 1
 // CHECK-P8-NEXT: [[REG380:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG379]], align 4
 // CHECK-P8: [[REG381:[0-9a-zA-Z_%.]+]] = getelementptr inbounds [2 x i32], [2 x i32]* {{[0-9a-zA-Z_%.]+}}, i64 0, i64 1
 // CHECK-P8-NEXT: [[REG382:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG381]], align 4
 // CHECK-P8-NEXT: sub nsw i32 [[REG380]], [[REG382]]
 
-// CHECK-P9: [[REG383:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 {{[0-9a-zA-Z_%.]+}})
+// CHECK-P9: [[REG383A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0
+// CHECK-P9-NEXT: [[REG383:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG383A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-P9-NEXT: [[REG384:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG383]] to <4 x i32>
 // CHECK-P9-NEXT: store <4 x i32> [[REG384]], <4 x i32>* [[REG385:[0-9a-zA-Z_%.]+]], align 16
-// CHECK-P9: [[REG386:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 {{[0-9a-zA-Z_%.]+}})
+// CHECK-P9: [[REG386A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0
+// CHECK-P9-NEXT: [[REG386:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG386A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-P9-NEXT: [[REG387:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG386]] to <4 x i32>
 // CHECK-P9-NEXT: store <4 x i32> [[REG387]], <4 x i32>* [[REG388:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-P9-NEXT: [[REG389:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG385]], align 16
 // CHECK-P9-NEXT: [[REG390:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG388]], align 16
 // CHECK-P9-NEXT: call <4 x i32> @vec_sub(int vector[4], int vector[4])(<4 x i32> [[REG389]], <4 x i32> [[REG390]])
 
 // CHECK: define available_externally i64 @_mm_sub_pi16
-// CHECK: [[REG391:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 {{[0-9a-zA-Z_%.]+}})
+// CHECK: [[REG391A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0
+// CHECK-NEXT: [[REG391:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG391A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG392:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG391]] to <8 x i16>
 // CHECK-NEXT: store <8 x i16> [[REG392]], <8 x i16>* [[REG393:[0-9a-zA-Z_%.]+]], align 16
-// CHECK: [[REG394:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 {{[0-9a-zA-Z_%.]+}})
+// CHECK: [[REG394A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0
+// CHECK-NEXT: [[REG394:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG394A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG395:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG394]] to <8 x i16>
 // CHECK-NEXT: store <8 x i16> [[REG395]], <8 x i16>* [[REG396:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG397:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG393]], align 16
 // CHECK-NEXT: [[REG398:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG396]], align 16
 // CHECK-NEXT: call <8 x i16> @vec_sub(short vector[8], short vector[8])(<8 x i16> [[REG397]], <8 x i16> [[REG398]])
 
 // CHECK: define available_externally i64 @_mm_sub_pi8
-// CHECK: [[REG399:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 {{[0-9a-zA-Z_%.]+}})
+// CHECK: [[REG399A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0
+// CHECK-NEXT: [[REG399:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG399A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG400:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG399]] to <16 x i8>
 // CHECK-NEXT: store <16 x i8> [[REG400]], <16 x i8>* [[REG401:[0-9a-zA-Z_%.]+]], align 16
-// CHECK: [[REG402:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 {{[0-9a-zA-Z_%.]+}})
+// CHECK: [[REG402A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0
+// CHECK-NEXT: [[REG402:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG402A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG403:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG402]] to <16 x i8>
 // CHECK-NEXT: store <16 x i8> [[REG403]], <16 x i8>* [[REG404:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG405:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG401]], align 16
 // CHECK-NEXT: [[REG406:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG404]], align 16
 // CHECK-NEXT: call <16 x i8> @vec_sub(signed char vector[16], signed char vector[16])(<16 x i8> [[REG405]], <16 x i8> [[REG406]])
 
 // CHECK: define available_externally i64 @_mm_subs_pi16
-// CHECK: [[REG407:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 {{[0-9a-zA-Z_%.]+}})
+// CHECK: [[REG407A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0
+// CHECK-NEXT: [[REG407:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG407A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG408:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG407]] to <8 x i16>
 // CHECK-NEXT: store <8 x i16> [[REG408]], <8 x i16>* [[REG409:[0-9a-zA-Z_%.]+]], align 16
-// CHECK: [[REG410:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 {{[0-9a-zA-Z_%.]+}})
+// CHECK: [[REG410A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0
+// CHECK-NEXT: [[REG410:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG410A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG411:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG410]] to <8 x i16>
 // CHECK-NEXT: store <8 x i16> [[REG411]], <8 x i16>* [[REG412:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG413:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG409]], align 16
 // CHECK-NEXT: [[REG414:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG412]], align 16
 // CHECK-NEXT: call <8 x i16> @vec_subs(short vector[8], short vector[8])(<8 x i16> [[REG413]], <8 x i16> [[REG414]])
 
 // CHECK: define available_externally i64 @_mm_subs_pi8
-// CHECK: [[REG415:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 {{[0-9a-zA-Z_%.]+}})
+// CHECK: [[REG415A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0
+// CHECK-NEXT: [[REG415:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG415A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG416:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG415]] to <16 x i8>
 // CHECK-NEXT: store <16 x i8> [[REG416]], <16 x i8>* [[REG417:[0-9a-zA-Z_%.]+]], align 16
-// CHECK: [[REG418:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 {{[0-9a-zA-Z_%.]+}})
+// CHECK: [[REG418A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0
+// CHECK-NEXT: [[REG418:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG418A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG419:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG418]] to <16 x i8>
 // CHECK-NEXT: store <16 x i8> [[REG419]], <16 x i8>* [[REG420:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG421:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG417]], align 16
 // CHECK-NEXT: [[REG422:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG420]], align 16
 // CHECK-NEXT: call <16 x i8> @vec_subs(signed char vector[16], signed char vector[16])(<16 x i8> [[REG421]], <16 x i8> [[REG422]])
 
 // CHECK: define available_externally i64 @_mm_subs_pu16
-// CHECK: [[REG423:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 {{[0-9a-zA-Z_%.]+}})
+// CHECK: [[REG423A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0
+// CHECK-NEXT: [[REG423:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG423A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG424:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG423]] to <8 x i16>
 // CHECK-NEXT: store <8 x i16> [[REG424]], <8 x i16>* [[REG425:[0-9a-zA-Z_%.]+]], align 16
-// CHECK: [[REG426:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 {{[0-9a-zA-Z_%.]+}})
+// CHECK: [[REG426A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0
+// CHECK-NEXT: [[REG426:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG426A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG427:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG426]] to <8 x i16>
 // CHECK-NEXT: store <8 x i16> [[REG427]], <8 x i16>* [[REG428:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG429:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG425]], align 16
 // CHECK-NEXT: [[REG430:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG428]], align 16
 // CHECK-NEXT: call <8 x i16> @vec_subs(unsigned short vector[8], unsigned short vector[8])(<8 x i16> [[REG429]], <8 x i16> [[REG430]])
 
 // CHECK: define available_externally i64 @_mm_subs_pu8
-// CHECK: [[REG431:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 {{[0-9a-zA-Z_%.]+}})
+// CHECK: [[REG431A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0
+// CHECK-NEXT: [[REG431:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG431A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG432:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG431]] to <16 x i8>
 // CHECK-NEXT: store <16 x i8> [[REG432]], <16 x i8>* [[REG433:[0-9a-zA-Z_%.]+]], align 16
-// CHECK: [[REG434:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 {{[0-9a-zA-Z_%.]+}})
+// CHECK: [[REG434A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0
+// CHECK-NEXT: [[REG434:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG434A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG435:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG434]] to <16 x i8>
 // CHECK-NEXT: store <16 x i8> [[REG435]], <16 x i8>* [[REG436:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG437:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG433]], align 16
 // CHECK-NEXT: [[REG438:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG436]], align 16
 // CHECK-NEXT: call <16 x i8> @vec_subs(unsigned char vector[16], unsigned char vector[16])(<16 x i8> [[REG437]], <16 x i8> [[REG438]])
 
 void __attribute__((noinline))
 test_alt_name_sub() {

 // CHECK: [[REG463:[0-9a-zA-Z_%.]+]] = getelementptr inbounds [4 x i16], [4 x i16]* {{[0-9a-zA-Z_%.]+}}, i64 0, i64 2
 // CHECK-NEXT: store i16 [[REG462]], i16* [[REG463]], align 4
 // CHECK: [[REG464:[0-9a-zA-Z_%.]+]] = getelementptr inbounds [4 x i16], [4 x i16]* {{[0-9a-zA-Z_%.]+}}, i64 0, i64 3
 // CHECK-NEXT: [[REG465:[0-9a-zA-Z_%.]+]] = load i16, i16* [[REG464]], align 2
 // CHECK: [[REG466:[0-9a-zA-Z_%.]+]] = getelementptr inbounds [4 x i16], [4 x i16]* {{[0-9a-zA-Z_%.]+}}, i64 0, i64 3
 // CHECK-NEXT: store i16 [[REG465]], i16* [[REG466]], align 2
 
 // CHECK: define available_externally i64 @_mm_unpackhi_pi8
-// CHECK: [[REG467:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)
+// CHECK: [[REG467A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0
+// CHECK-NEXT: [[REG467:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG467A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG468:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG467]] to <16 x i8>
 // CHECK-NEXT: store <16 x i8> [[REG468]], <16 x i8>* [[REG469:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG470:[0-9a-zA-Z_%.]+]] = load i64, i64* {{[0-9a-zA-Z_%.]+}}, align 8
-// CHECK-NEXT: [[REG471:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)
+// CHECK-NEXT: [[REG471A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0
+// CHECK-NEXT: [[REG471:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG471A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG472:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG471]] to <16 x i8>
 // CHECK-NEXT: store <16 x i8> [[REG472]], <16 x i8>* [[REG473:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG474:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG469]], align 16
 // CHECK-NEXT: [[REG475:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG473]], align 16
 // CHECK-NEXT: call <16 x i8> @vec_mergel(unsigned char vector[16], unsigned char vector[16])(<16 x i8> [[REG474]], <16 x i8> [[REG475]])
 
 // CHECK: define available_externally i64 @_mm_unpacklo_pi32
 // CHECK: [[REG476:[0-9a-zA-Z_%.]+]] = getelementptr inbounds [2 x i32], [2 x i32]* {{[0-9a-zA-Z_%.]+}}, i64 0, i64 0

 // CHECK: [[REG490:[0-9a-zA-Z_%.]+]] = getelementptr inbounds [4 x i16], [4 x i16]* {{[0-9a-zA-Z_%.]+}}, i64 0, i64 2
 // CHECK-NEXT: store i16 [[REG489]], i16* [[REG490]], align 4
 // CHECK: [[REG491:[0-9a-zA-Z_%.]+]] = getelementptr inbounds [4 x i16], [4 x i16]* {{[0-9a-zA-Z_%.]+}}, i64 0, i64 1
 // CHECK-NEXT: [[REG492:[0-9a-zA-Z_%.]+]] = load i16, i16* [[REG491]], align 2
 // CHECK: [[REG493:[0-9a-zA-Z_%.]+]] = getelementptr inbounds [4 x i16], [4 x i16]* {{[0-9a-zA-Z_%.]+}}, i64 0, i64 3
 // CHECK-NEXT: store i16 [[REG492]], i16* [[REG493]], align 2
 
 // CHECK: define available_externally i64 @_mm_unpacklo_pi8
-// CHECK: [[REG494:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)
+// CHECK: [[REG494A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0
+// CHECK-NEXT: [[REG494:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG494A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG495:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG494]] to <16 x i8>
 // CHECK-NEXT: store <16 x i8> [[REG495]], <16 x i8>* [[REG496:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG497:[0-9a-zA-Z_%.]+]] = load i64, i64* {{[0-9a-zA-Z_%.]+}}, align 8
-// CHECK-NEXT: [[REG498:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)
+// CHECK-NEXT: [[REG498A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0
+// CHECK-NEXT: [[REG498:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG498A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG499:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG498]] to <16 x i8>
 // CHECK-NEXT: store <16 x i8> [[REG499]], <16 x i8>* [[REG500:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG501:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG496]], align 16
 // CHECK-NEXT: [[REG502:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG500]], align 16
 // CHECK-NEXT: [[REG503:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_mergel(unsigned char vector[16], unsigned char vector[16])
 
 void __attribute__((noinline))
 test_alt_name_unpack() {

clang/test/CodeGen/ppc-pmmintrin.c

-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // REQUIRES: powerpc-registered-target
 
 // RUN: %clang -S -emit-llvm -target powerpc64-gnu-linux -mcpu=pwr8 -DNO_MM_MALLOC -ffreestanding -DNO_WARN_X86_INTRINSICS %s \
 // RUN:   -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s
 // RUN: %clang -S -emit-llvm -target powerpc64le-gnu-linux -mcpu=pwr8 -DNO_MM_MALLOC -ffreestanding -DNO_WARN_X86_INTRINSICS %s \
 // RUN:   -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s
 
 #include <pmmintrin.h>

 // CHECK-NEXT: [[REG79:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_vsx_ld(int, int const*)(i32 signext 0, i32* [[REG78]])
 // CHECK-NEXT: [[REG80:[0-9a-zA-Z_%.]+]] = bitcast <4 x i32> [[REG79]] to <2 x i64>
 // CHECK-NEXT: ret <2 x i64> [[REG80]]
 
 // CHECK: define available_externally <2 x double> @_mm_loaddup_pd(double* [[REG81:[0-9a-zA-Z_%.]+]])
 // CHECK: store double* [[REG81]], double** [[REG82:[0-9a-zA-Z_%.]+]], align 8
 // CHECK-NEXT: [[REG83:[0-9a-zA-Z_%.]+]] = load double*, double** [[REG82]], align 8
 // CHECK-NEXT: [[REG84:[0-9a-zA-Z_%.]+]] = load double, double* [[REG83]], align 8
-// CHECK-NEXT: [[REG85:[0-9a-zA-Z_%.]+]] = call <2 x double> @vec_splats(double)(double [[REG84]])
+// CHECK-NEXT: [[REG85A:[0-9a-zA-Z_%.]+]] = insertelement <2 x double> undef, double [[REG84]], i32 0
+// CHECK-NEXT: [[REG85:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x double> [[REG85A]], <2 x double> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: ret <2 x double> [[REG85]]
 
 // CHECK: define available_externally <2 x double> @_mm_movedup_pd(<2 x double> [[REG86:[0-9a-zA-Z_%.]+]])
 // CHECK: store <2 x double> [[REG86]], <2 x double>* [[REG87:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG88:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG87]], align 16
 // CHECK-NEXT: [[REG89:[0-9a-zA-Z_%.]+]] = load <2 x double>, <2 x double>* [[REG87]], align 16
 // CHECK-NEXT: [[REG90:[0-9a-zA-Z_%.]+]] = call <2 x double> @_mm_shuffle_pd(<2 x double> [[REG88]], <2 x double> [[REG89]], i32 signext 0)
 // CHECK-NEXT: ret <2 x double> [[REG90]]

clang/test/CodeGen/ppc-smmintrin.c

-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // REQUIRES: powerpc-registered-target
 
 // RUN: %clang -S -emit-llvm -target powerpc64le-unknown-linux-gnu -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \
 // RUN:   -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,LE
 // RUN: %clang -S -emit-llvm -target powerpc64-unknown-linux-gnu -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \
 // RUN:   -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,BE
 
 #include <smmintrin.h>

 // CHECK-LABEL: @test_blend
 
 // CHECK: define available_externally <2 x i64> @_mm_blend_epi16(<2 x i64> [[REG38:[0-9a-zA-Z_%.]+]], <2 x i64> [[REG39:[0-9a-zA-Z_%.]+]], i32 signext [[REG40:[0-9a-zA-Z_%.]+]])
 // CHECK: store <2 x i64> [[REG38]], <2 x i64>* [[REG41:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: store <2 x i64> [[REG39]], <2 x i64>* [[REG42:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: store i32 [[REG40]], i32* [[REG43:[0-9a-zA-Z_%.]+]], align 4
 // CHECK-NEXT: [[REG44:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG43]], align 4
 // CHECK-NEXT: [[REG45:[0-9a-zA-Z_%.]+]] = trunc i32 [[REG44]] to i8
-// CHECK-NEXT: [[REG46:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_splats(signed char)(i8 signext [[REG45]])
+// CHECK-NEXT: [[REG45A:[0-9a-zA-Z_%.]+]] = insertelement <16 x i8> undef, i8 [[REG45]], i32 0
+// CHECK-NEXT: [[REG46:[0-9a-zA-Z_%.]+]] = shufflevector <16 x i8> [[REG45A]], <16 x i8> undef, <16 x i32> zeroinitializer
 // CHECK-NEXT: store <16 x i8> [[REG46]], <16 x i8>* [[REG47:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG48:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG47]], align 16
 // CHECK-NEXT: [[REG49:[0-9a-zA-Z_%.]+]] = call <16 x i8> @llvm.ppc.altivec.vgbbd(<16 x i8> [[REG48]])
 // CHECK-NEXT: store <16 x i8> [[REG49]], <16 x i8>* [[REG47]], align 16
 // CHECK-NEXT: [[REG50:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG47]], align 16
 // CHECK-NEXT: [[REG51:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_unpackh(signed char vector[16])(<16 x i8> [[REG50]])
 // CHECK-NEXT: store <8 x i16> [[REG51]], <8 x i16>* [[REG52:[0-9a-zA-Z_%.]+]], align 16
 

 // CHECK-NEXT: [[REG60:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_sel(unsigned short vector[8], unsigned short vector[8], unsigned short vector[8])(<8 x i16> [[REG56]], <8 x i16> [[REG58]], <8 x i16> [[REG59]])
 // CHECK-NEXT: [[REG61:[0-9a-zA-Z_%.]+]] = bitcast <8 x i16> [[REG60]] to <2 x i64>
 // CHECK-NEXT: ret <2 x i64> [[REG61]]
 
 // CHECK: define available_externally <2 x i64> @_mm_blendv_epi8(<2 x i64> [[REG62:[0-9a-zA-Z_%.]+]], <2 x i64> [[REG63:[0-9a-zA-Z_%.]+]], <2 x i64> [[REG64:[0-9a-zA-Z_%.]+]])
 // CHECK: store <2 x i64> [[REG62]], <2 x i64>* [[REG65:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: store <2 x i64> [[REG63]], <2 x i64>* [[REG66:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: store <2 x i64> [[REG64]], <2 x i64>* [[REG67:[0-9a-zA-Z_%.]+]], align 16
-// CHECK-NEXT: [[REG68:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_splats(unsigned char)(i8 zeroext 7)
-// CHECK-NEXT: store <16 x i8> [[REG68]], <16 x i8>* [[REG69:[0-9a-zA-Z_%.]+]], align 16
+// CHECK-NEXT: store <16 x i8> <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>, <16 x i8>* [[REG68:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG70:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG67]], align 16
 // CHECK-NEXT: [[REG71:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG70]] to <16 x i8>
-// CHECK-NEXT: [[REG72:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG69]], align 16
-// CHECK-NEXT: [[REG73:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_sra(unsigned char vector[16], unsigned char vector[16])(<16 x i8> [[REG71]], <16 x i8> [[REG72]])
+// CHECK-NEXT: [[REG73:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_sra(unsigned char vector[16], unsigned char vector[16])(<16 x i8> [[REG71]], <16 x i8> <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>)
 // CHECK-NEXT: store <16 x i8> [[REG73]], <16 x i8>* [[REG74:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG75:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG65]], align 16
 // CHECK-NEXT: [[REG76:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG75]] to <16 x i8>
 // CHECK-NEXT: [[REG77:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG66]], align 16
 // CHECK-NEXT: [[REG78:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG77]] to <16 x i8>
 // CHECK-NEXT: [[REG79:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG74]], align 16
 // CHECK-NEXT: [[REG80:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_sel(unsigned char vector[16], unsigned char vector[16], unsigned char vector[16])(<16 x i8> [[REG76]], <16 x i8> [[REG78]], <16 x i8> [[REG79]])
 // CHECK-NEXT: [[REG81:[0-9a-zA-Z_%.]+]] = bitcast <16 x i8> [[REG80]] to <2 x i64>
 // CHECK-NEXT: ret <2 x i64> [[REG81]]

clang/test/CodeGen/ppc-tmmintrin.c

-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // REQUIRES: powerpc-registered-target
 
 // RUN: %clang -S -emit-llvm -target powerpc64-gnu-linux -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \
 // RUN:   -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-BE
 // RUN: %clang -S -emit-llvm -target powerpc64le-gnu-linux -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \
 // RUN:   -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-LE
 
 #include <tmmintrin.h>

 // CHECK-NEXT: store <2 x i64> zeroinitializer, <2 x i64>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: br label %[[REG72:[0-9a-zA-Z_%.]+]]
 
 // CHECK: [[REG85]]:
 // CHECK-NEXT: [[REG87:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG64]], align 4
 // CHECK-NEXT: [[REG88:[0-9a-zA-Z_%.]+]] = sub i32 [[REG87]], 16
 // CHECK-NEXT: [[REG89:[0-9a-zA-Z_%.]+]] = mul i32 [[REG88]], 8
 // CHECK-NEXT: [[REG90:[0-9a-zA-Z_%.]+]] = trunc i32 [[REG89]] to i8
-// CHECK-NEXT: [[REG91:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_splats(unsigned char)(i8 zeroext [[REG90]])
+// CHECK-NEXT: [[REG91A:[0-9a-zA-Z_%.]+]] = insertelement <16 x i8> undef, i8 [[REG90]], i32 0
+// CHECK-NEXT: [[REG91:[0-9a-zA-Z_%.]+]]  = shufflevector <16 x i8> [[REG91A]], <16 x i8> undef, <16 x i32> zeroinitializer
 // CHECK-NEXT: store <16 x i8> [[REG91]], <16 x i8>* [[REG92:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG93:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG65]], align 16
 // CHECK-NEXT: [[REG94:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG93]] to <16 x i8>
 // CHECK-NEXT: [[REG95:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* [[REG92]], align 16
 // CHECK-BE-NEXT: [[REG96:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_slo(unsigned char vector[16], unsigned char vector[16])
 // CHECK-LE-NEXT: [[REG96:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_sro(unsigned char vector[16], unsigned char vector[16])
 // CHECK-NEXT: [[REG97:[0-9a-zA-Z_%.]+]] = bitcast <16 x i8> [[REG96]] to <2 x i64>
 // CHECK-NEXT: store <2 x i64> [[REG97]], <2 x i64>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: br label %[[REG72:[0-9a-zA-Z_%.]+]]
 
 // CHECK: [[REG81]]:
 // CHECK-NEXT: [[REG98:[0-9a-zA-Z_%.]+]] = load i32, i32* [[REG64]], align 4
 // CHECK-NEXT: [[REG99:[0-9a-zA-Z_%.]+]] = sub i32 16, [[REG98]]
 // CHECK-NEXT: [[REG100:[0-9a-zA-Z_%.]+]] = mul i32 [[REG99]], 8
 
 // CHECK-BE: [[REG101:[0-9a-zA-Z_%.]+]] = trunc i32 [[REG100]] to i8
-// CHECK-BE: [[REG102:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_splats(unsigned char)(i8 zeroext [[REG101]])
+// CHECK-BE: [[REG102A:[0-9a-zA-Z_%.]+]] = insertelement <16 x i8> undef, i8 [[REG101]], i32 0
+// CHECK-BE-NEXT: [[REG102:[0-9a-zA-Z_%.]+]]  = shufflevector <16 x i8> [[REG102A]], <16 x i8> undef, <16 x i32> zeroinitializer
 // CHECK-BE: mul i32 {{[0-9a-zA-Z_%.]+}}, 8
 // CHECK-BE: call <16 x i8> @vec_sro(unsigned char vector[16], unsigned char vector[16])
 // CHECK-BE: call <16 x i8> @vec_slo(unsigned char vector[16], unsigned char vector[16])
 // CHECK-BE: [[REG103:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_or(unsigned char vector[16], unsigned char vector[16])
 // CHECK-BE-NEXT: [[REG104:[0-9a-zA-Z_%.]+]] = bitcast <16 x i8> [[REG103]] to <2 x i64>
 // CHECK-BE-NEXT: store <2 x i64> [[REG104]], <2 x i64>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-BE-NEXT: br label %[[REG72:[0-9a-zA-Z_%.]+]]
 
 // CHECK-LE: [[REG105:[0-9a-zA-Z_%.]+]] = mul i32 {{[0-9a-zA-Z_%.]+}}, 8
 // CHECK-LE-NEXT: trunc i32 [[REG105]] to i8
-// CHECK-LE: call <16 x i8> @vec_splats(unsigned char)
 // CHECK-LE: call <16 x i8> @vec_slo(unsigned char vector[16], unsigned char vector[16])
 // CHECK-LE: call <16 x i8> @vec_sro(unsigned char vector[16], unsigned char vector[16])
 // CHECK-LE: [[REG106:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_or(unsigned char vector[16], unsigned char vector[16])
 // CHECK-LE-NEXT: [[REG107:[0-9a-zA-Z_%.]+]] = bitcast <16 x i8> [[REG106]] to <2 x i64>
 // CHECK-LE-NEXT: store <2 x i64> [[REG107]], <2 x i64>* {{[0-9a-zA-Z_%.]+}}, align 16
 
 // CHECK: [[REG72]]:
 // CHECK-NEXT: [[REG108:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* {{[0-9a-zA-Z_%.]+}}, align 16
test_maddubs() {
   res = _mm_maddubs_pi16(m1, m2);
 }
 
 // CHECK-LABEL: @test_maddubs
 
 // CHECK: define available_externally <2 x i64> @_mm_maddubs_epi16(<2 x i64> [[REG645:[0-9a-zA-Z_%.]+]], <2 x i64> [[REG646:[0-9a-zA-Z_%.]+]])
 // CHECK: store <2 x i64> [[REG645]], <2 x i64>* [[REG647:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: store <2 x i64> [[REG646]], <2 x i64>* [[REG648:[0-9a-zA-Z_%.]+]], align 16
-// CHECK-NEXT: [[REG649:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_splats(short)(i16 signext 255)
-// CHECK-NEXT: store <8 x i16> [[REG649]], <8 x i16>* [[REG650:[0-9a-zA-Z_%.]+]], align 16
+// CHECK-NEXT: store <8 x i16> <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>, <8 x i16>* [[REG650:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG651:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG647]], align 16
 // CHECK-NEXT: [[REG652:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG651]] to <16 x i8>
 // CHECK-NEXT: [[REG653:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_unpackh(signed char vector[16])(<16 x i8> [[REG652]])
 // CHECK-NEXT: [[REG654:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG650]], align 16
 // CHECK-NEXT: [[REG655:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_and(short vector[8], short vector[8])(<8 x i16> [[REG653]], <8 x i16> [[REG654]])
 // CHECK-NEXT: store <8 x i16> [[REG655]], <8 x i16>* [[REG656:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG657:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG647]], align 16
 // CHECK-NEXT: [[REG658:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG657]] to <16 x i8>

 // CHECK-NEXT: store <2 x i64> [[REG694]], <2 x i64>* [[REG80:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG695:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG80]], align 16
 // CHECK-NEXT: [[REG84:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG695]] to <8 x i16>
 // CHECK-NEXT: store <8 x i16> [[REG84]], <8 x i16>* [[REG696:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG697:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG696]], align 16
 // CHECK-NEXT: [[REG698:[0-9a-zA-Z_%.]+]] = bitcast <8 x i16> [[REG697]] to <16 x i8>
 // CHECK-NEXT: [[REG699:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_unpackl(signed char vector[16])(<16 x i8> [[REG698]])
 // CHECK-NEXT: store <8 x i16> [[REG699]], <8 x i16>* [[REG696]], align 16
-// CHECK-NEXT: [[REG700:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_splats(short)(i16 signext 255)
-// CHECK-NEXT: store <8 x i16> [[REG700]], <8 x i16>* [[REG701:[0-9a-zA-Z_%.]+]], align 16
+// CHECK-NEXT: store <8 x i16> <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>, <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: [[REG702:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG696]], align 16
-// CHECK-NEXT: [[REG703:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG701]], align 16
-// CHECK-NEXT: [[REG704:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_and(short vector[8], short vector[8])(<8 x i16> [[REG702]], <8 x i16> [[REG703]])
+// CHECK-NEXT: [[REG704:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_and(short vector[8], short vector[8])(<8 x i16> [[REG702]], <8 x i16> <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>)
 // CHECK-NEXT: store <8 x i16> [[REG704]], <8 x i16>* [[REG696]], align 16
 // CHECK-NEXT: [[REG705:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG691]], align 8
 // CHECK-NEXT: [[REG706:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 [[REG705]], i32 0
 // CHECK-NEXT: [[REG707:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG691]], align 8
 // CHECK-NEXT: [[REG708:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> [[REG706]], i64 [[REG707]], i32 1
 // CHECK-NEXT: store <2 x i64> [[REG708]], <2 x i64>* [[REG709:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG710:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG709]], align 16
 // CHECK-NEXT: [[REG711:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG710]] to <8 x i16>

 // CHECK-NEXT: [[REG751:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG736]], align 16
 // CHECK-NEXT: [[REG752:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG751]] to <8 x i16>
 // CHECK-NEXT: [[REG753:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_unpackl(short vector[8])(<8 x i16> [[REG752]])
 // CHECK-NEXT: store <4 x i32> [[REG753]], <4 x i32>* [[REG754:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG755:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG744]], align 16
 // CHECK-NEXT: [[REG756:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG754]], align 16
 // CHECK-NEXT: [[REG757:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_mul(int vector[4], int vector[4])(<4 x i32> [[REG755]], <4 x i32> [[REG756]])
 // CHECK-NEXT: store <4 x i32> [[REG757]], <4 x i32>* [[REG744]], align 16
-// CHECK-NEXT: [[REG758:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splats(unsigned int)(i32 zeroext 14)
-// CHECK-NEXT: store <4 x i32> [[REG758]], <4 x i32>* [[REG759:[0-9a-zA-Z_%.]+]], align 16
+// CHECK-NEXT: store <4 x i32> <i32 14, i32 14, i32 14, i32 14>, <4 x i32>* [[REG759:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG760:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG740]], align 16
-// CHECK-NEXT: [[REG761:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG759]], align 16
-// CHECK-NEXT: [[REG762:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sr(int vector[4], unsigned int vector[4])(<4 x i32> [[REG760]], <4 x i32> [[REG761]])
+// CHECK-NEXT: [[REG762:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sr(int vector[4], unsigned int vector[4])(<4 x i32> [[REG760]], <4 x i32> <i32 14, i32 14, i32 14, i32 14>)
 // CHECK-NEXT: store <4 x i32> [[REG762]], <4 x i32>* [[REG740]], align 16
 // CHECK-NEXT: [[REG763:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG744]], align 16
-// CHECK-NEXT: [[REG764:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG759]], align 16
-// CHECK-NEXT: [[REG765:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sr(int vector[4], unsigned int vector[4])(<4 x i32> [[REG763]], <4 x i32> [[REG764]])
+// CHECK-NEXT: [[REG765:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sr(int vector[4], unsigned int vector[4])(<4 x i32> [[REG763]], <4 x i32> <i32 14, i32 14, i32 14, i32 14>)
 // CHECK-NEXT: store <4 x i32> [[REG765]], <4 x i32>* [[REG744]], align 16
-// CHECK-NEXT: [[REG766:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splats(int)(i32 signext 1)
-// CHECK-NEXT: store <4 x i32> [[REG766]], <4 x i32>* [[REG767:[0-9a-zA-Z_%.]+]], align 16
+// CHECK-NEXT: store <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32>* [[REG767:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG768:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG740]], align 16
-// CHECK-NEXT: [[REG769:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG767]], align 16
-// CHECK-NEXT: [[REG770:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_add(int vector[4], int vector[4])(<4 x i32> [[REG768]], <4 x i32> [[REG769]])
+// CHECK-NEXT: [[REG770:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_add(int vector[4], int vector[4])(<4 x i32> [[REG768]], <4 x i32> <i32 1, i32 1, i32 1, i32 1>)
 // CHECK-NEXT: store <4 x i32> [[REG770]], <4 x i32>* [[REG740]], align 16
 // CHECK-NEXT: [[REG771:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG740]], align 16
-// CHECK-NEXT: [[REG772:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG767]], align 16
-// CHECK-NEXT: [[REG773:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sr(int vector[4], unsigned int vector[4])(<4 x i32> [[REG771]], <4 x i32> [[REG772]])
+// CHECK-NEXT: [[REG773:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sr(int vector[4], unsigned int vector[4])(<4 x i32> [[REG771]], <4 x i32> <i32 1, i32 1, i32 1, i32 1>)
 // CHECK-NEXT: store <4 x i32> [[REG773]], <4 x i32>* [[REG740]], align 16
 // CHECK-NEXT: [[REG774:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG744]], align 16
-// CHECK-NEXT: [[REG775:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG767]], align 16
-// CHECK-NEXT: [[REG776:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_add(int vector[4], int vector[4])(<4 x i32> [[REG774]], <4 x i32> [[REG775]])
+// CHECK-NEXT: [[REG776:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_add(int vector[4], int vector[4])(<4 x i32> [[REG774]], <4 x i32> <i32 1, i32 1, i32 1, i32 1>)
 // CHECK-NEXT: store <4 x i32> [[REG776]], <4 x i32>* [[REG744]], align 16
 // CHECK-NEXT: [[REG777:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG744]], align 16
-// CHECK-NEXT: [[REG778:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG767]], align 16
-// CHECK-NEXT: [[REG779:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sr(int vector[4], unsigned int vector[4])(<4 x i32> [[REG777]], <4 x i32> [[REG778]])
+// CHECK-NEXT: [[REG779:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sr(int vector[4], unsigned int vector[4])(<4 x i32> [[REG777]], <4 x i32> <i32 1, i32 1, i32 1, i32 1>)
 // CHECK-NEXT: store <4 x i32> [[REG779]], <4 x i32>* [[REG744]], align 16
 // CHECK-NEXT: [[REG780:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG740]], align 16
 // CHECK-NEXT: [[REG781:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG744]], align 16
 // CHECK-NEXT: [[REG782:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_pack(int vector[4], int vector[4])(<4 x i32> [[REG780]], <4 x i32> [[REG781]])
 // CHECK-NEXT: [[REG783:[0-9a-zA-Z_%.]+]] = bitcast <8 x i16> [[REG782]] to <2 x i64>
 // CHECK-NEXT: ret <2 x i64> [[REG783]]
 
 // CHECK: define available_externally i64 @_mm_mulhrs_pi16(i64 [[REG784:[0-9a-zA-Z_%.]+]], i64 [[REG785:[0-9a-zA-Z_%.]+]])

 // CHECK-NEXT: [[REG807:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG806]], align 16
 // CHECK-NEXT: [[REG808:[0-9a-zA-Z_%.]+]] = bitcast <4 x i32> [[REG807]] to <8 x i16>
 // CHECK-NEXT: [[REG809:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_unpackh(short vector[8])(<8 x i16> [[REG808]])
 // CHECK-NEXT: store <4 x i32> [[REG809]], <4 x i32>* [[REG806]], align 16
 // CHECK-NEXT: [[REG810:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG795]], align 16
 // CHECK-NEXT: [[REG811:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG806]], align 16
 // CHECK-NEXT: [[REG812:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_mul(int vector[4], int vector[4])(<4 x i32> [[REG810]], <4 x i32> [[REG811]])
 // CHECK-NEXT: store <4 x i32> [[REG812]], <4 x i32>* [[REG795]], align 16
-// CHECK-NEXT: [[REG813:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splats(unsigned int)(i32 zeroext 14)
-// CHECK-NEXT: store <4 x i32> [[REG813]], <4 x i32>* [[REG814:[0-9a-zA-Z_%.]+]], align 16
+// CHECK-NEXT: store <4 x i32> <i32 14, i32 14, i32 14, i32 14>, <4 x i32>* [[REG814:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG815:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG795]], align 16
-// CHECK-NEXT: [[REG816:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG814]], align 16
-// CHECK-NEXT: [[REG817:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sr(int vector[4], unsigned int vector[4])(<4 x i32> [[REG815]], <4 x i32> [[REG816]])
+// CHECK-NEXT: [[REG817:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sr(int vector[4], unsigned int vector[4])(<4 x i32> [[REG815]], <4 x i32> <i32 14, i32 14, i32 14, i32 14>)
 // CHECK-NEXT: store <4 x i32> [[REG817]], <4 x i32>* [[REG795]], align 16
-// CHECK-NEXT: [[REG818:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_splats(int)(i32 signext 1)
-// CHECK-NEXT: store <4 x i32> [[REG818]], <4 x i32>* [[REG819:[0-9a-zA-Z_%.]+]], align 16
+// CHECK-NEXT: store <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32>* [[REG819:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG820:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG795]], align 16
-// CHECK-NEXT: [[REG821:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG819]], align 16
-// CHECK-NEXT: [[REG822:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_add(int vector[4], int vector[4])(<4 x i32> [[REG820]], <4 x i32> [[REG821]])
+// CHECK-NEXT: [[REG822:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_add(int vector[4], int vector[4])(<4 x i32> [[REG820]], <4 x i32> <i32 1, i32 1, i32 1, i32 1>)
 // CHECK-NEXT: store <4 x i32> [[REG822]], <4 x i32>* [[REG795]], align 16
 // CHECK-NEXT: [[REG823:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG795]], align 16
-// CHECK-NEXT: [[REG824:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG819]], align 16
-// CHECK-NEXT: [[REG825:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sr(int vector[4], unsigned int vector[4])(<4 x i32> [[REG823]], <4 x i32> [[REG824]])
+// CHECK-NEXT: [[REG825:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_sr(int vector[4], unsigned int vector[4])(<4 x i32> [[REG823]], <4 x i32> <i32 1, i32 1, i32 1, i32 1>)
 // CHECK-NEXT: store <4 x i32> [[REG825]], <4 x i32>* [[REG795]], align 16
 // CHECK-NEXT: [[REG826:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG795]], align 16
 // CHECK-NEXT: [[REG827:[0-9a-zA-Z_%.]+]] = load <4 x i32>, <4 x i32>* [[REG806]], align 16
 // CHECK-NEXT: [[REG828:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_pack(int vector[4], int vector[4])(<4 x i32> [[REG826]], <4 x i32> [[REG827]])
 // CHECK-NEXT: store <8 x i16> [[REG828]], <8 x i16>* [[REG829:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG830:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* [[REG829]], align 16
 // CHECK-NEXT: [[REG831:[0-9a-zA-Z_%.]+]] = bitcast <8 x i16> [[REG830]] to <2 x i64>
 // CHECK-NEXT: [[REG832:[0-9a-zA-Z_%.]+]] = extractelement <2 x i64> [[REG831]], i32 0
 // CHECK-NEXT: ret i64 [[REG832]]

clang/test/CodeGen/ppc-xmmintrin.c

-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // REQUIRES: powerpc-registered-target
 
 // RUN: %clang -S -emit-llvm -target powerpc64-unknown-linux-gnu -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \
 // RUN:   -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-BE
 // RUN: %clang -S -emit-llvm -target powerpc64le-unknown-linux-gnu -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \
 // RUN:   -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-LE
 
 #include <xmmintrin.h>

 }
 
 // CHECK-LABEL: @test_avg
 
 // CHECK: define available_externally i64 @_mm_avg_pu16
 // CHECK: store i64 {{[0-9a-zA-Z_%.]+}}, i64* {{[0-9a-zA-Z_%.]+}}, align 8
 // CHECK-NEXT: store i64 {{[0-9a-zA-Z_%.]+}}, i64* {{[0-9a-zA-Z_%.]+}}, align 8
 // CHECK-NEXT: [[REG25:[0-9a-zA-Z_%.]+]] = load i64, i64* {{[0-9a-zA-Z_%.]+}}, align 8
-// CHECK-NEXT: [[REG26:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 [[REG25]])
+// CHECK-NEXT: [[REG26A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 [[REG25]], i32 0
+// CHECK-NEXT: [[REG26:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG26A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG27:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG26]] to <8 x i16>
 // CHECK-NEXT: store <8 x i16> [[REG27]], <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: [[REG28:[0-9a-zA-Z_%.]+]] = load i64, i64* {{[0-9a-zA-Z_%.]+}}, align 8
-// CHECK-NEXT: [[REG29:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 [[REG28]])
+// CHECK-NEXT: [[REG29A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 [[REG28]], i32 0
+// CHECK-NEXT: [[REG29:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG29A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG30:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG29]] to <8 x i16>
 // CHECK-NEXT: store <8 x i16> [[REG30]], <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: [[REG31:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: [[REG32:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: [[REG33:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_avg(unsigned short vector[8], unsigned short vector[8])(<8 x i16> [[REG31]], <8 x i16> [[REG32]])
 // CHECK-NEXT: store <8 x i16> [[REG33]], <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: [[REG34:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: [[REG35:[0-9a-zA-Z_%.]+]] = bitcast <8 x i16> [[REG34]] to <2 x i64>
 // CHECK-NEXT: [[REG36:[0-9a-zA-Z_%.]+]] = extractelement <2 x i64> [[REG35]], i32 0
 // CHECK-NEXT: ret i64 [[REG36]]
 
 // CHECK: define available_externally i64 @_mm_avg_pu8
 // CHECK: store i64 {{[0-9a-zA-Z_%.]+}}, i64* {{[0-9a-zA-Z_%.]+}}, align 8
 // CHECK-NEXT: store i64 {{[0-9a-zA-Z_%.]+}}, i64* {{[0-9a-zA-Z_%.]+}}, align 8
 // CHECK-NEXT: [[REG37:[0-9a-zA-Z_%.]+]] = load i64, i64* {{[0-9a-zA-Z_%.]+}}, align 8
-// CHECK-NEXT: [[REG38:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 [[REG37]])
+// CHECK-NEXT: [[REG38A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 [[REG37]], i32 0
+// CHECK-NEXT: [[REG38:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG38A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG39:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG38]] to <16 x i8>
 // CHECK-NEXT: store <16 x i8> [[REG39]], <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: [[REG40:[0-9a-zA-Z_%.]+]] = load i64, i64* {{[0-9a-zA-Z_%.]+}}, align 8
-// CHECK-NEXT: [[REG41:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 [[REG40]])
+// CHECK-NEXT: [[REG41A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 [[REG40]], i32 0
+// CHECK-NEXT: [[REG41:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG41A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG42:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG41]] to <16 x i8>
 // CHECK-NEXT: store <16 x i8> [[REG42]], <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: [[REG43:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: [[REG44:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: [[REG45:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_avg(unsigned char vector[16], unsigned char vector[16])(<16 x i8> [[REG43]], <16 x i8> [[REG44]])
 // CHECK-NEXT: store <16 x i8> [[REG45]], <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: [[REG46:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: [[REG47:[0-9a-zA-Z_%.]+]] = bitcast <16 x i8> [[REG46]] to <2 x i64>

 // CHECK: [[REG471:[0-9a-zA-Z_%.]+]] = call <4 x float> @_mm_set_ss
 // CHECK-NEXT: ret <4 x float> [[REG471]]
 
 // CHECK: define available_externally <4 x float> @_mm_load1_ps
 // CHECK: [[REG472:[0-9a-zA-Z_%.]+]] = call <4 x float> @_mm_set1_ps
 // CHECK-NEXT: ret <4 x float> [[REG472]]
 
 // CHECK: define available_externally <4 x float> @_mm_loadh_pi
-// CHECK: [[REG473:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)
+// CHECK: [[REG473A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0
+// CHECK-NEXT: [[REG473:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG473A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: store <2 x i64> [[REG473]], <2 x i64>* [[REG474:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG475:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG474]], align 16
 // CHECK-NEXT: [[REG476:[0-9a-zA-Z_%.]+]] = extractelement <2 x i64> [[REG475]], i32 1
 // CHECK-NEXT: [[REG477:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG478:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG479:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> [[REG477]], i64 [[REG476]], i32 1
 // CHECK-NEXT: store <2 x i64> [[REG479]], <2 x i64>* [[REG478]], align 16
 // CHECK-NEXT: [[REG480:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG478]], align 16
 // CHECK-NEXT: [[REG481:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG480]] to <4 x float>
 // CHECK-NEXT: ret <4 x float> [[REG481]]
 
 // CHECK: define available_externally <4 x float> @_mm_loadl_pi
-// CHECK: [[REG482:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)
+// CHECK: [[REG482A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 {{[0-9a-zA-Z_%.]+}}, i32 0
+// CHECK-NEXT: [[REG482:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG482A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: store <2 x i64> [[REG482]], <2 x i64>* [[REG483:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG484:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG483]], align 16
 // CHECK-NEXT: [[REG485:[0-9a-zA-Z_%.]+]] = extractelement <2 x i64> [[REG484]], i32 0
 // CHECK-NEXT: [[REG486:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG487:[0-9a-zA-Z_%.]+]], align 16
 // CHECK-NEXT: [[REG488:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> [[REG486]], i64 [[REG485]], i32 0
 // CHECK-NEXT: store <2 x i64> [[REG488]], <2 x i64>* [[REG487]], align 16
 // CHECK-NEXT: [[REG489:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* [[REG487]], align 16
 // CHECK-NEXT: [[REG490:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG489]] to <4 x float>

 // CHECK-NEXT: [[REG527:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG524]], align 16
 // CHECK-NEXT: [[REG528:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG526]], align 16
 // CHECK-NEXT: call <4 x float> @vec_max(float vector[4], float vector[4])(<4 x float> [[REG527]], <4 x float> [[REG528]])
 // CHECK: [[REG529:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_sel(float vector[4], float vector[4], unsigned int vector[4])(<4 x float> {{[0-9a-zA-Z_%.]+}}, <4 x float> {{[0-9a-zA-Z_%.]+}}, <4 x i32> <i32 -1, i32 0, i32 0, i32 0>)
 // CHECK-NEXT: ret <4 x float> [[REG529]]
 
 // CHECK: define available_externally i64 @_mm_max_pi16
 // CHECK: [[REG530:[0-9a-zA-Z_%.]+]] = load i64, i64* {{[0-9a-zA-Z_%.]+}}, align 8
-// CHECK-NEXT: [[REG531:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 [[REG530]])
+// CHECK-NEXT: [[REG531A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 [[REG530]], i32 0
+// CHECK-NEXT: [[REG531:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG531A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG532:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG531]] to <8 x i16>
 // CHECK-NEXT: store <8 x i16> [[REG532]], <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: [[REG533:[0-9a-zA-Z_%.]+]] = load i64, i64* {{[0-9a-zA-Z_%.]+}}, align 8
-// CHECK-NEXT: [[REG534:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 [[REG533]])
+// CHECK-NEXT: [[REG534A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 [[REG533]], i32 0
+// CHECK-NEXT: [[REG534:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG534A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG535:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG534]] to <8 x i16>
 // CHECK-NEXT: store <8 x i16> [[REG535]], <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: [[REG536:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: [[REG537:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: [[REG538:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_cmpgt(short vector[8], short vector[8])(<8 x i16> [[REG536]], <8 x i16> [[REG537]])
 // CHECK-NEXT: store <8 x i16> [[REG538]], <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: [[REG539:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: [[REG540:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: [[REG541:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: [[REG542:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_sel(short vector[8], short vector[8], bool vector[8])(<8 x i16> [[REG539]], <8 x i16> [[REG540]], <8 x i16> [[REG541]])
 // CHECK-NEXT: store <8 x i16> [[REG542]], <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: [[REG543:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: [[REG544:[0-9a-zA-Z_%.]+]] = bitcast <8 x i16> [[REG543]] to <2 x i64>
 // CHECK-NEXT: [[REG545:[0-9a-zA-Z_%.]+]] = extractelement <2 x i64> [[REG544]], i32 0
 // CHECK-NEXT: ret i64 [[REG545]]
 
 // CHECK: define available_externally i64 @_mm_max_pu8
 // CHECK: [[REG546:[0-9a-zA-Z_%.]+]] = load i64, i64* {{[0-9a-zA-Z_%.]+}}, align 8
-// CHECK-NEXT: [[REG547:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 [[REG546]])
+// CHECK-NEXT: [[REG547A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 [[REG546]], i32 0
+// CHECK-NEXT: [[REG547:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG547A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG548:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG547]] to <16 x i8>
 // CHECK-NEXT: store <16 x i8> [[REG548]], <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: [[REG549:[0-9a-zA-Z_%.]+]] = load i64, i64* {{[0-9a-zA-Z_%.]+}}, align 8
-// CHECK-NEXT: [[REG550:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 [[REG549]])
+// CHECK-NEXT: [[REG550A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 [[REG549]], i32 0
+// CHECK-NEXT: [[REG550:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG550A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG551:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG550]] to <16 x i8>
 // CHECK-NEXT: store <16 x i8> [[REG551]], <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: [[REG552:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: [[REG553:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: [[REG554:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_cmpgt(unsigned char vector[16], unsigned char vector[16])(<16 x i8> [[REG552]], <16 x i8> [[REG553]])
 // CHECK-NEXT: store <16 x i8> [[REG554]], <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: [[REG555:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: [[REG556:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16

 // CHECK-NEXT: [[REG578:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG575]], align 16
 // CHECK-NEXT: [[REG579:[0-9a-zA-Z_%.]+]] = load <4 x float>, <4 x float>* [[REG577]], align 16
 // CHECK-NEXT: call <4 x float> @vec_min(float vector[4], float vector[4])(<4 x float> [[REG578]], <4 x float> [[REG579]])
 // CHECK: [[REG580:[0-9a-zA-Z_%.]+]] = call <4 x float> @vec_sel(float vector[4], float vector[4], unsigned int vector[4])(<4 x float> {{[0-9a-zA-Z_%.]+}}, <4 x float> {{[0-9a-zA-Z_%.]+}}, <4 x i32> <i32 -1, i32 0, i32 0, i32 0>)
 // CHECK-NEXT: ret <4 x float> [[REG580]]
 
 // CHECK: define available_externally i64 @_mm_min_pi16
 // CHECK: [[REG581:[0-9a-zA-Z_%.]+]] = load i64, i64* {{[0-9a-zA-Z_%.]+}}, align 8
-// CHECK-NEXT: [[REG582:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 [[REG581]])
+// CHECK-NEXT: [[REG582A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 [[REG581]], i32 0
+// CHECK-NEXT: [[REG582:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG582A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG583:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG582]] to <8 x i16>
 // CHECK-NEXT: store <8 x i16> [[REG583]], <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: [[REG584:[0-9a-zA-Z_%.]+]] = load i64, i64* {{[0-9a-zA-Z_%.]+}}, align 8
-// CHECK-NEXT: [[REG585:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 [[REG584]])
+// CHECK-NEXT: [[REG585A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 [[REG584]], i32 0
+// CHECK-NEXT: [[REG585:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG585A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG586:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG585]] to <8 x i16>
 // CHECK-NEXT: store <8 x i16> [[REG586]], <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: [[REG587:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: [[REG588:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: [[REG589:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_cmplt(short vector[8], short vector[8])(<8 x i16> [[REG587]], <8 x i16> [[REG588]])
 // CHECK-NEXT: store <8 x i16> [[REG589]], <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: [[REG590:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: [[REG591:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: [[REG592:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: [[REG593:[0-9a-zA-Z_%.]+]] = call <8 x i16> @vec_sel(short vector[8], short vector[8], bool vector[8])(<8 x i16> [[REG590]], <8 x i16> [[REG591]], <8 x i16> [[REG592]])
 // CHECK-NEXT: store <8 x i16> [[REG593]], <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: [[REG594:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: [[REG595:[0-9a-zA-Z_%.]+]] = bitcast <8 x i16> [[REG594]] to <2 x i64>
 // CHECK-NEXT: [[REG596:[0-9a-zA-Z_%.]+]] = extractelement <2 x i64> [[REG595]], i32 0
 // CHECK-NEXT: ret i64 [[REG596]]
 
 // CHECK: define available_externally i64 @_mm_min_pu8
 // CHECK: [[REG597:[0-9a-zA-Z_%.]+]] = load i64, i64* {{[0-9a-zA-Z_%.]+}}, align 8
-// CHECK-NEXT: [[REG598:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 [[REG597]])
+// CHECK-NEXT: [[REG598A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 [[REG597]], i32 0
+// CHECK-NEXT: [[REG598:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG598A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG599:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG598]] to <16 x i8>
 // CHECK-NEXT: store <16 x i8> [[REG599]], <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: [[REG600:[0-9a-zA-Z_%.]+]] = load i64, i64* {{[0-9a-zA-Z_%.]+}}, align 8
-// CHECK-NEXT: [[REG601:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 [[REG600]])
+// CHECK-NEXT: [[REG601A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 [[REG600]], i32 0
+// CHECK-NEXT: [[REG601:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG601A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG602:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG601]] to <16 x i8>
 // CHECK-NEXT: store <16 x i8> [[REG602]], <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: [[REG603:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: [[REG604:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: [[REG605:[0-9a-zA-Z_%.]+]] = call <16 x i8> @vec_cmplt(unsigned char vector[16], unsigned char vector[16])(<16 x i8> [[REG603]], <16 x i8> [[REG604]])
 // CHECK-NEXT: store <16 x i8> [[REG605]], <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: [[REG606:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: [[REG607:[0-9a-zA-Z_%.]+]] = load <16 x i8>, <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16

 // CHECK-NEXT: ret <4 x float> [[REG683]]
 
 // CHECK: define available_externally i64 @_mm_mulhi_pu16(i64 [[REG684:[0-9a-zA-Z_%.]+]], i64 [[REG685:[0-9a-zA-Z_%.]+]])
 // CHECK: store i64 [[REG684]], i64* [[REG686:[0-9a-zA-Z_%.]+]], align 8
 // CHECK-NEXT: store i64 [[REG685]], i64* [[REG687:[0-9a-zA-Z_%.]+]], align 8
 // CHECK-LE-NEXT: store <16 x i8> <i8 2, i8 3, i8 18, i8 19, i8 6, i8 7, i8 22, i8 23, i8 10, i8 11, i8 26, i8 27, i8 14, i8 15, i8 30, i8 31>, <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-BE-NEXT: store <16 x i8> <i8 0, i8 1, i8 16, i8 17, i8 4, i8 5, i8 20, i8 21, i8 0, i8 1, i8 16, i8 17, i8 4, i8 5, i8 20, i8 21>, <16 x i8>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: [[REG688:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG686]], align 8
-// CHECK-NEXT: [[REG689:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 [[REG688]])
+// CHECK-NEXT: [[REG689A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 [[REG688]], i32 0
+// CHECK-NEXT: [[REG689:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG689A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG690:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG689]] to <8 x i16>
 // CHECK-NEXT: store <8 x i16> [[REG690]], <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: [[REG691:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG687]], align 8
-// CHECK-NEXT: [[REG692:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 [[REG691]])
+// CHECK-NEXT: [[REG692A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 [[REG691]], i32 0
+// CHECK-NEXT: [[REG692:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG692A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: [[REG693:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG692]] to <8 x i16>
 // CHECK-NEXT: store <8 x i16> [[REG693]], <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: [[REG694:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: [[REG695:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: [[REG696:[0-9a-zA-Z_%.]+]] = call <4 x i32> @vec_vmuleuh(<8 x i16> [[REG694]], <8 x i16> [[REG695]])
 // CHECK-NEXT: store <4 x i32> [[REG696]], <4 x i32>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: [[REG697:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: [[REG698:[0-9a-zA-Z_%.]+]] = load <8 x i16>, <8 x i16>* {{[0-9a-zA-Z_%.]+}}, align 16

 // CHECK-NEXT: [[REG864:[0-9a-zA-Z_%.]+]] = getelementptr inbounds [4 x i16], [4 x i16]* @_mm_shuffle_pi16.permute_selectors, i64 0, i64 [[REG863]]
 // CHECK-NEXT: [[REG865:[0-9a-zA-Z_%.]+]] = load i16, i16* [[REG864]], align 2
 // CHECK-NEXT: [[REG866:[0-9a-zA-Z_%.]+]] = bitcast {{[0-9a-zA-Z_%.]+}}* {{[0-9a-zA-Z_%.]+}} to [4 x i16]*
 // CHECK-LE-NEXT: [[REG867:[0-9a-zA-Z_%.]+]] = getelementptr inbounds [4 x i16], [4 x i16]* [[REG866]], i64 0, i64 3
 // CHECK-BE-NEXT: [[REG867:[0-9a-zA-Z_%.]+]] = getelementptr inbounds [4 x i16], [4 x i16]* [[REG866]], i64 0, i64 0
 // CHECK-NEXT: store i16 [[REG865]], i16* [[REG867]]
 // CHECK-NEXT: [[REG868:[0-9a-zA-Z_%.]+]] = bitcast {{[0-9a-zA-Z_%.]+}}* {{[0-9a-zA-Z_%.]+}} to i64*
 // CHECK-NEXT: [[REG869:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG868]], align 8
-// CHECK-NEXT: [[REG870:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 [[REG869]])
+// CHECK-NEXT: [[REG870A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 [[REG869]], i32 0
+// CHECK-NEXT: [[REG870:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG870A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: store <2 x i64> [[REG870]], <2 x i64>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: [[REG871:[0-9a-zA-Z_%.]+]] = load i64, i64* [[REG831]], align 8
-// CHECK-NEXT: [[REG872:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_splats(unsigned long long)(i64 [[REG871]])
+// CHECK-NEXT: [[REG872A:[0-9a-zA-Z_%.]+]] = insertelement <2 x i64> undef, i64 [[REG871]], i32 0
+// CHECK-NEXT: [[REG872:[0-9a-zA-Z_%.]+]]  = shufflevector <2 x i64> [[REG872A]], <2 x i64> undef, <2 x i32> zeroinitializer
 // CHECK-NEXT: store <2 x i64> [[REG872]], <2 x i64>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: [[REG873:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: [[REG874:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: [[REG875:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: [[REG876:[0-9a-zA-Z_%.]+]] = bitcast <2 x i64> [[REG875]] to <16 x i8>
 // CHECK-NEXT: [[REG877:[0-9a-zA-Z_%.]+]] = call <2 x i64> @vec_perm(unsigned long long vector[2], unsigned long long vector[2], unsigned char vector[16])(<2 x i64> [[REG873]], <2 x i64> [[REG874]], <16 x i8> [[REG876]])
 // CHECK-NEXT: store <2 x i64> [[REG877]], <2 x i64>* {{[0-9a-zA-Z_%.]+}}, align 16
 // CHECK-NEXT: [[REG878:[0-9a-zA-Z_%.]+]] = load <2 x i64>, <2 x i64>* {{[0-9a-zA-Z_%.]+}}, align 16

clang/test/CodeGen/pr44276.c

+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: powerpc-registered-target
+// RUN: %clang -S -emit-llvm -target powerpc64-unknown-unknown -mcpu=pwr8 %s -o - | FileCheck %s
+
+// Check that this compiles
+
+#include <altivec.h>
+
+// CHECK-LABEL: @test(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    ret void
+//
+void test() {
+  static vector unsigned char a = vec_splats('1');
+  static vector signed char b = vec_splats((signed char)'1');
+  static vector unsigned short c = vec_splats(1U);
+  static vector signed short d = vec_splats(1);
+  static vector unsigned int e = vec_splats(1U);
+  static vector signed int f = vec_splats(1);
+  static vector float g = vec_splats(1.0f);
+  static vector unsigned long long h = vec_splats(1ULL);
+  static vector signed long long i = vec_splats(1LL);
+  static vector double j = vec_splats(1.0);
+  static vector unsigned __int128 k = vec_splats((__int128)1);
+  static vector signed __int128 l = vec_splats((__int128)1);
+}