[ARM] select is not lowered in branching

[kamleshbhalui]

Summary

for test case please see at https://godbolt.org/z/XY5iTx

instruction vadd.f64 is executed even when if condition is false.
later we ignore the result but we ended up setting fp exception bit,
which breaks posix conformance.
This behavior is pops up when optimization enabled.

As part of this fix conversion of select to branching instruction is enabled.

[kamleshbhalui]

fixed failing testcase.

[kamleshbhalui]

-ftrapping-math will do the work.
so abandoning it.

llvm/lib/Target/ARM/ARMISelLowering.cpp

case ARM::STRH_preidx: {
     }
     MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(NewOpc));
     for (unsigned i = 0; i < MI.getNumOperands(); ++i)
       MIB.add(MI.getOperand(i));
     MI.eraseFromParent();
     return BB;
   }
 
+  case ARM::VMOVDcc:
   case ARM::tMOVCCr_pseudo: {
     // To "insert" a SELECT_CC instruction, we actually have to insert the
     // diamond control-flow pattern.  The incoming instruction knows the
     // destination vreg to set, the condition code register to branch on, the
     // true/false values to select between, and a branch opcode to use.
     const BasicBlock *LLVM_BB = BB->getBasicBlock();
     MachineFunction::iterator It = ++BB->getIterator();
 
case ARM::tMOVCCr_pseudo: {
     // Transfer the remainder of BB and its successor edges to sinkMBB.
     sinkMBB->splice(sinkMBB->begin(), BB,
                     std::next(MachineBasicBlock::iterator(MI)), BB->end());
     sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
 
     BB->addSuccessor(copy0MBB);
     BB->addSuccessor(sinkMBB);
 
-    BuildMI(BB, dl, TII->get(ARM::tBcc))
-        .addMBB(sinkMBB)
+
+    BuildMI(BB, dl,
+           Subtarget->isThumb() ? TII->get(ARM::tBcc) : TII->get(ARM::Bcc))       .addMBB(sinkMBB)
         .addImm(MI.getOperand(3).getImm())
         .addReg(MI.getOperand(4).getReg());
 
     //  copy0MBB:
     //   %FalseValue = ...
     //   # fallthrough to sinkMBB
     BB = copy0MBB;
 

llvm/lib/Target/ARM/ARMInstrVFP.td

def : Pat<(fneg (f16 (fma HPR:$Sn, (fneg HPR:$Sm), HPR:$Sdin))),
           (VFNMSH HPR:$Sdin, HPR:$Sn, HPR:$Sm)>,
       Requires<[HasFullFP16]>;
 
 //===----------------------------------------------------------------------===//
 // FP Conditional moves.
 //
 
 let hasSideEffects = 0 in {
+let usesCustomInserter = 1 in {
 def VMOVDcc  : PseudoInst<(outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm, cmovpred:$p),
                     IIC_fpUNA64,
                     [(set (f64 DPR:$Dd),
                           (ARMcmov DPR:$Dn, DPR:$Dm, cmovpred:$p))]>,
                RegConstraint<"$Dn = $Dd">, Requires<[HasFPRegs64]>;
+}
 
 def VMOVScc  : PseudoInst<(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm, cmovpred:$p),
                     IIC_fpUNA32,
                     [(set (f32 SPR:$Sd),
                           (ARMcmov SPR:$Sn, SPR:$Sm, cmovpred:$p))]>,
                RegConstraint<"$Sn = $Sd">, Requires<[HasFPRegs]>;
 
 def VMOVHcc  : PseudoInst<(outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm, cmovpred:$p),

llvm/test/CodeGen/ARM/select.ll

entry:
     ret i32 %tmp1.s
 }
 
 define double @f7(double %a, double %b) {
 ;CHECK-LABEL: f7:
 ;CHECK: movmi
 ;CHECK: movpl
 ;CHECK-VFP-LABEL: f7:
-;CHECK-VFP: vmovmi
+;CHECK-VFP: vldrmi
     %tmp = fcmp olt double %a, 1.234e+00
     %tmp1 = select i1 %tmp, double -1.000e+00, double %b
     ret double %tmp1
 }
 
 ; <rdar://problem/7260094>
 ;
 ; We used to generate really horrible code for this function. The main cause was

 ; CHECK: subs [[ZERO:r[0-9]+]], [[HI]], [[LO]], asr #31
 ; CHECK: movne [[ZERO]], #1
   %prod = call { i32, i1 } @llvm.smul.with.overflow.i32(i32 %in1, i32 %in2)
   %overflow = extractvalue { i32, i1 } %prod, 1
   ret i1 %overflow
 }
 
 declare { i32, i1 } @llvm.smul.with.overflow.i32(i32, i32)
+
+@ff = dso_local local_unnamed_addr global double 0x7FEFFFFFFFFFFFFF, align 8
+@xx = dso_local local_unnamed_addr global i32 16777216, align 4
+
+; CHECK-VFP-LABEL: f13:
+define double @f13() {
+; CHECK-VFP: %bb.1
+; CHECK-VFP-NEXT: vadd
+entry:
+  %0 = load double, double* @ff, align 8
+  %1 = load i32, i32* @xx, align 4
+  %cmp = icmp slt i32 %1, 1048576
+  %mul = fmul double %0, 2.000000e+00
+  %spec.select = select i1 %cmp, double %mul, double %0
+  ret double %spec.select
+}

llvm/test/CodeGen/Thumb2/float-ops.ll

 ; SP: ands r0, r0, #1
 ; SP-DAG: vmov [[ALO:r[0-9]+]], [[AHI:r[0-9]+]], d0
 ; SP-DAG: vmov [[BLO:r[0-9]+]], [[BHI:r[0-9]+]], d1
 ; SP: itt ne
 ; SP-DAG: movne [[BLO]], [[ALO]]
 ; SP-DAG: movne [[BHI]], [[AHI]]
 ; SP: vmov d0, [[BLO]], [[BHI]]
 ; DP: lsls   r0, r0, #31
-; VFP4-DP: vmovne.f64      d1, d0
-; VFP4-DP: vmov.f64        d0, d1
+; VFP4-DP: vmoveq.f64      d0, d1
 ; FP-ARMV8: vseleq.f64      d0, d1, d0
   %1 = select i1 %c, double %a, double %b
   ret double %1
 }