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Differential D80460

[AArch64][GlobalISel] When generating SUBS for compares, don't write to wzr/xzr.
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Authored by aemerson on May 22 2020, 3:34 PM.

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paquette
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rG99660217e930: [AArch64][GlobalISel] When generating SUBS for compares, don't write to wzr/xzr.
Summary

Although writing to wzr/xzr is correct since we don't care about the result of the sub, only the flags, doing so causes tail merge blocks to fail.

Writing to an unused virtual register instead allows the optimization to fire, improving performance significantly on 256.bzip2.

Diff Detail

Event Timeline

aemerson created this revision.May 22 2020, 3:34 PM
Herald added subscribers: danielkiss, hiraditya, kristof.beyls, rovka. · View Herald TranscriptMay 22 2020, 3:34 PM
paquette added inline comments.May 22 2020, 3:36 PM
llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
3702

Can probably remove this

3705

Can probably remove this

Harbormaster completed remote builds in B57686: Diff 265811.May 22 2020, 4:06 PM
aemerson updated this revision to Diff 265820.May 22 2020, 5:18 PM

Deleted old lines.

Harbormaster completed remote builds in B57693: Diff 265820.May 22 2020, 6:16 PM
paquette accepted this revision.May 22 2020, 9:46 PM

LGTM

This revision is now accepted and ready to land.May 22 2020, 9:46 PM
Closed by commit rG99660217e930: [AArch64][GlobalISel] When generating SUBS for compares, don't write to wzr/xzr. (authored by aemerson). · Explain WhyMay 23 2020, 11:57 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
lib/
Target/
AArch64/
4 lines
test/
CodeGen/
AArch64/
GlobalISel/
10 lines
8 lines
2 lines
6 lines
2 lines
2 lines

Diff 265820

llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp

Show First 20 Lines • Show All 3,693 Lines • ▼ Show 20 LinesAArch64InstructionSelector::emitIntegerCompare(
unsigned CmpOpc = 0; unsigned CmpOpc = 0;
Register ZReg; Register ZReg;
LLT CmpTy = MRI.getType(LHS.getReg()); LLT CmpTy = MRI.getType(LHS.getReg());
assert((CmpTy.isScalar() || CmpTy.isPointer()) && assert((CmpTy.isScalar() || CmpTy.isPointer()) &&
"Expected scalar or pointer"); "Expected scalar or pointer");
if (CmpTy == LLT::scalar(32)) { if (CmpTy == LLT::scalar(32)) {
CmpOpc = AArch64::SUBSWrr; CmpOpc = AArch64::SUBSWrr;
ZReg = AArch64::WZR; ZReg = MRI.createVirtualRegister(&AArch64::GPR32RegClass);
paquetteUnsubmitted
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Can probably remove this

paquette: Can probably remove this
} else if (CmpTy == LLT::scalar(64) || CmpTy.isPointer()) { } else if (CmpTy == LLT::scalar(64) || CmpTy.isPointer()) {
CmpOpc = AArch64::SUBSXrr; CmpOpc = AArch64::SUBSXrr;
ZReg = AArch64::XZR; ZReg = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
paquetteUnsubmitted
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Can probably remove this

paquette: Can probably remove this
} else { } else {
return {nullptr, CmpInst::Predicate::BAD_ICMP_PREDICATE}; return {nullptr, CmpInst::Predicate::BAD_ICMP_PREDICATE};
} }
// Try to match immediate forms. // Try to match immediate forms.
MachineInstr *ImmedCmp = MachineInstr *ImmedCmp =
tryOptArithImmedIntegerCompare(LHS, RHS, Predicate, MIRBuilder); tryOptArithImmedIntegerCompare(LHS, RHS, Predicate, MIRBuilder);
if (ImmedCmp) if (ImmedCmp)
▲ Show 20 Lines • Show All 1,887 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-compare.mir

Show First 20 Lines • Show All 105 Lines • ▼ Show 20 Lines bb.0:
; CHECK-LABEL: name: no_cmn_s32_rhs ; CHECK-LABEL: name: no_cmn_s32_rhs
; CHECK: liveins: $w0, $w1 ; CHECK: liveins: $w0, $w1
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[COPY2]], [[COPY1]], implicit-def $nzcv ; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[COPY2]], [[COPY1]], implicit-def $nzcv
; CHECK: $wzr = SUBSWrr [[COPY]], [[SUBSWrr]], implicit-def $nzcv ; CHECK: [[SUBSWrr1:%[0-9]+]]:gpr32 = SUBSWrr [[COPY]], [[SUBSWrr]], implicit-def $nzcv
; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm]], [[COPY2]], 11, implicit $nzcv ; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm]], [[COPY2]], 11, implicit $nzcv
; CHECK: $w0 = COPY [[CSELWr]] ; CHECK: $w0 = COPY [[CSELWr]]
; CHECK: RET_ReallyLR implicit $w0 ; CHECK: RET_ReallyLR implicit $w0
%0:gpr(s32) = COPY $w0 %0:gpr(s32) = COPY $w0
%1:gpr(s32) = COPY $w1 %1:gpr(s32) = COPY $w1
%2:gpr(s32) = G_CONSTANT i32 0 %2:gpr(s32) = G_CONSTANT i32 0
%6:gpr(s32) = G_CONSTANT i32 1 %6:gpr(s32) = G_CONSTANT i32 1
%3:gpr(s32) = G_SUB %2, %1 %3:gpr(s32) = G_SUB %2, %1
Show All 16 Lines bb.0:
; CHECK-LABEL: name: no_cmn_s32_lhs ; CHECK-LABEL: name: no_cmn_s32_lhs
; CHECK: liveins: $w0, $w1 ; CHECK: liveins: $w0, $w1
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[COPY2]], [[COPY]], implicit-def $nzcv ; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[COPY2]], [[COPY]], implicit-def $nzcv
; CHECK: $wzr = SUBSWrr [[SUBSWrr]], [[COPY1]], implicit-def $nzcv ; CHECK: [[SUBSWrr1:%[0-9]+]]:gpr32 = SUBSWrr [[SUBSWrr]], [[COPY1]], implicit-def $nzcv
; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm]], [[COPY2]], 11, implicit $nzcv ; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[MOVi32imm]], [[COPY2]], 11, implicit $nzcv
; CHECK: $w0 = COPY [[CSELWr]] ; CHECK: $w0 = COPY [[CSELWr]]
; CHECK: RET_ReallyLR implicit $w0 ; CHECK: RET_ReallyLR implicit $w0
%0:gpr(s32) = COPY $w0 %0:gpr(s32) = COPY $w0
%1:gpr(s32) = COPY $w1 %1:gpr(s32) = COPY $w1
%2:gpr(s32) = G_CONSTANT i32 0 %2:gpr(s32) = G_CONSTANT i32 0
%6:gpr(s32) = G_CONSTANT i32 1 %6:gpr(s32) = G_CONSTANT i32 1
%3:gpr(s32) = G_SUB %2, %0 %3:gpr(s32) = G_SUB %2, %0
▲ Show 20 Lines • Show All 83 Lines • ▼ Show 20 Lines bb.0:
; CHECK-LABEL: name: no_cmn_s64_rhs ; CHECK-LABEL: name: no_cmn_s64_rhs
; CHECK: liveins: $x0, $x1 ; CHECK: liveins: $x0, $x1
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK: [[COPY2:%[0-9]+]]:gpr64 = COPY $xzr ; CHECK: [[COPY2:%[0-9]+]]:gpr64 = COPY $xzr
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
; CHECK: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY2]], [[COPY1]], implicit-def $nzcv ; CHECK: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY2]], [[COPY1]], implicit-def $nzcv
; CHECK: $xzr = SUBSXrr [[COPY]], [[SUBSXrr]], implicit-def $nzcv ; CHECK: [[SUBSXrr1:%[0-9]+]]:gpr64 = SUBSXrr [[COPY]], [[SUBSXrr]], implicit-def $nzcv
; CHECK: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[SUBREG_TO_REG]], [[COPY2]], 11, implicit $nzcv ; CHECK: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[SUBREG_TO_REG]], [[COPY2]], 11, implicit $nzcv
; CHECK: $x0 = COPY [[CSELXr]] ; CHECK: $x0 = COPY [[CSELXr]]
; CHECK: RET_ReallyLR implicit $x0 ; CHECK: RET_ReallyLR implicit $x0
%0:gpr(s64) = COPY $x0 %0:gpr(s64) = COPY $x0
%1:gpr(s64) = COPY $x1 %1:gpr(s64) = COPY $x1
%2:gpr(s64) = G_CONSTANT i64 0 %2:gpr(s64) = G_CONSTANT i64 0
%6:gpr(s64) = G_CONSTANT i64 1 %6:gpr(s64) = G_CONSTANT i64 1
%3:gpr(s64) = G_SUB %2, %1 %3:gpr(s64) = G_SUB %2, %1
Show All 17 Lines bb.0:
; CHECK-LABEL: name: no_cmn_s64_lhs ; CHECK-LABEL: name: no_cmn_s64_lhs
; CHECK: liveins: $x0, $x1 ; CHECK: liveins: $x0, $x1
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK: [[COPY2:%[0-9]+]]:gpr64 = COPY $xzr ; CHECK: [[COPY2:%[0-9]+]]:gpr64 = COPY $xzr
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
; CHECK: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY2]], [[COPY]], implicit-def $nzcv ; CHECK: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY2]], [[COPY]], implicit-def $nzcv
; CHECK: $xzr = SUBSXrr [[SUBSXrr]], [[COPY1]], implicit-def $nzcv ; CHECK: [[SUBSXrr1:%[0-9]+]]:gpr64 = SUBSXrr [[SUBSXrr]], [[COPY1]], implicit-def $nzcv
; CHECK: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[SUBREG_TO_REG]], [[COPY2]], 11, implicit $nzcv ; CHECK: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[SUBREG_TO_REG]], [[COPY2]], 11, implicit $nzcv
; CHECK: $x0 = COPY [[CSELXr]] ; CHECK: $x0 = COPY [[CSELXr]]
; CHECK: RET_ReallyLR implicit $x0 ; CHECK: RET_ReallyLR implicit $x0
%0:gpr(s64) = COPY $x0 %0:gpr(s64) = COPY $x0
%1:gpr(s64) = COPY $x1 %1:gpr(s64) = COPY $x1
%2:gpr(s64) = G_CONSTANT i64 0 %2:gpr(s64) = G_CONSTANT i64 0
%6:gpr(s64) = G_CONSTANT i64 1 %6:gpr(s64) = G_CONSTANT i64 1
%3:gpr(s64) = G_SUB %2, %0 %3:gpr(s64) = G_SUB %2, %0
▲ Show 20 Lines • Show All 203 Lines • ▼ Show 20 Lines
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $x0, $x1 liveins: $x0, $x1
; CHECK-LABEL: name: test_physreg_copy ; CHECK-LABEL: name: test_physreg_copy
; CHECK: liveins: $x0, $x1 ; CHECK: liveins: $x0, $x1
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK: $xzr = SUBSXrr [[COPY]], [[COPY1]], implicit-def $nzcv ; CHECK: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY]], [[COPY1]], implicit-def $nzcv
; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
; CHECK: $w0 = COPY [[CSINCWr]] ; CHECK: $w0 = COPY [[CSINCWr]]
; CHECK: RET_ReallyLR implicit $x0 ; CHECK: RET_ReallyLR implicit $x0
%0:gpr(s64) = COPY $x0 %0:gpr(s64) = COPY $x0
%1:gpr(s64) = COPY $x1 %1:gpr(s64) = COPY $x1
; When we find the defs of the LHS and RHS of the compare, we walk over ; When we find the defs of the LHS and RHS of the compare, we walk over
; copies. Make sure that we don't crash when we hit a copy from a physical ; copies. Make sure that we don't crash when we hit a copy from a physical
; register. ; register.
%7:gpr(s32) = G_ICMP intpred(eq), %0, %1 %7:gpr(s32) = G_ICMP intpred(eq), %0, %1
$w0 = COPY %7(s32) $w0 = COPY %7(s32)
RET_ReallyLR implicit $x0 RET_ReallyLR implicit $x0

llvm/test/CodeGen/AArch64/GlobalISel/select-arith-immed-compare.mir

Show First 20 Lines • Show All 456 Lines • ▼ Show 20 Lines bb.0:
; ;
; x slt c => x sle c - 1 ; x slt c => x sle c - 1
; x sge c => x sgt c - 1 ; x sge c => x sgt c - 1
; CHECK-LABEL: name: no_opt_int32_min ; CHECK-LABEL: name: no_opt_int32_min
; CHECK: liveins: $w0 ; CHECK: liveins: $w0
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm -2147483648 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm -2147483648
; CHECK: $wzr = SUBSWrr [[COPY]], [[MOVi32imm]], implicit-def $nzcv ; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[COPY]], [[MOVi32imm]], implicit-def $nzcv
; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv
; CHECK: [[ANDWri:%[0-9]+]]:gpr32sp = ANDWri [[CSINCWr]], 0 ; CHECK: [[ANDWri:%[0-9]+]]:gpr32sp = ANDWri [[CSINCWr]], 0
; CHECK: $w0 = COPY [[ANDWri]] ; CHECK: $w0 = COPY [[ANDWri]]
; CHECK: RET_ReallyLR implicit $w0 ; CHECK: RET_ReallyLR implicit $w0
%0:gpr(s32) = COPY $w0 %0:gpr(s32) = COPY $w0
%1:gpr(s32) = G_CONSTANT i32 -2147483648 %1:gpr(s32) = G_CONSTANT i32 -2147483648
%4:gpr(s32) = G_ICMP intpred(slt), %0(s32), %1 %4:gpr(s32) = G_ICMP intpred(slt), %0(s32), %1
%5:gpr(s32) = G_CONSTANT i32 1 %5:gpr(s32) = G_CONSTANT i32 1
Show All 19 Lines bb.0:
; ;
; x slt c => x sle c - 1 ; x slt c => x sle c - 1
; x sge c => x sgt c - 1 ; x sge c => x sgt c - 1
; CHECK-LABEL: name: no_opt_int64_min ; CHECK-LABEL: name: no_opt_int64_min
; CHECK: liveins: $x0 ; CHECK: liveins: $x0
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm -9223372036854775808 ; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm -9223372036854775808
; CHECK: $xzr = SUBSXrr [[COPY]], [[MOVi64imm]], implicit-def $nzcv ; CHECK: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY]], [[MOVi64imm]], implicit-def $nzcv
; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv
; CHECK: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gpr64 = INSERT_SUBREG [[DEF]], [[CSINCWr]], %subreg.sub_32 ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gpr64 = INSERT_SUBREG [[DEF]], [[CSINCWr]], %subreg.sub_32
; CHECK: [[ANDXri:%[0-9]+]]:gpr64sp = ANDXri [[INSERT_SUBREG]], 4096 ; CHECK: [[ANDXri:%[0-9]+]]:gpr64sp = ANDXri [[INSERT_SUBREG]], 4096
; CHECK: $x0 = COPY [[ANDXri]] ; CHECK: $x0 = COPY [[ANDXri]]
; CHECK: RET_ReallyLR implicit $x0 ; CHECK: RET_ReallyLR implicit $x0
%0:gpr(s64) = COPY $x0 %0:gpr(s64) = COPY $x0
%1:gpr(s64) = G_CONSTANT i64 -9223372036854775808 %1:gpr(s64) = G_CONSTANT i64 -9223372036854775808
Show All 22 Lines bb.0:
; ;
; x slt c => x sle c - 1 ; x slt c => x sle c - 1
; x sge c => x sgt c - 1 ; x sge c => x sgt c - 1
; CHECK-LABEL: name: no_opt_int32_max ; CHECK-LABEL: name: no_opt_int32_max
; CHECK: liveins: $w0 ; CHECK: liveins: $w0
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 2147483647 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 2147483647
; CHECK: $wzr = SUBSWrr [[COPY]], [[MOVi32imm]], implicit-def $nzcv ; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[COPY]], [[MOVi32imm]], implicit-def $nzcv
; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv
; CHECK: [[ANDWri:%[0-9]+]]:gpr32sp = ANDWri [[CSINCWr]], 0 ; CHECK: [[ANDWri:%[0-9]+]]:gpr32sp = ANDWri [[CSINCWr]], 0
; CHECK: $w0 = COPY [[ANDWri]] ; CHECK: $w0 = COPY [[ANDWri]]
; CHECK: RET_ReallyLR implicit $w0 ; CHECK: RET_ReallyLR implicit $w0
%0:gpr(s32) = COPY $w0 %0:gpr(s32) = COPY $w0
%1:gpr(s32) = G_CONSTANT i32 2147483647 %1:gpr(s32) = G_CONSTANT i32 2147483647
%4:gpr(s32) = G_ICMP intpred(sle), %0(s32), %1 %4:gpr(s32) = G_ICMP intpred(sle), %0(s32), %1
%5:gpr(s32) = G_CONSTANT i32 1 %5:gpr(s32) = G_CONSTANT i32 1
Show All 20 Lines bb.0:
; x slt c => x sle c - 1 ; x slt c => x sle c - 1
; x sge c => x sgt c - 1 ; x sge c => x sgt c - 1
; CHECK-LABEL: name: no_opt_int64_max ; CHECK-LABEL: name: no_opt_int64_max
; CHECK: liveins: $x0 ; CHECK: liveins: $x0
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm 9223372036854775807 ; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm 9223372036854775807
; CHECK: $xzr = SUBSXrr [[COPY]], [[MOVi64imm]], implicit-def $nzcv ; CHECK: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY]], [[MOVi64imm]], implicit-def $nzcv
; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 12, implicit $nzcv
; CHECK: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gpr64 = INSERT_SUBREG [[DEF]], [[CSINCWr]], %subreg.sub_32 ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gpr64 = INSERT_SUBREG [[DEF]], [[CSINCWr]], %subreg.sub_32
; CHECK: [[ANDXri:%[0-9]+]]:gpr64sp = ANDXri [[INSERT_SUBREG]], 4096 ; CHECK: [[ANDXri:%[0-9]+]]:gpr64sp = ANDXri [[INSERT_SUBREG]], 4096
; CHECK: $x0 = COPY [[ANDXri]] ; CHECK: $x0 = COPY [[ANDXri]]
; CHECK: RET_ReallyLR implicit $x0 ; CHECK: RET_ReallyLR implicit $x0
%0:gpr(s64) = COPY $x0 %0:gpr(s64) = COPY $x0
%1:gpr(s64) = G_CONSTANT i64 9223372036854775807 %1:gpr(s64) = G_CONSTANT i64 9223372036854775807
▲ Show 20 Lines • Show All 45 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/GlobalISel/select-cmp.mir

Show First 20 Lines • Show All 54 Lines • ▼ Show 20 Linesbody: |
bb.1: bb.1:
liveins: $x0 liveins: $x0
; CHECK-LABEL: name: cmp_imm_out_of_range ; CHECK-LABEL: name: cmp_imm_out_of_range
; CHECK: liveins: $x0 ; CHECK: liveins: $x0
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 13132 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 13132
; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
; CHECK: $xzr = SUBSXrr [[COPY]], [[SUBREG_TO_REG]], implicit-def $nzcv ; CHECK: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY]], [[SUBREG_TO_REG]], implicit-def $nzcv
; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
; CHECK: $w0 = COPY [[CSINCWr]] ; CHECK: $w0 = COPY [[CSINCWr]]
; CHECK: RET_ReallyLR implicit $w0 ; CHECK: RET_ReallyLR implicit $w0
%0:gpr(s64) = COPY $x0 %0:gpr(s64) = COPY $x0
%1:gpr(s64) = G_CONSTANT i64 13132 %1:gpr(s64) = G_CONSTANT i64 13132
%5:gpr(s32) = G_ICMP intpred(eq), %0(s64), %1 %5:gpr(s32) = G_ICMP intpred(eq), %0(s64), %1
$w0 = COPY %5(s32) $w0 = COPY %5(s32)
RET_ReallyLR implicit $w0 RET_ReallyLR implicit $w0
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llvm/test/CodeGen/AArch64/GlobalISel/select.mir

Show First 20 Lines • Show All 193 Lines • ▼ Show 20 Linesregisters:
- { id: 6, class: gpr } - { id: 6, class: gpr }
- { id: 7, class: gpr } - { id: 7, class: gpr }
- { id: 8, class: gpr } - { id: 8, class: gpr }
- { id: 9, class: gpr } - { id: 9, class: gpr }
- { id: 10, class: gpr } - { id: 10, class: gpr }
- { id: 11, class: gpr } - { id: 11, class: gpr }
# CHECK: body: # CHECK: body:
# CHECK: $wzr = SUBSWrr %0, %0, implicit-def $nzcv # CHECK: SUBSWrr %0, %0, implicit-def $nzcv
# CHECK: %1:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv # CHECK: %1:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
# CHECK: $xzr = SUBSXrr %2, %2, implicit-def $nzcv # CHECK: SUBSXrr %2, %2, implicit-def $nzcv
# CHECK: %3:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv # CHECK: %3:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv
# CHECK: $xzr = SUBSXrr %4, %4, implicit-def $nzcv # CHECK: SUBSXrr %4, %4, implicit-def $nzcv
# CHECK: %5:gpr32 = CSINCWr $wzr, $wzr, 0, implicit $nzcv # CHECK: %5:gpr32 = CSINCWr $wzr, $wzr, 0, implicit $nzcv
body: | body: |
bb.0: bb.0:
liveins: $w0, $x0 liveins: $w0, $x0
%0(s32) = COPY $w0 %0(s32) = COPY $w0
%1(s32) = G_ICMP intpred(eq), %0, %0 %1(s32) = G_ICMP intpred(eq), %0, %0
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llvm/test/CodeGen/AArch64/GlobalISel/tbnz-slt.mir

Show First 20 Lines • Show All 126 Lines • ▼ Show 20 Lines
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
; CHECK-LABEL: name: dont_commute ; CHECK-LABEL: name: dont_commute
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000) ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
; CHECK: %copy:gpr64 = COPY $x0 ; CHECK: %copy:gpr64 = COPY $x0
; CHECK: %zero:gpr64 = COPY $xzr ; CHECK: %zero:gpr64 = COPY $xzr
; CHECK: $xzr = SUBSXrr %zero, %copy, implicit-def $nzcv ; CHECK: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr %zero, %copy, implicit-def $nzcv
; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 10, implicit $nzcv
; CHECK: TBNZW %cmp, 0, %bb.1 ; CHECK: TBNZW %cmp, 0, %bb.1
; CHECK: B %bb.0 ; CHECK: B %bb.0
; CHECK: bb.1: ; CHECK: bb.1:
; CHECK: RET_ReallyLR ; CHECK: RET_ReallyLR
bb.0: bb.0:
successors: %bb.0, %bb.1 successors: %bb.0, %bb.1
liveins: $x0 liveins: $x0
%copy:gpr(s64) = COPY $x0 %copy:gpr(s64) = COPY $x0
%zero:gpr(s64) = G_CONSTANT i64 0 %zero:gpr(s64) = G_CONSTANT i64 0
%cmp:gpr(s32) = G_ICMP intpred(slt), %zero, %copy(s64) %cmp:gpr(s32) = G_ICMP intpred(slt), %zero, %copy(s64)
%cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32) %cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
G_BRCOND %cmp_trunc(s1), %bb.1 G_BRCOND %cmp_trunc(s1), %bb.1
G_BR %bb.0 G_BR %bb.0
bb.1: bb.1:
RET_ReallyLR RET_ReallyLR

llvm/test/CodeGen/AArch64/GlobalISel/tbz-sgt.mir

Show First 20 Lines • Show All 126 Lines • ▼ Show 20 Lines
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
; CHECK-LABEL: name: dont_commute ; CHECK-LABEL: name: dont_commute
; CHECK: bb.0: ; CHECK: bb.0:
; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000) ; CHECK: successors: %bb.0(0x40000000), %bb.1(0x40000000)
; CHECK: %copy:gpr64 = COPY $x0 ; CHECK: %copy:gpr64 = COPY $x0
; CHECK: %negative_one:gpr64 = MOVi64imm -1 ; CHECK: %negative_one:gpr64 = MOVi64imm -1
; CHECK: $xzr = SUBSXrr %negative_one, %copy, implicit-def $nzcv ; CHECK: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr %negative_one, %copy, implicit-def $nzcv
; CHECK: Bcc 12, %bb.1, implicit $nzcv ; CHECK: Bcc 12, %bb.1, implicit $nzcv
; CHECK: B %bb.0 ; CHECK: B %bb.0
; CHECK: bb.1: ; CHECK: bb.1:
; CHECK: RET_ReallyLR ; CHECK: RET_ReallyLR
bb.0: bb.0:
successors: %bb.0, %bb.1 successors: %bb.0, %bb.1
liveins: $x0 liveins: $x0
%copy:gpr(s64) = COPY $x0 %copy:gpr(s64) = COPY $x0
%negative_one:gpr(s64) = G_CONSTANT i64 -1 %negative_one:gpr(s64) = G_CONSTANT i64 -1
%cmp:gpr(s32) = G_ICMP intpred(sgt), %negative_one, %copy(s64) %cmp:gpr(s32) = G_ICMP intpred(sgt), %negative_one, %copy(s64)
%cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32) %cmp_trunc:gpr(s1) = G_TRUNC %cmp(s32)
G_BRCOND %cmp_trunc(s1), %bb.1 G_BRCOND %cmp_trunc(s1), %bb.1
G_BR %bb.0 G_BR %bb.0
bb.1: bb.1:
RET_ReallyLR RET_ReallyLR