[AArch64] Changes some SchedAlias to WriteRes for Cortex-A57.

[cestes]

Summary

While SchedAliases are a simple way to "map" default SchedWrites
to target-specific ones, the lead to entries in the generatated
AArch64WriteLatencyTable with WriteResourceIds of zero. This does
not affect simple latency and resource lookup, but it does break
SchedReadAdvances when using those SchedWrites. This patch changes
the only two SchedAliases for Cortex-A57 that were also used in
SchedReadAdannces to use WriteRes instead.

[apazos]

I have verified that with this patch the MachineCombiner pass works better and we are able to generate more multiply-add instructions on a57. Before we were missing opportunities due to wrong computation of forwarding latency (e.g., mul instruction that feeds into a madd instruction as its accumulator should have a reduced latency).

[mcrosier]

Ping. :)

[mcrosier]

Dave, Ana and I are confident this is a good patch and seeing as Dave is the code owner, I went ahead and gave the LGTM. If there are any concerns, please comment and I/we will address them ASAP.

Committed in r234594.

lib/Target/AArch64/AArch64SchedA57.td

 
 include "AArch64SchedA57WriteRes.td"
 
 //===----------------------------------------------------------------------===//
 // Map the target-defined scheduler read/write resources and latency for
 // Cortex-A57. The Cortex-A57 types are directly associated with resources, so
 // defining the aliases precludes the need for mapping them using WriteRes. The
 // aliases are sufficient for creating a coarse, working model. As the model
-// evolves, InstRWs will be used to override these SchedAliases.
+// evolves, InstRWs will be used to override some of these SchedAliases.
+//
+// WARNING: Using SchedAliases is convenient and works well for latency and
+//          resource lookup for instructions. However, this creates an entry in
+//          AArch64WriteLatencyTable with a WriteResourceID of 0, breaking
+//          any SchedReadAdvance since the lookup will fail.
 
 def : SchedAlias<WriteImm,   A57Write_1cyc_1I>;
 def : SchedAlias<WriteI,     A57Write_1cyc_1I>;
 def : SchedAlias<WriteISReg, A57Write_2cyc_1M>;
 def : SchedAlias<WriteIEReg, A57Write_2cyc_1M>;
 def : SchedAlias<WriteExtr,  A57Write_1cyc_1I>;
 def : SchedAlias<WriteIS,    A57Write_1cyc_1I>;
 def : SchedAlias<WriteID32,  A57Write_19cyc_1M>;
 def : SchedAlias<WriteID64,  A57Write_35cyc_1M>;
-def : SchedAlias<WriteIM32,  A57Write_3cyc_1M>;
-def : SchedAlias<WriteIM64,  A57Write_5cyc_1M>;
+def : WriteRes<WriteIM32, [A57UnitM]> { let Latency = 3; }
+def : WriteRes<WriteIM64, [A57UnitM]> { let Latency = 5; }
 def : SchedAlias<WriteBr,    A57Write_1cyc_1B>;
 def : SchedAlias<WriteBrReg, A57Write_1cyc_1B>;
 def : SchedAlias<WriteLD,    A57Write_4cyc_1L>;
 def : SchedAlias<WriteST,    A57Write_1cyc_1S>;
 def : SchedAlias<WriteSTP,   A57Write_1cyc_1S>;
 def : SchedAlias<WriteAdr,   A57Write_1cyc_1I>;
 def : SchedAlias<WriteLDIdx, A57Write_4cyc_1I_1L>;
 def : SchedAlias<WriteSTIdx, A57Write_1cyc_1I_1S>;