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cestes (Dave Estes)
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User Since
Feb 14 2014, 2:45 PM (291 w, 5 d)

Recent Activity

Mar 4 2015

cestes updated subscribers of D8043: [AArch64] Adjusts Cortex-A57 machine model to handle zero shift..
Mar 4 2015, 12:13 PM
cestes updated subscribers of D8045: [AArch64] Changes some SchedAlias to WriteRes for Cortex-A57..
Mar 4 2015, 12:13 PM

Mar 3 2015

cestes retitled D8045: [AArch64] Changes some SchedAlias to WriteRes for Cortex-A57. from to [AArch64] Changes some SchedAlias to WriteRes for Cortex-A57..
Mar 3 2015, 2:38 PM
cestes retitled D8043: [AArch64] Adjusts Cortex-A57 machine model to handle zero shift. from to [AArch64] Adjusts Cortex-A57 machine model to handle zero shift..
Mar 3 2015, 2:37 PM

Oct 22 2014

cestes retitled D5908: Generate Loop Fusion Statistics from to Generate Loop Fusion Statistics.
Oct 22 2014, 8:43 AM

Sep 29 2014

cestes closed D5372: [AArch64] Refines the Cortex-A57 Machine Model.

Committed as r218627.

Sep 29 2014, 2:40 PM

Sep 26 2014

cestes added a comment to D5372: [AArch64] Refines the Cortex-A57 Machine Model.

Excellent. Thanks, Jiangning. Your new numbers show a regressions in gap and equake. I'll try to get an equake number, but I do know that we're seeing ~1% gain. Interestingly enough one of the regressions that we're seeing is on twolf, but your device shows a gain. :) Despite the differences, I too think this latest patch looks like a good foundation for future work.

Sep 26 2014, 11:00 AM

Sep 24 2014

cestes added a comment to D5372: [AArch64] Refines the Cortex-A57 Machine Model.

This new patchset moves the model back to out-of-order yet restricts the issue-width to the minimum of the actual issue width and dispatch width as Andy suggested. It brought the Spec2000/2006 numbers back up and even outperformed the original model by a few percent (geomean). It also improved the EEMBC numbers by a percent (geomean). I did see some degradation in individual tests, but nothing horrible. It will take some more detailed analysis to determine the cause there.

Sep 24 2014, 7:47 AM

Sep 23 2014

cestes updated the diff for D5372: [AArch64] Refines the Cortex-A57 Machine Model.

Update changes from 3-way issue in-order to 3-way issue out-of-
order.

Sep 23 2014, 2:01 PM

Sep 18 2014

cestes added a comment to D5372: [AArch64] Refines the Cortex-A57 Machine Model.

I did some more runs and I've got mixed news. Seems I've been a bit more
focused on this new model's gains over -mcpu=generic rather than using
the existing A57 model as a baseline. The reason was primarily because
our earlier testing showed the existing A57 model performing very
poorly. However, I re-did my runs using the existing A57 model as a
baseline and it actually performs really well. So that's the good news.
The mediocre news is that increasing the accuracy of the model has
merely shifted performance around and not actually increased it.

Sep 18 2014, 9:34 AM

Sep 17 2014

cestes added a comment to D5372: [AArch64] Refines the Cortex-A57 Machine Model.

Setting IssueWidth=3 is correct. That really means how many micro-ops can be "handled" per cycle. So it should be the minimum of decode/issue width. To be precise, we should have a decodeWidth that counts instructions, but I never bothered to add it since IssueWidth can serve the same purpose.

Sep 17 2014, 9:07 AM
cestes added a comment to D5372: [AArch64] Refines the Cortex-A57 Machine Model.

I'm seeing strong improvements for Spec2000 on device here, so I'll try ToT too and get to the bottom of this.

Sep 17 2014, 8:19 AM
cestes updated subscribers of D5372: [AArch64] Refines the Cortex-A57 Machine Model.
Sep 17 2014, 8:17 AM

Sep 16 2014

cestes retitled D5372: [AArch64] Refines the Cortex-A57 Machine Model from to [AArch64] Refines the Cortex-A57 Machine Model.
Sep 16 2014, 1:53 PM

Jun 6 2014

cestes added a comment to D4008: [AArch64] Basic Sched Model for Cortex-A57.

Thanks, Renato. With this patch I wanted to lay the groundwork for future refinements. Specifically, I'm speaking of the myriad SchedWrite types. These represent every combination of latency, micro-op count, and processor resource used by every instruction for the A57. At this point, I haven't actually mapped all of these to individual instructions using SchedRWs and InstRWs; instead I've just relied mostly on the default SchedRWs. I think doing this mapping is a logical next step, but I wanted to get this basic model in the community because won't be able to work on it for another three weeks (looooooong vacation). Hopefully it's a good start and will hold folks over until I get back.

Jun 6 2014, 8:01 AM

Jun 5 2014

cestes updated the diff for D4037: [AArch64] Fix the ordering of the accumulate operand in SchedRW list..

Updated lit test to just check the computed latencies instead of final schedule. This
will make the test case more robust to future scheduling changes.

Jun 5 2014, 1:23 PM
cestes retitled D4037: [AArch64] Fix the ordering of the accumulate operand in SchedRW list. from to [AArch64] Fix the ordering of the accumulate operand in SchedRW list..
Jun 5 2014, 12:37 PM
cestes updated the diff for D4008: [AArch64] Basic Sched Model for Cortex-A57.

Restoring original diff after accidently submitting another patch
as a new diff for this review.

Jun 5 2014, 12:33 PM
cestes updated the diff for D4008: [AArch64] Basic Sched Model for Cortex-A57.
  • [AArch64] Fix the ordering of the accumulate operand in SchedRW list.
Jun 5 2014, 12:30 PM

Jun 3 2014

cestes retitled D4008: [AArch64] Basic Sched Model for Cortex-A57 from to [AArch64] Basic Sched Model for Cortex-A57.
Jun 3 2014, 1:41 PM
cestes closed D3769: [ARM64] Increases the Sched Model accuracy for Cortex-A53..
Jun 3 2014, 1:35 PM

May 19 2014

cestes added inline comments to D3829: [ARM64] Adds Cortex-A53 scheduling support for vector load/store post..
May 19 2014, 2:42 PM
cestes updated subscribers of D3829: [ARM64] Adds Cortex-A53 scheduling support for vector load/store post..
May 19 2014, 2:02 PM
cestes retitled D3829: [ARM64] Adds Cortex-A53 scheduling support for vector load/store post. from to [ARM64] Adds Cortex-A53 scheduling support for vector load/store post..
May 19 2014, 1:30 PM

May 16 2014

cestes added a comment to D3769: [ARM64] Increases the Sched Model accuracy for Cortex-A53..

Accidentally committed the patchset without the recommended revisions from Tim. Will submit with a subsequent patchset that adds these revisions and also resolves http://llvm.org/bugs/show_bug.cgi?id=19761.

May 16 2014, 12:57 PM

May 15 2014

cestes added a comment to D3769: [ARM64] Increases the Sched Model accuracy for Cortex-A53..

Thanks, Tim.

May 15 2014, 10:41 AM
cestes updated the diff for D3769: [ARM64] Increases the Sched Model accuracy for Cortex-A53..

Removing commented out code.

May 15 2014, 10:26 AM
cestes updated the diff for D3769: [ARM64] Increases the Sched Model accuracy for Cortex-A53..

Explicitly checking Opcodes in the helper function(s) for shifting/extending.

May 15 2014, 10:23 AM

May 14 2014

cestes retitled D3769: [ARM64] Increases the Sched Model accuracy for Cortex-A53. from to [ARM64] Increases the Sched Model accuracy for Cortex-A53..
May 14 2014, 12:13 PM