[AArch64][GlobalISel] Don't bail out of folding in extends into WRO addressing modes.

[aemerson]

Summary

We were doing an additional check to see if a G_SEXT is worth folding into a mem op compared to SelectionDAG. In terms of code size it's usually a wash.

I'm not entirely sure this is the right thing to do, I don't have performance numbers to show any difference with this either way.

[paquette]

Is this only for code size? Does SDAG do this at, say, -O3?

The GISel version of the function has a check for minsize, but SDAG has a check against shouldOptForSize() in its version of this function (AArch64DAGToDAGISel::isWorthFolding)

We're also missing a couple cases that are present in the SDAG version of the function. Adding them might make this fire.

[aemerson]

Abandon this for now, not enough justification.

llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp

auto ExtendedShl = selectExtendedSHL(Root, LHS, OffsetInst->getOperand(0),
                                        SizeInBytes, /*WantsExt=*/true);
   if (ExtendedShl)
     return ExtendedShl;
 
   // There was no shift. We can try and fold a G_Z/S/ANYEXT in alone though.
   //
   // e.g.
   // ldr something, [base_reg, ext_reg, sxtw]
-  if (!isWorthFoldingIntoExtendedReg(*OffsetInst, MRI))
-    return None;
-
   // Check if this is an extend. We'll get an extend type if it is.
   AArch64_AM::ShiftExtendType Ext =
       getExtendTypeForInst(*OffsetInst, MRI, /*IsLoadStore=*/true);
   if (Ext == AArch64_AM::InvalidShiftExtend)
     return None;
 
   // Need a 32-bit wide register.
   MachineIRBuilder MIB(*PtrAdd);

llvm/test/CodeGen/AArch64/GlobalISel/load-wro-addressing-modes.mir

bb.0:
     %and:gpr(s64) = G_AND %imp, %mask
     %c:gpr(s64) = G_CONSTANT i64 8
     %mul:gpr(s64) = G_MUL %c, %and
     %ptr:gpr(p0) = G_PTR_ADD %base, %mul(s64)
     %load:gpr(s64) = G_LOAD %ptr(p0) :: (load 8)
     $x1 = COPY %load(s64)
     RET_ReallyLR implicit $x1
 ...
+---
+name:            extend_only_multi_use
+alignment:       4
+legalized:       true
+regBankSelected: true
+selected:        false
+tracksRegLiveness: true
+frameInfo:
+  maxAlignment:    1
+fixedStack:      []
+stack:           []
+callSites:       []
+constants:       []
+machineFunctionInfo: {}
+body:             |
+  bb.1.entry:
+    liveins: $w0, $x1
+    ; Check that even if the G_SEXT is used by another instruction we still
+    ; fold it into the load, to match SDAG.
+    ; CHECK-LABEL: name: extend_only_multi_use
+    ; CHECK: liveins: $w0, $x1
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x1
+    ; CHECK: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF
+    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gpr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32
+    ; CHECK: [[SBFMXri:%[0-9]+]]:gpr64 = SBFMXri [[INSERT_SUBREG]], 0, 31
+    ; CHECK: [[LDRBBroW:%[0-9]+]]:gpr32 = LDRBBroW [[COPY1]], [[COPY]], 1, 0 :: (load 1)
+    ; CHECK: %other_use:gpr64 = ADDXrr [[SBFMXri]], [[SBFMXri]]
+    ; CHECK: $w0 = COPY [[LDRBBroW]]
+    ; CHECK: $x1 = COPY %other_use
+    ; CHECK: RET_ReallyLR implicit $w0
+    %0:gpr(s32) = COPY $w0
+    %1:gpr(p0) = COPY $x1
+    %4:gpr(s64) = G_SEXT %0(s32)
+    %5:gpr(p0) = G_PTR_ADD %1, %4(s64)
+    %296:gpr(s32) = G_ZEXTLOAD %5(p0) :: (load 1)
+    %other_use:gpr(s64) = G_ADD %4(s64), %4(s64)
+    $w0 = COPY %296(s32)
+    $x1 = COPY %other_use(s64)
+    RET_ReallyLR implicit $w0
+...