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Differential D80430

[AMDGPU][MC][GFX8+] Enabled clamp for v_add_u16, v_sub_u16 and v_subrev_u16
ClosedPublic

Authored by dp on May 22 2020, 4:32 AM.

Details

Reviewers
arsenm
rampitec
vpykhtin
Commits
rG77aec3b4c0e6: [AMDGPU][MC][GFX8+] Enabled clamp for v_add_u16, v_sub_u16 and v_subrev_u16
Summary

See bug 45926

Diff Detail

Event Timeline

dp created this revision.May 22 2020, 4:32 AM
Herald added a project: Restricted Project. · View Herald TranscriptMay 22 2020, 4:32 AM
Herald added subscribers: llvm-commits, kerbowa, hiraditya and 8 others. · View Herald Transcript
arsenm accepted this revision.May 22 2020, 6:26 AM
This revision is now accepted and ready to land.May 22 2020, 6:26 AM
Closed by commit rG77aec3b4c0e6: [AMDGPU][MC][GFX8+] Enabled clamp for v_add_u16, v_sub_u16 and v_subrev_u16 (authored by dp). · Explain WhyMay 25 2020, 10:42 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
1 line
6 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
16 lines
MC/
AMDGPU/
6 lines
15 lines
Disassembler/
AMDGPU/
6 lines
9 lines

Diff 266049

llvm/lib/Target/AMDGPU/SIInstrInfo.td

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def VOP_F16_F16 : VOPProfile <[f16, f16, untyped, untyped]>; def VOP_F16_F16 : VOPProfile <[f16, f16, untyped, untyped]>;
def VOP_F16_I16 : VOPProfile <[f16, i16, untyped, untyped]>; def VOP_F16_I16 : VOPProfile <[f16, i16, untyped, untyped]>;
def VOP_I16_F16 : VOPProfile <[i16, f16, untyped, untyped]>; def VOP_I16_F16 : VOPProfile <[i16, f16, untyped, untyped]>;
def VOP_F16_F16_F16 : VOPProfile <[f16, f16, f16, untyped]>; def VOP_F16_F16_F16 : VOPProfile <[f16, f16, f16, untyped]>;
def VOP_F16_F16_I16 : VOPProfile <[f16, f16, i16, untyped]>; def VOP_F16_F16_I16 : VOPProfile <[f16, f16, i16, untyped]>;
def VOP_F16_F16_I32 : VOPProfile <[f16, f16, i32, untyped]>; def VOP_F16_F16_I32 : VOPProfile <[f16, f16, i32, untyped]>;
def VOP_I16_I16_I16 : VOPProfile <[i16, i16, i16, untyped]>; def VOP_I16_I16_I16 : VOPProfile <[i16, i16, i16, untyped]>;
def VOP_I16_I16_I16_ARITH : VOPProfile <[i16, i16, i16, untyped], 0, /*EnableClamp=*/1>;
def VOP_I16_I16_I16_I16 : VOPProfile <[i16, i16, i16, i16, untyped]>; def VOP_I16_I16_I16_I16 : VOPProfile <[i16, i16, i16, i16, untyped]>;
def VOP_F16_F16_F16_F16 : VOPProfile <[f16, f16, f16, f16, untyped]>; def VOP_F16_F16_F16_F16 : VOPProfile <[f16, f16, f16, f16, untyped]>;
def VOP_I32_I16_I16_I32 : VOPProfile <[i32, i16, i16, i32, untyped]>; def VOP_I32_I16_I16_I32 : VOPProfile <[i32, i16, i16, i32, untyped]>;
def VOP_V2F16_V2F16_V2F16 : VOPProfile <[v2f16, v2f16, v2f16, untyped]>; def VOP_V2F16_V2F16_V2F16 : VOPProfile <[v2f16, v2f16, v2f16, untyped]>;
def VOP_V2I16_V2I16_V2I16 : VOPProfile <[v2i16, v2i16, v2i16, untyped]>; def VOP_V2I16_V2I16_V2I16 : VOPProfile <[v2i16, v2i16, v2i16, untyped]>;
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llvm/lib/Target/AMDGPU/VOP2Instructions.td

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let isCommutable = 1 in { let isCommutable = 1 in {
let FPDPRounding = 1 in { let FPDPRounding = 1 in {
defm V_ADD_F16 : VOP2Inst <"v_add_f16", VOP_F16_F16_F16, fadd>; defm V_ADD_F16 : VOP2Inst <"v_add_f16", VOP_F16_F16_F16, fadd>;
defm V_SUB_F16 : VOP2Inst <"v_sub_f16", VOP_F16_F16_F16, fsub>; defm V_SUB_F16 : VOP2Inst <"v_sub_f16", VOP_F16_F16_F16, fsub>;
defm V_SUBREV_F16 : VOP2Inst <"v_subrev_f16", VOP_F16_F16_F16, null_frag, "v_sub_f16">; defm V_SUBREV_F16 : VOP2Inst <"v_subrev_f16", VOP_F16_F16_F16, null_frag, "v_sub_f16">;
defm V_MUL_F16 : VOP2Inst <"v_mul_f16", VOP_F16_F16_F16, fmul>; defm V_MUL_F16 : VOP2Inst <"v_mul_f16", VOP_F16_F16_F16, fmul>;
def V_MADAK_F16 : VOP2_Pseudo <"v_madak_f16", VOP_MADAK_F16, [], "">; def V_MADAK_F16 : VOP2_Pseudo <"v_madak_f16", VOP_MADAK_F16, [], "">;
} // End FPDPRounding = 1 } // End FPDPRounding = 1
defm V_ADD_U16 : VOP2Inst <"v_add_u16", VOP_I16_I16_I16, add>; defm V_ADD_U16 : VOP2Inst <"v_add_u16", VOP_I16_I16_I16_ARITH, add>;
defm V_SUB_U16 : VOP2Inst <"v_sub_u16" , VOP_I16_I16_I16, sub>; defm V_SUB_U16 : VOP2Inst <"v_sub_u16" , VOP_I16_I16_I16_ARITH, sub>;
defm V_SUBREV_U16 : VOP2Inst <"v_subrev_u16", VOP_I16_I16_I16, null_frag, "v_sub_u16">; defm V_SUBREV_U16 : VOP2Inst <"v_subrev_u16", VOP_I16_I16_I16_ARITH, null_frag, "v_sub_u16">;
defm V_MUL_LO_U16 : VOP2Inst <"v_mul_lo_u16", VOP_I16_I16_I16, mul>; defm V_MUL_LO_U16 : VOP2Inst <"v_mul_lo_u16", VOP_I16_I16_I16, mul>;
defm V_MAX_F16 : VOP2Inst <"v_max_f16", VOP_F16_F16_F16, fmaxnum_like>; defm V_MAX_F16 : VOP2Inst <"v_max_f16", VOP_F16_F16_F16, fmaxnum_like>;
defm V_MIN_F16 : VOP2Inst <"v_min_f16", VOP_F16_F16_F16, fminnum_like>; defm V_MIN_F16 : VOP2Inst <"v_min_f16", VOP_F16_F16_F16, fminnum_like>;
defm V_MAX_U16 : VOP2Inst <"v_max_u16", VOP_I16_I16_I16, umax>; defm V_MAX_U16 : VOP2Inst <"v_max_u16", VOP_I16_I16_I16, umax>;
defm V_MAX_I16 : VOP2Inst <"v_max_i16", VOP_I16_I16_I16, smax>; defm V_MAX_I16 : VOP2Inst <"v_max_i16", VOP_I16_I16_I16, smax>;
defm V_MIN_U16 : VOP2Inst <"v_min_u16", VOP_I16_I16_I16, umin>; defm V_MIN_U16 : VOP2Inst <"v_min_u16", VOP_I16_I16_I16, umin>;
defm V_MIN_I16 : VOP2Inst <"v_min_i16", VOP_I16_I16_I16, smin>; defm V_MIN_I16 : VOP2Inst <"v_min_i16", VOP_I16_I16_I16, smin>;
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llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.s16.mir

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body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; GFX6-LABEL: name: add_s16 ; GFX6-LABEL: name: add_s16
; GFX6: liveins: $vgpr0, $vgpr1 ; GFX6: liveins: $vgpr0, $vgpr1
; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX6: [[V_ADD_U16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U16_e64 [[COPY]], [[COPY1]], implicit $exec ; GFX6: [[V_ADD_U16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U16_e64 [[COPY]], [[COPY1]], 0, implicit $exec
; GFX6: S_ENDPGM 0, implicit [[V_ADD_U16_e64_]] ; GFX6: S_ENDPGM 0, implicit [[V_ADD_U16_e64_]]
; GFX10-LABEL: name: add_s16 ; GFX10-LABEL: name: add_s16
; GFX10: liveins: $vgpr0, $vgpr1 ; GFX10: liveins: $vgpr0, $vgpr1
; GFX10: $vcc_hi = IMPLICIT_DEF ; GFX10: $vcc_hi = IMPLICIT_DEF
; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX10: [[V_ADD_U16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U16_e64 [[COPY]], [[COPY1]], implicit $exec ; GFX10: [[V_ADD_U16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U16_e64 [[COPY]], [[COPY1]], 0, implicit $exec
; GFX10: S_ENDPGM 0, implicit [[V_ADD_U16_e64_]] ; GFX10: S_ENDPGM 0, implicit [[V_ADD_U16_e64_]]
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1 %3:vgpr(s16) = G_TRUNC %1
%4:vgpr(s16) = G_ADD %2, %3 %4:vgpr(s16) = G_ADD %2, %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...
--- ---
name: add_s16_zext_to_s32 name: add_s16_zext_to_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; GFX6-LABEL: name: add_s16_zext_to_s32 ; GFX6-LABEL: name: add_s16_zext_to_s32
; GFX6: liveins: $vgpr0, $vgpr1 ; GFX6: liveins: $vgpr0, $vgpr1
; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX6: [[V_ADD_U16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U16_e64 [[COPY]], [[COPY1]], implicit $exec ; GFX6: [[V_ADD_U16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U16_e64 [[COPY]], [[COPY1]], 0, implicit $exec
; GFX6: S_ENDPGM 0, implicit [[V_ADD_U16_e64_]] ; GFX6: S_ENDPGM 0, implicit [[V_ADD_U16_e64_]]
; GFX10-LABEL: name: add_s16_zext_to_s32 ; GFX10-LABEL: name: add_s16_zext_to_s32
; GFX10: liveins: $vgpr0, $vgpr1 ; GFX10: liveins: $vgpr0, $vgpr1
; GFX10: $vcc_hi = IMPLICIT_DEF ; GFX10: $vcc_hi = IMPLICIT_DEF
; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX10: [[V_ADD_U16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U16_e64 [[COPY]], [[COPY1]], implicit $exec ; GFX10: [[V_ADD_U16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U16_e64 [[COPY]], [[COPY1]], 0, implicit $exec
; GFX10: [[V_BFE_U32_:%[0-9]+]]:vgpr_32 = V_BFE_U32 [[V_ADD_U16_e64_]], 0, 16, implicit $exec ; GFX10: [[V_BFE_U32_:%[0-9]+]]:vgpr_32 = V_BFE_U32 [[V_ADD_U16_e64_]], 0, 16, implicit $exec
; GFX10: S_ENDPGM 0, implicit [[V_BFE_U32_]] ; GFX10: S_ENDPGM 0, implicit [[V_BFE_U32_]]
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s16) = G_TRUNC %0 %2:vgpr(s16) = G_TRUNC %0
%3:vgpr(s16) = G_TRUNC %1 %3:vgpr(s16) = G_TRUNC %1
%4:vgpr(s16) = G_ADD %2, %3 %4:vgpr(s16) = G_ADD %2, %3
%5:vgpr(s32) = G_ZEXT %4 %5:vgpr(s32) = G_ZEXT %4
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body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; GFX6-LABEL: name: add_s16_neg_inline_const_64 ; GFX6-LABEL: name: add_s16_neg_inline_const_64
; GFX6: liveins: $vgpr0 ; GFX6: liveins: $vgpr0
; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX6: [[V_SUB_U16_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U16_e64 [[COPY]], 64, implicit $exec ; GFX6: [[V_SUB_U16_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U16_e64 [[COPY]], 64, 0, implicit $exec
; GFX6: S_ENDPGM 0, implicit [[V_SUB_U16_e64_]] ; GFX6: S_ENDPGM 0, implicit [[V_SUB_U16_e64_]]
; GFX10-LABEL: name: add_s16_neg_inline_const_64 ; GFX10-LABEL: name: add_s16_neg_inline_const_64
; GFX10: liveins: $vgpr0 ; GFX10: liveins: $vgpr0
; GFX10: $vcc_hi = IMPLICIT_DEF ; GFX10: $vcc_hi = IMPLICIT_DEF
; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX10: [[V_SUB_U16_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U16_e64 [[COPY]], 64, implicit $exec ; GFX10: [[V_SUB_U16_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U16_e64 [[COPY]], 64, 0, implicit $exec
; GFX10: S_ENDPGM 0, implicit [[V_SUB_U16_e64_]] ; GFX10: S_ENDPGM 0, implicit [[V_SUB_U16_e64_]]
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s16) = G_TRUNC %0 %1:vgpr(s16) = G_TRUNC %0
%2:vgpr(s16) = G_CONSTANT i16 -64 %2:vgpr(s16) = G_CONSTANT i16 -64
%3:vgpr(s16) = G_ADD %1, %2 %3:vgpr(s16) = G_ADD %1, %2
S_ENDPGM 0, implicit %3 S_ENDPGM 0, implicit %3
... ...
--- ---
name: add_s16_neg_inline_const_64_zext_to_s32 name: add_s16_neg_inline_const_64_zext_to_s32
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; GFX6-LABEL: name: add_s16_neg_inline_const_64_zext_to_s32 ; GFX6-LABEL: name: add_s16_neg_inline_const_64_zext_to_s32
; GFX6: liveins: $vgpr0 ; GFX6: liveins: $vgpr0
; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX6: [[V_SUB_U16_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U16_e64 [[COPY]], 64, implicit $exec ; GFX6: [[V_SUB_U16_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U16_e64 [[COPY]], 64, 0, implicit $exec
; GFX6: S_ENDPGM 0, implicit [[V_SUB_U16_e64_]] ; GFX6: S_ENDPGM 0, implicit [[V_SUB_U16_e64_]]
; GFX10-LABEL: name: add_s16_neg_inline_const_64_zext_to_s32 ; GFX10-LABEL: name: add_s16_neg_inline_const_64_zext_to_s32
; GFX10: liveins: $vgpr0 ; GFX10: liveins: $vgpr0
; GFX10: $vcc_hi = IMPLICIT_DEF ; GFX10: $vcc_hi = IMPLICIT_DEF
; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX10: [[V_SUB_U16_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U16_e64 [[COPY]], 64, implicit $exec ; GFX10: [[V_SUB_U16_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U16_e64 [[COPY]], 64, 0, implicit $exec
; GFX10: [[V_BFE_U32_:%[0-9]+]]:vgpr_32 = V_BFE_U32 [[V_SUB_U16_e64_]], 0, 16, implicit $exec ; GFX10: [[V_BFE_U32_:%[0-9]+]]:vgpr_32 = V_BFE_U32 [[V_SUB_U16_e64_]], 0, 16, implicit $exec
; GFX10: S_ENDPGM 0, implicit [[V_BFE_U32_]] ; GFX10: S_ENDPGM 0, implicit [[V_BFE_U32_]]
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s16) = G_TRUNC %0 %1:vgpr(s16) = G_TRUNC %0
%2:vgpr(s16) = G_CONSTANT i16 -64 %2:vgpr(s16) = G_CONSTANT i16 -64
%3:vgpr(s16) = G_ADD %1, %2 %3:vgpr(s16) = G_ADD %1, %2
%4:vgpr(s32) = G_ZEXT %3 %4:vgpr(s32) = G_ZEXT %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...

llvm/test/MC/AMDGPU/gfx10_asm_all.s

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// GFX10: encoding: [0x05,0x00,0x03,0xd7,0x01,0x83,0x01,0x00] // GFX10: encoding: [0x05,0x00,0x03,0xd7,0x01,0x83,0x01,0x00]
v_add_nc_u16 v5, v1, 0.5 v_add_nc_u16 v5, v1, 0.5
// GFX10: encoding: [0x05,0x00,0x03,0xd7,0x01,0xe1,0x01,0x00] // GFX10: encoding: [0x05,0x00,0x03,0xd7,0x01,0xe1,0x01,0x00]
v_add_nc_u16 v5, v1, -4.0 v_add_nc_u16 v5, v1, -4.0
// GFX10: encoding: [0x05,0x00,0x03,0xd7,0x01,0xef,0x01,0x00] // GFX10: encoding: [0x05,0x00,0x03,0xd7,0x01,0xef,0x01,0x00]
v_add_nc_u16 v5, v1, -4.0 clamp
// GFX10: encoding: [0x05,0x80,0x03,0xd7,0x01,0xef,0x01,0x00]
v_sub_nc_u16 v5, v1, v2 v_sub_nc_u16 v5, v1, v2
// GFX10: encoding: [0x05,0x00,0x04,0xd7,0x01,0x05,0x02,0x00] // GFX10: encoding: [0x05,0x00,0x04,0xd7,0x01,0x05,0x02,0x00]
v_sub_nc_u16 v255, v1, v2 v_sub_nc_u16 v255, v1, v2
// GFX10: encoding: [0xff,0x00,0x04,0xd7,0x01,0x05,0x02,0x00] // GFX10: encoding: [0xff,0x00,0x04,0xd7,0x01,0x05,0x02,0x00]
v_sub_nc_u16 v5, v255, v2 v_sub_nc_u16 v5, v255, v2
// GFX10: encoding: [0x05,0x00,0x04,0xd7,0xff,0x05,0x02,0x00] // GFX10: encoding: [0x05,0x00,0x04,0xd7,0xff,0x05,0x02,0x00]
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// GFX10: encoding: [0x05,0x00,0x04,0xd7,0x01,0x83,0x01,0x00] // GFX10: encoding: [0x05,0x00,0x04,0xd7,0x01,0x83,0x01,0x00]
v_sub_nc_u16 v5, v1, 0.5 v_sub_nc_u16 v5, v1, 0.5
// GFX10: encoding: [0x05,0x00,0x04,0xd7,0x01,0xe1,0x01,0x00] // GFX10: encoding: [0x05,0x00,0x04,0xd7,0x01,0xe1,0x01,0x00]
v_sub_nc_u16 v5, v1, -4.0 v_sub_nc_u16 v5, v1, -4.0
// GFX10: encoding: [0x05,0x00,0x04,0xd7,0x01,0xef,0x01,0x00] // GFX10: encoding: [0x05,0x00,0x04,0xd7,0x01,0xef,0x01,0x00]
v_sub_nc_u16 v5, v1, -4.0 clamp
// GFX10: encoding: [0x05,0x80,0x04,0xd7,0x01,0xef,0x01,0x00]
v_mul_lo_u16 v5, v1, v2 v_mul_lo_u16 v5, v1, v2
// GFX10: encoding: [0x05,0x00,0x05,0xd7,0x01,0x05,0x02,0x00] // GFX10: encoding: [0x05,0x00,0x05,0xd7,0x01,0x05,0x02,0x00]
v_mul_lo_u16 v255, v1, v2 v_mul_lo_u16 v255, v1, v2
// GFX10: encoding: [0xff,0x00,0x05,0xd7,0x01,0x05,0x02,0x00] // GFX10: encoding: [0xff,0x00,0x05,0xd7,0x01,0x05,0x02,0x00]
v_mul_lo_u16 v5, v255, v2 v_mul_lo_u16 v5, v255, v2
// GFX10: encoding: [0x05,0x00,0x05,0xd7,0xff,0x05,0x02,0x00] // GFX10: encoding: [0x05,0x00,0x05,0xd7,0xff,0x05,0x02,0x00]
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llvm/test/MC/AMDGPU/vop2.s

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// VI: v_madak_f16 v1, v2, v3, 0x5400 ; encoding: [0x02,0x07,0x02,0x4a,0x00,0x54,0x00,0x00] // VI: v_madak_f16 v1, v2, v3, 0x5400 ; encoding: [0x02,0x07,0x02,0x4a,0x00,0x54,0x00,0x00]
v_madak_f16 v1, v2, v3, 64.0 v_madak_f16 v1, v2, v3, 64.0
// NOSICI: error: instruction not supported on this GPU // NOSICI: error: instruction not supported on this GPU
// NOSICI: v_add_u16_e32 v1, v2, v3 // NOSICI: v_add_u16_e32 v1, v2, v3
// VI: v_add_u16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x4c] // VI: v_add_u16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x4c]
v_add_u16_e32 v1, v2, v3 v_add_u16_e32 v1, v2, v3
// NOSICI: error: invalid operand for instruction
// NOSICI: v_add_u16 v1, v2, v3 clamp
// VI: v_add_u16_e64 v1, v2, v3 clamp ; encoding: [0x01,0x80,0x26,0xd1,0x02,0x07,0x02,0x00]
v_add_u16 v1, v2, v3 clamp
// NOSICI: error: instruction not supported on this GPU // NOSICI: error: instruction not supported on this GPU
// NOSICI: v_sub_u16_e32 v1, v2, v3 // NOSICI: v_sub_u16_e32 v1, v2, v3
// VI: v_sub_u16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x4e] // VI: v_sub_u16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x4e]
v_sub_u16_e32 v1, v2, v3 v_sub_u16_e32 v1, v2, v3
// NOSICI: error: invalid operand for instruction
// NOSICI: v_sub_u16 v1, v2, v3 clamp
// VI: v_sub_u16_e64 v1, v2, v3 clamp ; encoding: [0x01,0x80,0x27,0xd1,0x02,0x07,0x02,0x00]
v_sub_u16 v1, v2, v3 clamp
// NOSICI: error: instruction not supported on this GPU // NOSICI: error: instruction not supported on this GPU
// NOSICI: v_subrev_u16_e32 v1, v2, v3 // NOSICI: v_subrev_u16_e32 v1, v2, v3
// VI: v_subrev_u16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x50] // VI: v_subrev_u16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x50]
v_subrev_u16_e32 v1, v2, v3 v_subrev_u16_e32 v1, v2, v3
// NOSICI: error: invalid operand for instruction
// NOSICI: v_subrev_u16 v1, v2, v3 clamp
// VI: v_subrev_u16_e64 v1, v2, v3 clamp ; encoding: [0x01,0x80,0x28,0xd1,0x02,0x07,0x02,0x00]
v_subrev_u16 v1, v2, v3 clamp
// NOSICI: error: instruction not supported on this GPU // NOSICI: error: instruction not supported on this GPU
// NOSICI: v_mul_lo_u16_e32 v1, v2, v3 // NOSICI: v_mul_lo_u16_e32 v1, v2, v3
// VI: v_mul_lo_u16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x52] // VI: v_mul_lo_u16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x52]
v_mul_lo_u16_e32 v1, v2, v3 v_mul_lo_u16_e32 v1, v2, v3
// NOSICI: error: instruction not supported on this GPU // NOSICI: error: instruction not supported on this GPU
// NOSICI: v_lshlrev_b16_e32 v1, v2, v3 // NOSICI: v_lshlrev_b16_e32 v1, v2, v3
// VI: v_lshlrev_b16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x54] // VI: v_lshlrev_b16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x54]
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llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt

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0x05,0x00,0x03,0xd7,0xff,0x05,0x02,0x00 0x05,0x00,0x03,0xd7,0xff,0x05,0x02,0x00
# GFX10: v_add_nc_u16_e64 v5, vcc_hi, v2 ; encoding: [0x05,0x00,0x03,0xd7,0x6b,0x04,0x02,0x00] # GFX10: v_add_nc_u16_e64 v5, vcc_hi, v2 ; encoding: [0x05,0x00,0x03,0xd7,0x6b,0x04,0x02,0x00]
0x05,0x00,0x03,0xd7,0x6b,0x04,0x02,0x00 0x05,0x00,0x03,0xd7,0x6b,0x04,0x02,0x00
# GFX10: v_add_nc_u16_e64 v5, vcc_lo, v2 ; encoding: [0x05,0x00,0x03,0xd7,0x6a,0x04,0x02,0x00] # GFX10: v_add_nc_u16_e64 v5, vcc_lo, v2 ; encoding: [0x05,0x00,0x03,0xd7,0x6a,0x04,0x02,0x00]
0x05,0x00,0x03,0xd7,0x6a,0x04,0x02,0x00 0x05,0x00,0x03,0xd7,0x6a,0x04,0x02,0x00
# GFX10: v_add_nc_u16_e64 v5, vcc_lo, v2 clamp ; encoding: [0x05,0x80,0x03,0xd7,0x6a,0x04,0x02,0x00]
0x05,0x80,0x03,0xd7,0x6a,0x04,0x02,0x00
# GFX10: v_add_nc_u32_e32 v255, v1, v2 ; encoding: [0x01,0x05,0xfe,0x4b] # GFX10: v_add_nc_u32_e32 v255, v1, v2 ; encoding: [0x01,0x05,0xfe,0x4b]
0x01,0x05,0xfe,0x4b 0x01,0x05,0xfe,0x4b
# GFX10: v_add_nc_u32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x4a] # GFX10: v_add_nc_u32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x4a]
0xc1,0x04,0x0a,0x4a 0xc1,0x04,0x0a,0x4a
# GFX10: v_add_nc_u32_e32 v5, -4.0, v2 ; encoding: [0xf7,0x04,0x0a,0x4a] # GFX10: v_add_nc_u32_e32 v5, -4.0, v2 ; encoding: [0xf7,0x04,0x0a,0x4a]
0xf7,0x04,0x0a,0x4a 0xf7,0x04,0x0a,0x4a
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0x05,0x00,0x04,0xd7,0xff,0x05,0x02,0x00 0x05,0x00,0x04,0xd7,0xff,0x05,0x02,0x00
# GFX10: v_sub_nc_u16_e64 v5, vcc_hi, v2 ; encoding: [0x05,0x00,0x04,0xd7,0x6b,0x04,0x02,0x00] # GFX10: v_sub_nc_u16_e64 v5, vcc_hi, v2 ; encoding: [0x05,0x00,0x04,0xd7,0x6b,0x04,0x02,0x00]
0x05,0x00,0x04,0xd7,0x6b,0x04,0x02,0x00 0x05,0x00,0x04,0xd7,0x6b,0x04,0x02,0x00
# GFX10: v_sub_nc_u16_e64 v5, vcc_lo, v2 ; encoding: [0x05,0x00,0x04,0xd7,0x6a,0x04,0x02,0x00] # GFX10: v_sub_nc_u16_e64 v5, vcc_lo, v2 ; encoding: [0x05,0x00,0x04,0xd7,0x6a,0x04,0x02,0x00]
0x05,0x00,0x04,0xd7,0x6a,0x04,0x02,0x00 0x05,0x00,0x04,0xd7,0x6a,0x04,0x02,0x00
# GFX10: v_sub_nc_u16_e64 v5, vcc_lo, v2 clamp ; encoding: [0x05,0x80,0x04,0xd7,0x6a,0x04,0x02,0x00]
0x05,0x80,0x04,0xd7,0x6a,0x04,0x02,0x00
# GFX10: v_sub_nc_u32_e32 v255, v1, v2 ; encoding: [0x01,0x05,0xfe,0x4d] # GFX10: v_sub_nc_u32_e32 v255, v1, v2 ; encoding: [0x01,0x05,0xfe,0x4d]
0x01,0x05,0xfe,0x4d 0x01,0x05,0xfe,0x4d
# GFX10: v_sub_nc_u32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x4c] # GFX10: v_sub_nc_u32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x4c]
0xc1,0x04,0x0a,0x4c 0xc1,0x04,0x0a,0x4c
# GFX10: v_sub_nc_u32_e32 v5, -4.0, v2 ; encoding: [0xf7,0x04,0x0a,0x4c] # GFX10: v_sub_nc_u32_e32 v5, -4.0, v2 ; encoding: [0xf7,0x04,0x0a,0x4c]
0xf7,0x04,0x0a,0x4c 0xf7,0x04,0x0a,0x4c
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llvm/test/MC/Disassembler/AMDGPU/vop2_vi.txt

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0x02 0x07 0x02 0x48 0x00 0x00 0x80 0x42 0x02 0x07 0x02 0x48 0x00 0x00 0x80 0x42
# VI: v_madak_f16 v1, v2, v3, 0x42800000 ; encoding: [0x02,0x07,0x02,0x4a,0x00,0x00,0x80,0x42] # VI: v_madak_f16 v1, v2, v3, 0x42800000 ; encoding: [0x02,0x07,0x02,0x4a,0x00,0x00,0x80,0x42]
0x02 0x07 0x02 0x4a 0x00 0x00 0x80 0x42 0x02 0x07 0x02 0x4a 0x00 0x00 0x80 0x42
# VI: v_add_u16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x4c] # VI: v_add_u16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x4c]
0x02 0x07 0x02 0x4c 0x02 0x07 0x02 0x4c
# VI: v_add_u16_e64 v1, v2, v3 clamp ; encoding: [0x01,0x80,0x26,0xd1,0x02,0x07,0x02,0x00]
0x01 0x80 0x26 0xd1 0x02 0x07 0x02 0x00
# VI: v_sub_u16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x4e] # VI: v_sub_u16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x4e]
0x02 0x07 0x02 0x4e 0x02 0x07 0x02 0x4e
# VI: v_sub_u16_e64 v1, v2, v3 clamp ; encoding: [0x01,0x80,0x27,0xd1,0x02,0x07,0x02,0x00]
0x01 0x80 0x27 0xd1 0x02 0x07 0x02 0x00
# VI: v_subrev_u16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x50] # VI: v_subrev_u16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x50]
0x02 0x07 0x02 0x50 0x02 0x07 0x02 0x50
# VI: v_subrev_u16_e64 v1, v2, v3 clamp ; encoding: [0x01,0x80,0x28,0xd1,0x02,0x07,0x02,0x00]
0x01 0x80 0x28 0xd1 0x02 0x07 0x02 0x00
# VI: v_mul_lo_u16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x52] # VI: v_mul_lo_u16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x52]
0x02 0x07 0x02 0x52 0x02 0x07 0x02 0x52
# VI: v_lshlrev_b16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x54] # VI: v_lshlrev_b16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x54]
0x02 0x07 0x02 0x54 0x02 0x07 0x02 0x54
# VI: v_lshrrev_b16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x56] # VI: v_lshrrev_b16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x56]
0x02 0x07 0x02 0x56 0x02 0x07 0x02 0x56
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