[AMDGPU] Correct formatting typos in documentation

[t-tye]

Summary

• Correct missing space in some "note" and "TODO" directives in AMDGPUUsage.rst
• Correct warning for heading underline being too short in BitCodeFormat.rst

[kzhuravl]

LGTM

llvm/docs/AMDGPUUsage.rst

 
 9.  Implicit Argument Ptr (2 SGPRs)
 
     The value is computed by adding an offset to Kernarg Segment Ptr to get the
     global address space pointer to the first kernarg implicit argument.
 
 The input and result arguments are assigned in order in the following manner:
 
-..note::
+.. note::
 
   There are likely some errors and omissions in the following description that
   need correction.
 
-  ..TODO::
+  .. TODO::
 
     Check the clang source code to decipher how function arguments and return
     results are handled. Also see the AMDGPU specific values used.
 
 * VGPR arguments are assigned to consecutive VGPRs starting at VGPR0 up to
   VGPR31.
 
   If there are more arguments than will fit in these registers, the remaining
2.  Runtime stack alignment is supported. SGPR34 is used as a base pointer (BP)
     to access the incoming stack arguments in the function. The BP is needed
     only when the function requires the runtime stack alignment.
 
 3.  Allocating SGPR arguments on the stack are not supported.
 
 4.  No CFI is currently generated. See
     :ref:`amdgpu-dwarf-call-frame-information`.
 
-    ..note::
+    .. note::
 
       CFI will be generated that defines the CFA as the unswizzled address
       relative to the wave scratch base in the unswizzled private address space
       of the lowest address stack allocated local variable.
 
       ``DW_AT_frame_base`` will be defined as the swizzled address in the
       swizzled private address space by dividing the CFA by the wavefront size
       (since CFA is always at least dword aligned which matches the scratch
       swizzle element size).
 
       If no dynamic stack alignment was performed, the stack allocated arguments
       are accessed as negative offsets relative to ``DW_AT_frame_base``, and the
       local variables and register spill slots are accessed as positive offsets
       relative to ``DW_AT_frame_base``.
 
 5.  Function argument passing is implemented by copying the input physical
     registers to virtual registers on entry. The register allocator can spill if
     necessary. These are copied back to physical registers at call sites. The
     net effect is that each function call can have these values in entirely
     distinct locations. The IPRA can help avoid shuffling argument registers.
 6.  Call sites are implemented by setting up the arguments at positive offsets
     from SP. Then SP is incremented to account for the known frame size before
     the call and decremented after the call.
 
-    ..note::
+    .. note::
 
       The CFI will reflect the changed calculation needed to compute the CFA
       from SP.
 
 7.  4 byte spill slots are used in the stack frame. One slot is allocated for an
     emergency spill slot. Buffer instructions are used for stack accesses and
     not the ``flat_scratch`` instruction.
 
-    ..TODO::
+    .. TODO::
 
       Explain when the emergency spill slot is used.
 
 .. TODO::
 
   Possible broken issues:
 
   - Stack arguments must be aligned to required alignment.

llvm/docs/BitCodeFormat.rst

 ^^^^^^^^^^^^^^^^^^^^^
 
 ``[HALF]``
 
 The ``HALF`` record (code 10) adds a ``half`` (16-bit floating point) type to
 the type table.
 
 TYPE_CODE_BFLOAT Record
-^^^^^^^^^^^^^^^^^^^^^
+^^^^^^^^^^^^^^^^^^^^^^^
 
 ``[BFLOAT]``
 
 The ``BFLOAT`` record (code 23) adds a ``bfloat`` (16-bit brain floating point)
 type to the type table.
 
 TYPE_CODE_FLOAT Record
 ^^^^^^^^^^^^^^^^^^^^^^