[ARM] Add big-endian version of pcrel fixups for adr instructions

[dim]

Summary

In 2e24219d3cbf, a number of ARM pcrel fixups were resolved at assembly
time, to solve PR44929. This only covered little-endian ARM however, so
add similar fixups for big-endian ARM. Also extend the test case to
cover big-endian ARM.

[psmith]

Looks good to me. The intention is that the little and big-endian table flags match, only the Offset is expected to change for big-endian, and this change does make sure that the flags match. Will be worth waiting a day or so to see if there are any further comments.

[dim]

Note I already merged this fix (minus the test case) into FreeBSD here: https://svnweb.freebsd.org/changeset/base/360697, since we needed it ASAP for being able to build big-endian ARM kernel code. So in that sense it's already been exercised for a bit. :)

[MaskRay]

In the title, s/\[arm]/[ARM]/

[MaskRay]

In D79774#2031755, @dim wrote:

Note I already merged this fix (minus the test case) into FreeBSD here: https://svnweb.freebsd.org/changeset/base/360697, since we needed it ASAP for being able to build big-endian ARM kernel code. So in that sense it's already been exercised for a bit. :)

MFC after: immediately, since this fix is meant for stable/11

I still think the offending FreeBSD assembly can be fixed to be more portable.

[dim]

In D79774#2031805, @MaskRay wrote:

In D79774#2031755, @dim wrote:

Note I already merged this fix (minus the test case) into FreeBSD here: https://svnweb.freebsd.org/changeset/base/360697, since we needed it ASAP for being able to build big-endian ARM kernel code. So in that sense it's already been exercised for a bit. :)

MFC after: immediately, since this fix is meant for stable/11

I still think the offending FreeBSD assembly can be fixed to be more portable.

It's really up to the FreeBSD ARM maintainers, and they seemed to be rather unhappy with the required changes. Then again this particular fix is only meant for the upcoming FreeBSD 11.4 release, which will probably be the last one to support big-endian ARM. So if this whole piece of code is refactored later on, it will most likely not matter anymore.

llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp

const static MCFixupKindInfo InfosLE[ARM::NumTargetFixupKinds] = {
       {"fixup_wls", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
       {"fixup_le", 0, 32, MCFixupKindInfo::FKF_IsPCRel}
   };
   const static MCFixupKindInfo InfosBE[ARM::NumTargetFixupKinds] = {
       // This table *must* be in the order that the fixup_* kinds are defined in
       // ARMFixupKinds.h.
       //
       // Name                      Offset (bits) Size (bits)     Flags
-      {"fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
+      {"fixup_arm_ldst_pcrel_12", 0, 32, IsPCRelConstant},
       {"fixup_t2_ldst_pcrel_12", 0, 32,
-       MCFixupKindInfo::FKF_IsPCRel |
-           MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
-      {"fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
-      {"fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
+       IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
+      {"fixup_arm_pcrel_10_unscaled", 0, 32, IsPCRelConstant},
+      {"fixup_arm_pcrel_10", 0, 32, IsPCRelConstant},
       {"fixup_t2_pcrel_10", 0, 32,
        MCFixupKindInfo::FKF_IsPCRel |
            MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
       {"fixup_arm_pcrel_9", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
       {"fixup_t2_pcrel_9", 0, 32,
-       MCFixupKindInfo::FKF_IsPCRel |
-           MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
+       IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
       {"fixup_thumb_adr_pcrel_10", 8, 8,
-       MCFixupKindInfo::FKF_IsPCRel |
-           MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
-      {"fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
+       IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
+      {"fixup_arm_adr_pcrel_12", 0, 32, IsPCRelConstant},
       {"fixup_t2_adr_pcrel_12", 0, 32,
-       MCFixupKindInfo::FKF_IsPCRel |
-           MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
+       IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
       {"fixup_arm_condbranch", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
       {"fixup_arm_uncondbranch", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
       {"fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
       {"fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
       {"fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
       {"fixup_arm_uncondbl", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
       {"fixup_arm_condbl", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
       {"fixup_arm_blx", 8, 24, MCFixupKindInfo::FKF_IsPCRel},

llvm/test/MC/ARM/pcrel-global.s

 @ RUN: llvm-mc -filetype=obj -triple=armv7 %s -o %t
 @ RUN: llvm-readelf -r %t | FileCheck %s
+@ RUN: llvm-mc -filetype=obj -triple=armebv7 %s -o %t
+@ RUN: llvm-readelf -r %t | FileCheck %s
 
 @ CHECK: There are no relocations in this file.
 .syntax unified
 
 .globl foo
 foo:
 ldrd r0, r1, foo @ arm_pcrel_10_unscaled
 vldr d0, foo     @ arm_pcrel_10