[PowerPC] Add support for llvm.ppc.dcbt, llvm.ppc.dcbtst, llvm.ppc.isync intrinsics

[amyk]

Summary

This patch adds LLVM intrinsics for the dcbt (Data Cache Block Touch),
dcbtst (Data Cache Block Touch for Store) and isync (Instruction
Synchronize) instructions.

The intrinsic for dcbt and dcbst in this patch are named llvm.ppc.dcbt.with.hint
and llvm.ppc.dcbtst.with.hint respectively as there already exists an intrinsic
for llvm.ppc.dcbt and llvm.ppc.dcbtst. However, the original variants of the
intrinsics do not accept the TH immediate field, whereas these variants do.

[lei]

LGTM

llvm/include/llvm/IR/IntrinsicsPowerPC.td

let TargetPrefix = "ppc" in {  // All intrinsics start with "llvm.ppc.".
   def int_ppc_dcbfl : Intrinsic<[], [llvm_ptr_ty], []>;
   def int_ppc_dcbflp: Intrinsic<[], [llvm_ptr_ty], []>;
   def int_ppc_dcbi  : Intrinsic<[], [llvm_ptr_ty], []>;
   def int_ppc_dcbst : Intrinsic<[], [llvm_ptr_ty], []>;
   def int_ppc_dcbt  : Intrinsic<[], [llvm_ptr_ty],
     [IntrArgMemOnly, NoCapture<0>]>;
   def int_ppc_dcbtst: Intrinsic<[], [llvm_ptr_ty],
     [IntrArgMemOnly, NoCapture<0>]>;
+  def int_ppc_dcbt_with_hint: Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty],
+    [IntrArgMemOnly, NoCapture<0>, ImmArg<1>]>;
+  def int_ppc_dcbtst_with_hint: Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty],
+    [IntrArgMemOnly, NoCapture<0>, ImmArg<1>]>;
   def int_ppc_dcbz  : Intrinsic<[], [llvm_ptr_ty], []>;
   def int_ppc_dcbzl : Intrinsic<[], [llvm_ptr_ty], []>;
 
   // sync instruction (i.e. sync 0, a.k.a hwsync)
   def int_ppc_sync : Intrinsic<[], [], []>;
+  // isync instruction
+  def int_ppc_isync : Intrinsic<[], [], []>;
   // lwsync is sync 1
   def int_ppc_lwsync : Intrinsic<[], [], []>;
   // eieio instruction
   def int_ppc_eieio : Intrinsic<[],[],[]>;
 
   // Intrinsics used to generate ctr-based loops. These should only be
   // generated by the PowerPC backend!
   // The branch intrinsic is marked as NoDuplicate because loop rotation will

llvm/lib/Target/PowerPC/PPCInstrInfo.td

 
 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
           (DCBT 0, xoaddr:$dst)>;   // data prefetch for loads
 def : Pat<(prefetch xoaddr:$dst, (i32 1), imm, (i32 1)),
           (DCBTST 0, xoaddr:$dst)>; // data prefetch for stores
 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 0)),
           (ICBT 0, xoaddr:$dst)>, Requires<[HasICBT]>; // inst prefetch (for read)
 
+def : Pat<(int_ppc_dcbt_with_hint xoaddr:$dst, i32:$TH),
+          (DCBT i32:$TH, xoaddr:$dst)>;
+def : Pat<(int_ppc_dcbtst_with_hint xoaddr:$dst, i32:$TH),
+          (DCBTST i32:$TH, xoaddr:$dst)>;
+
 // Atomic operations
 // FIXME: some of these might be used with constant operands. This will result
 // in constant materialization instructions that may be redundant. We currently
 // clean this up in PPCMIPeephole with calls to
 // PPCInstrInfo::convertToImmediateForm() but we should probably not emit them
 // in the first place.
 let Defs = [CR0] in {
   def ATOMIC_LOAD_ADD_I8 : PPCCustomInserterPseudo<

 def DCBTSTCT : PPCAsmPseudo<"dcbtstct $dst, $TH", (ins memrr:$dst, u5imm:$TH)>;
 def DCBTSTDS : PPCAsmPseudo<"dcbtstds $dst, $TH", (ins memrr:$dst, u5imm:$TH)>;
 def DCBTSTT  : PPCAsmPseudo<"dcbtstt $dst", (ins memrr:$dst)>;
 
 def DCBFx  : PPCAsmPseudo<"dcbf $dst", (ins memrr:$dst)>;
 def DCBFL  : PPCAsmPseudo<"dcbfl $dst", (ins memrr:$dst)>;
 def DCBFLP : PPCAsmPseudo<"dcbflp $dst", (ins memrr:$dst)>;
 
+def : Pat<(int_ppc_isync),  (ISYNC)>;
 def : Pat<(int_ppc_dcbfl xoaddr:$dst),
           (DCBFL xoaddr:$dst)>;
 def : Pat<(int_ppc_dcbflp xoaddr:$dst),
           (DCBFLP xoaddr:$dst)>;
 
 def : InstAlias<"crset $bx", (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
 def : InstAlias<"crclr $bx", (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
 def : InstAlias<"crmove $bx, $by", (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;

llvm/test/CodeGen/PowerPC/dcbt.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu < %s \
+; RUN:     -verify-machineinstrs -ppc-asm-full-reg-names \
+; RUN:     -ppc-vsr-nums-as-vr | FileCheck %s
+
+define void @dcbt_with_hint_test1(i8* %a) {
+; CHECK-LABEL: dcbt_with_hint_test1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    dcbt 0, r3
+; CHECK-NEXT:    blr
+entry:
+  tail call void @llvm.ppc.dcbt.with.hint(i8* %a, i32 0)
+  ret void
+}
+
+define void @dcbt_with_hint_test2(i8* %a) {
+; CHECK-LABEL: dcbt_with_hint_test2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    dcbt 0, r3, 8
+; CHECK-NEXT:    blr
+entry:
+  tail call void @llvm.ppc.dcbt.with.hint(i8* %a, i32 8)
+  ret void
+}
+
+define void @dcbt_with_hint_test3(i8* %a) {
+; CHECK-LABEL: dcbt_with_hint_test3:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    dcbt 0, r3, 15
+; CHECK-NEXT:    blr
+entry:
+  tail call void @llvm.ppc.dcbt.with.hint(i8* %a, i32 15)
+  ret void
+}
+
+define void @dcbtst_with_hint_test1(i8* %a) {
+; CHECK-LABEL: dcbtst_with_hint_test1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    dcbtst 0, r3
+; CHECK-NEXT:    blr
+entry:
+  tail call void @llvm.ppc.dcbtst.with.hint(i8* %a, i32 0)
+  ret void
+}
+
+define void @dcbtst_with_hint_test2(i8* %a) {
+; CHECK-LABEL: dcbtst_with_hint_test2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    dcbtst 0, r3, 8
+; CHECK-NEXT:    blr
+entry:
+  tail call void @llvm.ppc.dcbtst.with.hint(i8* %a, i32 8)
+  ret void
+}
+
+define void @dcbtst_with_hint_test3(i8* %a) {
+; CHECK-LABEL: dcbtst_with_hint_test3:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    dcbtst 0, r3, 15
+; CHECK-NEXT:    blr
+entry:
+  tail call void @llvm.ppc.dcbtst.with.hint(i8* %a, i32 15)
+  ret void
+}
+
+declare void @llvm.ppc.dcbt.with.hint(i8*, i32)
+declare void @llvm.ppc.dcbtst.with.hint(i8*, i32)

llvm/test/CodeGen/PowerPC/isync.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu < %s \
+; RUN:     -verify-machineinstrs -ppc-asm-full-reg-names \
+; RUN:     -ppc-vsr-nums-as-vr | FileCheck %s
+
+define void @isync_test() {
+; CHECK-LABEL: isync_test:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    isync
+; CHECK-NEXT:    blr
+
+entry:
+  tail call void @llvm.ppc.isync()
+  ret void
+}
+
+declare void @llvm.ppc.isync()