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Differential D79585

[AMDGPU][MC][GFX9+] Enabled clamp for v_add_i32 and v_sub_i32
ClosedPublic

Authored by dp on May 7 2020, 9:37 AM.

Details

Reviewers
arsenm
rampitec
Commits
rG18a5428e6027: [AMDGPU][MC][GFX9+] Enabled clamp for v_add_i32 and v_sub_i32
Summary

Note that these instructions were renamed to v_add_nc_i32 and v_sub_nc_i32 in gfx10. They are corrected as well.

See bug 45830

Diff Detail

Event Timeline

dp created this revision.May 7 2020, 9:37 AM
Herald added a project: Restricted Project. · View Herald TranscriptMay 7 2020, 9:37 AM
Herald added subscribers: llvm-commits, kerbowa, hiraditya and 8 others. · View Herald Transcript
foad added a subscriber: foad.May 8 2020, 1:02 AM
arsenm accepted this revision.May 12 2020, 8:19 AM
This revision is now accepted and ready to land.May 12 2020, 8:19 AM
Closed by commit rG18a5428e6027: [AMDGPU][MC][GFX9+] Enabled clamp for v_add_i32 and v_sub_i32 (authored by dp). · Explain WhyMay 13 2020, 4:48 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
4 lines
test/
MC/
AMDGPU/
6 lines
16 lines
Disassembler/
AMDGPU/
6 lines
5 lines

Diff 262678

llvm/lib/Target/AMDGPU/VOP3Instructions.td

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def V_SUB_I16 : VOP3Inst <"v_sub_i16", VOP3_Profile<VOP_I16_I16_I16, VOP3_OPSEL>>; def V_SUB_I16 : VOP3Inst <"v_sub_i16", VOP3_Profile<VOP_I16_I16_I16, VOP3_OPSEL>>;
def V_MAD_U32_U16 : VOP3Inst <"v_mad_u32_u16", VOP3_Profile<VOP_I32_I16_I16_I32, VOP3_OPSEL>>; def V_MAD_U32_U16 : VOP3Inst <"v_mad_u32_u16", VOP3_Profile<VOP_I32_I16_I16_I32, VOP3_OPSEL>>;
def V_MAD_I32_I16 : VOP3Inst <"v_mad_i32_i16", VOP3_Profile<VOP_I32_I16_I16_I32, VOP3_OPSEL>>; def V_MAD_I32_I16 : VOP3Inst <"v_mad_i32_i16", VOP3_Profile<VOP_I32_I16_I16_I32, VOP3_OPSEL>>;
def V_CVT_PKNORM_I16_F16 : VOP3Inst <"v_cvt_pknorm_i16_f16", VOP3_Profile<VOP_B32_F16_F16, VOP3_OPSEL>>; def V_CVT_PKNORM_I16_F16 : VOP3Inst <"v_cvt_pknorm_i16_f16", VOP3_Profile<VOP_B32_F16_F16, VOP3_OPSEL>>;
def V_CVT_PKNORM_U16_F16 : VOP3Inst <"v_cvt_pknorm_u16_f16", VOP3_Profile<VOP_B32_F16_F16, VOP3_OPSEL>>; def V_CVT_PKNORM_U16_F16 : VOP3Inst <"v_cvt_pknorm_u16_f16", VOP3_Profile<VOP_B32_F16_F16, VOP3_OPSEL>>;
def V_ADD_I32_gfx9 : VOP3Inst <"v_add_i32_gfx9", VOP3_Profile<VOP_I32_I32_I32>>; def V_ADD_I32_gfx9 : VOP3Inst <"v_add_i32_gfx9", VOP3_Profile<VOP_I32_I32_I32_ARITH>>;
def V_SUB_I32_gfx9 : VOP3Inst <"v_sub_i32_gfx9", VOP3_Profile<VOP_I32_I32_I32>>; def V_SUB_I32_gfx9 : VOP3Inst <"v_sub_i32_gfx9", VOP3_Profile<VOP_I32_I32_I32_ARITH>>;
class ThreeOp_i32_Pats <SDPatternOperator op1, SDPatternOperator op2, Instruction inst> : GCNPat < class ThreeOp_i32_Pats <SDPatternOperator op1, SDPatternOperator op2, Instruction inst> : GCNPat <
// This matches (op2 (op1 i32:$src0, i32:$src1), i32:$src2) with conditions. // This matches (op2 (op1 i32:$src0, i32:$src1), i32:$src2) with conditions.
(ThreeOpFrag<op1, op2> i32:$src0, i32:$src1, i32:$src2), (ThreeOpFrag<op1, op2> i32:$src0, i32:$src1, i32:$src2),
(inst VSrc_b32:$src0, VSrc_b32:$src1, VSrc_b32:$src2) (inst VSrc_b32:$src0, VSrc_b32:$src1, VSrc_b32:$src2)
>; >;
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llvm/test/MC/AMDGPU/gfx10_asm_all.s

Context not available.
v_sub_nc_i32 v5, v1, -4.0 v_sub_nc_i32 v5, v1, -4.0
// GFX10: encoding: [0x05,0x00,0x76,0xd7,0x01,0xef,0x01,0x00] // GFX10: encoding: [0x05,0x00,0x76,0xd7,0x01,0xef,0x01,0x00]
v_sub_nc_i32 v5, v1, -4.0 clamp
// GFX10: v_sub_nc_i32 v5, v1, -4.0 clamp ; encoding: [0x05,0x80,0x76,0xd7,0x01,0xef,0x01,0x00]
v_permlane16_b32 v5, v1, v2, v3 v_permlane16_b32 v5, v1, v2, v3
// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
Context not available.
v_add_nc_i32 v5, v1, -4.0 v_add_nc_i32 v5, v1, -4.0
// GFX10: encoding: [0x05,0x00,0x7f,0xd7,0x01,0xef,0x01,0x00] // GFX10: encoding: [0x05,0x00,0x7f,0xd7,0x01,0xef,0x01,0x00]
v_add_nc_i32 v5, v1, -4.0 clamp
// GFX10: v_add_nc_i32 v5, v1, -4.0 clamp ; encoding: [0x05,0x80,0x7f,0xd7,0x01,0xef,0x01,0x00]
v_pk_fmac_f16 v5, v1, v2 v_pk_fmac_f16 v5, v1, v2
// GFX10: encoding: [0x01,0x05,0x0a,0x78] // GFX10: encoding: [0x01,0x05,0x0a,0x78]
Context not available.

llvm/test/MC/AMDGPU/vop3-gfx9.s

Context not available.
// GFX9: v_subrev_co_u32_e32 v84, vcc, v13, v31 ; encoding: [0x0d,0x3f,0xa8,0x36] // GFX9: v_subrev_co_u32_e32 v84, vcc, v13, v31 ; encoding: [0x0d,0x3f,0xa8,0x36]
// NOVI: error: instruction not supported on this GPU // NOVI: error: instruction not supported on this GPU
v_add_i32 v1, v2, v3
// GFX9: v_add_i32 v1, v2, v3 ; encoding: [0x01,0x00,0x9c,0xd2,0x02,0x07,0x02,0x00]
// NOVI: error: instruction not supported on this GPU
v_add_i32 v1, v2, v3 clamp
// GFX9: v_add_i32 v1, v2, v3 clamp ; encoding: [0x01,0x80,0x9c,0xd2,0x02,0x07,0x02,0x00]
// NOVI: error: invalid operand for instruction
v_sub_i32 v1, v2, v3
// GFX9: v_sub_i32 v1, v2, v3 ; encoding: [0x01,0x00,0x9d,0xd2,0x02,0x07,0x02,0x00]
// NOVI: error: instruction not supported on this GPU
v_sub_i32 v1, v2, v3 clamp
// GFX9: v_sub_i32 v1, v2, v3 clamp ; encoding: [0x01,0x80,0x9d,0xd2,0x02,0x07,0x02,0x00]
// NOVI: error: invalid operand for instruction
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Validate register size checks (bug 37943) // Validate register size checks (bug 37943)
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
Context not available.

llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt

Context not available.
# GFX10: v_add_nc_i32 v5, vcc_lo, v2 ; encoding: [0x05,0x00,0x7f,0xd7,0x6a,0x04,0x02,0x00] # GFX10: v_add_nc_i32 v5, vcc_lo, v2 ; encoding: [0x05,0x00,0x7f,0xd7,0x6a,0x04,0x02,0x00]
0x05,0x00,0x7f,0xd7,0x6a,0x04,0x02,0x00 0x05,0x00,0x7f,0xd7,0x6a,0x04,0x02,0x00
# GFX10: v_add_nc_i32 v1, v2, v3 clamp ; encoding: [0x01,0x80,0x7f,0xd7,0x02,0x07,0x02,0x00]
0x01,0x80,0x7f,0xd7,0x02,0x07,0x02,0x00
# GFX10: v_add_nc_u16_e64 v255, v1, v2 ; encoding: [0xff,0x00,0x03,0xd7,0x01,0x05,0x02,0x00] # GFX10: v_add_nc_u16_e64 v255, v1, v2 ; encoding: [0xff,0x00,0x03,0xd7,0x01,0x05,0x02,0x00]
0xff,0x00,0x03,0xd7,0x01,0x05,0x02,0x00 0xff,0x00,0x03,0xd7,0x01,0x05,0x02,0x00
Context not available.
# GFX10: v_sub_nc_i32 v5, vcc_lo, v2 ; encoding: [0x05,0x00,0x76,0xd7,0x6a,0x04,0x02,0x00] # GFX10: v_sub_nc_i32 v5, vcc_lo, v2 ; encoding: [0x05,0x00,0x76,0xd7,0x6a,0x04,0x02,0x00]
0x05,0x00,0x76,0xd7,0x6a,0x04,0x02,0x00 0x05,0x00,0x76,0xd7,0x6a,0x04,0x02,0x00
# GFX10: v_sub_nc_i32 v1, v2, v3 clamp ; encoding: [0x01,0x80,0x76,0xd7,0x02,0x07,0x02,0x00]
0x01,0x80,0x76,0xd7,0x02,0x07,0x02,0x00
# GFX10: v_sub_nc_u16_e64 v255, v1, v2 ; encoding: [0xff,0x00,0x04,0xd7,0x01,0x05,0x02,0x00] # GFX10: v_sub_nc_u16_e64 v255, v1, v2 ; encoding: [0xff,0x00,0x04,0xd7,0x01,0x05,0x02,0x00]
0xff,0x00,0x04,0xd7,0x01,0x05,0x02,0x00 0xff,0x00,0x04,0xd7,0x01,0x05,0x02,0x00
Context not available.

llvm/test/MC/Disassembler/AMDGPU/vop3_gfx9.txt

Context not available.
# GFX9: v_subrev_co_u32_e64 v84, vcc, v13, v31 clamp ; encoding: [0x54,0xea,0x1b,0xd1,0x0d,0x3f,0x02,0x00] # GFX9: v_subrev_co_u32_e64 v84, vcc, v13, v31 clamp ; encoding: [0x54,0xea,0x1b,0xd1,0x0d,0x3f,0x02,0x00]
0x54,0xea,0x1b,0xd1,0x0d,0x3f,0x02,0x00 0x54,0xea,0x1b,0xd1,0x0d,0x3f,0x02,0x00
# GFX9: v_add_i32 v1, v2, v3 clamp ; encoding: [0x01,0x80,0x9c,0xd2,0x02,0x07,0x02,0x00]
0x01,0x80,0x9c,0xd2,0x02,0x07,0x02,0x00
# GFX9: v_sub_i32 v1, v2, v3 clamp ; encoding: [0x01,0x80,0x9d,0xd2,0x02,0x07,0x02,0x00]
0x01,0x80,0x9d,0xd2,0x02,0x07,0x02,0x00
Context not available.