[X86] Remove support some inline assembly constraints that are no longer supported by gcc.

[craig.topper]

Summary

This removes the Y0, Yi, Yt, Y2, Ym, and Y constraints.

[spatel]

llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp

154–156

Unrelated diff?

[craig.topper]

I committed part of this, but got nervous when I found icc supported some of this. Still need to check our internal tests to see if they are used.

clang/lib/Basic/Targets/X86.cpp

 //===--- X86.cpp - Implement X86 target feature support -------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
bool X86TargetInfo::validateOperandSize(const llvm::StringMap<bool> &FeatureMap,
   case 't':
   case 'u':
     return Size <= 128;
   case 'Y':
     // 'Y' is the first character for several 2-character constraints.
     switch (Constraint[1]) {
     default:
       return false;
-    case 'm':
-      // 'Ym' is synonymous with 'y'.
     case 'k':
       return Size <= 64;
     case 'z':
-    case '0':
       // XMM0/YMM/ZMM0
       if (FeatureMap.lookup("avx512f"))
         // ZMM0 can be used if target supports AVX512F.
         return Size <= 512U;
       else if (FeatureMap.lookup("avx"))
         // YMM0 can be used if target supports AVX.
         return Size <= 256U;
       else if (FeatureMap.lookup("sse"))
         return Size <= 128U;
       return false;
-    case 'i':
-    case 't':
-    case '2':
-      // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled.
-      if (SSELevel < SSE2)
-        return false;
-      break;
     }
-    LLVM_FALLTHROUGH;
+    break;
   case 'v':
   case 'x':
     if (FeatureMap.lookup("avx512f"))
       // 512-bit zmm registers can be used if target supports AVX512F.
       return Size <= 512U;
     else if (FeatureMap.lookup("avx"))
       // 256-bit ymm registers can be used if target supports AVX.
       return Size <= 256U;
     return Size <= 128U;
-
   }
 
   return true;
 }
 
 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const {
   switch (*Constraint) {
   case '@':
std::string X86TargetInfo::convertConstraint(const char *&Constraint) const {
   case 'Y':
     switch (Constraint[1]) {
     default:
       // Break from inner switch and fall through (copy single char),
       // continue parsing after copying the current constraint into
       // the return string.
       break;
     case 'k':
-    case 'm':
-    case 'i':
-    case 't':
     case 'z':
-    case '0':
-    case '2':
       // "^" hints llvm that this is a 2 letter constraint.
       // "Constraint++" is used to promote the string iterator
       // to the next constraint.
       return std::string("^") + std::string(Constraint++, 2);
     }
     LLVM_FALLTHROUGH;
   default:
     return std::string(1, *Constraint);

clang/test/CodeGen/x86-GCC-inline-asm-Y-constraints.c

 // RUN: %clang_cc1 -ffreestanding  -triple=x86_64-apple-darwin -target-cpu skx %s -emit-llvm -o - | FileCheck %s
 #include <xmmintrin.h>
 // This test is complimented by the .ll test under llvm/test/MC/X86/. 
 // At this level we can only check if the constarints are passed correctly
 // from inline asm to llvm IR.
 
-// CHECK-LABEL: @f_Ym
-void f_Ym(__m64 m)
-  {
-  // CHECK: movq  $0, %mm1
-  // CHECK-SAME: "=^Ym,~{dirflag},~{fpsr},~{flags}"
-  __asm__ volatile ("movq %0, %%mm1\n\t"
-          :"=Ym" (m));
-}
-
-// CHECK-LABEL: f_Yi
-void f_Yi(__m128 x, __m128 y, __m128 z)
-  {
-  // CHECK: vpaddq
-  // CHECK-SAME: "=^Yi,^Yi,^Yi,~{dirflag},~{fpsr},~{flags}"
-  __asm__ volatile ("vpaddq %0, %1, %2\n\t"
-          :"=Yi" (x)
-          :"Yi" (y),"Yi"(z));
-}
-
-// CHECK-LABEL: f_Yt
-void f_Yt(__m128 x, __m128 y, __m128 z)
-  {
-  // CHECK: vpaddq
-  // CHECK-SAME: "=^Yt,^Yt,^Yt,~{dirflag},~{fpsr},~{flags}"
-  __asm__ volatile ("vpaddq %0, %1, %2\n\t"
-          :"=Yt" (x)
-          :"Yt" (y),"Yt"(z));
-}
-
-// CHECK-LABEL: f_Y2
-void f_Y2(__m128 x, __m128 y, __m128 z)
-    {
-  // CHECK: vpaddq
-  // CHECK-SAME: "=^Y2,^Y2,^Y2,~{dirflag},~{fpsr},~{flags}"
-  __asm__ volatile ("vpaddq %0, %1, %2\n\t"
-            :"=Y2" (x)
-            :"Y2" (y),"Y2"(z));
-}
-
 // CHECK-LABEL: f_Yz
 void f_Yz(__m128 x, __m128 y, __m128 z)
   {
   // CHECK: vpaddq
   // CHECK-SAME: vpaddq
-  // CHECK-SAME: "=^Yi,=^Yz,^Yi,0,~{dirflag},~{fpsr},~{flags}"
+  // CHECK-SAME: "=x,=^Yz,x,0,~{dirflag},~{fpsr},~{flags}"
   __asm__ volatile ("vpaddq %0,%2,%1\n\t"
        "vpaddq %1,%0,%2\n\t"
-          :"+Yi"(z),"=Yz" (x)
-          :"Yi" (y) );
+          :"+x"(z),"=Yz" (x)
+          :"x" (y) );
 }
-
-// CHECK-LABEL: f_Y0
-void f_Y0(__m128 x, __m128 y, __m128 z)
-  {
-  // CHECK: vpaddq
-  // CHECK-SAME: "=^Yi,=^Y0,^Yi,0,~{dirflag},~{fpsr},~{flags}"
-  __asm__ volatile ("vpaddq %0,%2,%1\n\t"
-          "vpaddq %1,%0,%2\n\t"
-          :"+Yi"(z),"=Y0" (x)
-          :"Yi" (y) );
-}
-

llvm/lib/Target/X86/X86ISelLowering.cpp

     case 'q':
     case 'Q':
     case 'f':
     case 't':
     case 'u':
     case 'y':
     case 'x':
     case 'v':
-    case 'Y':
     case 'l':
     case 'k': // AVX512 masking registers.
       return C_RegisterClass;
     case 'a':
     case 'b':
     case 'c':
     case 'd':
     case 'S':

     switch (Constraint[0]) {
     default:
       break;
     case 'Y':
       switch (Constraint[1]) {
       default:
         break;
       case 'z':
-      case '0':
         return C_Register;
-      case 'i':
-      case 'm':
       case 'k':
-      case 't':
-      case '2':
         return C_RegisterClass;
       }
     }
   } else if (parseConstraintCode(Constraint) != X86::COND_INVALID)
     return C_Other;
   return TargetLowering::getConstraintType(Constraint);
 }
 

     if (type->isFloatingPointTy())
       weight = CW_SpecificReg;
     break;
   case 'y':
     if (type->isX86_MMXTy() && Subtarget.hasMMX())
       weight = CW_SpecificReg;
     break;
   case 'Y': {
-    unsigned Size = StringRef(constraint).size();
-    // Pick 'i' as the next char as 'Yi' and 'Y' are synonymous, when matching 'Y'
-    char NextChar = Size == 2 ? constraint[1] : 'i';
-    if (Size > 2)
+    if (StringRef(constraint).size() != 2)
       break;
-    switch (NextChar) {
+    switch (constraint[1]) {
       default:
         return CW_Invalid;
       // XMM0
       case 'z':
-      case '0':
         if (((type->getPrimitiveSizeInBits() == 128) && Subtarget.hasSSE1()) ||
             ((type->getPrimitiveSizeInBits() == 256) && Subtarget.hasAVX()) ||
             ((type->getPrimitiveSizeInBits() == 512) && Subtarget.hasAVX512()))
           return CW_SpecificReg;
         return CW_Invalid;
       // Conditional OpMask regs (AVX512)
       case 'k':
         if ((type->getPrimitiveSizeInBits() == 64) && Subtarget.hasAVX512())
           return CW_Register;
         return CW_Invalid;
-      // Any MMX reg
-      case 'm':
-        if (type->isX86_MMXTy() && Subtarget.hasMMX())
-          return weight;
-        return CW_Invalid;
-      // Any SSE reg when ISA >= SSE2, same as 'Y'
-      case 'i':
-      case 't':
-      case '2':
-        if (!Subtarget.hasSSE2())
-          return CW_Invalid;
-        break;
     }
-    // Fall through (handle "Y" constraint).
-    LLVM_FALLTHROUGH;
+    break;
   }
   case 'v':
     if ((type->getPrimitiveSizeInBits() == 512) && Subtarget.hasAVX512())
       weight = CW_Register;
     LLVM_FALLTHROUGH;
   case 'x':
     if (((type->getPrimitiveSizeInBits() == 128) && Subtarget.hasSSE1()) ||
         ((type->getPrimitiveSizeInBits() == 256) && Subtarget.hasAVX()))

 /// Try to replace an X constraint, which matches anything, with another that
 /// has more specific requirements based on the type of the corresponding
 /// operand.
 const char *X86TargetLowering::
 LowerXConstraint(EVT ConstraintVT) const {
   // FP X constraints get lowered to SSE1/2 registers if available, otherwise
   // 'f' like normal targets.
   if (ConstraintVT.isFloatingPoint()) {
-    if (Subtarget.hasSSE2())
-      return "Y";
     if (Subtarget.hasSSE1())
       return "x";
   }
 
   return TargetLowering::LowerXConstraint(ConstraintVT);
 }
 
 // Lower @cc targets via setcc.

       if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
         return std::make_pair(0U, &X86::RFP32RegClass);
       if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
         return std::make_pair(0U, &X86::RFP64RegClass);
       return std::make_pair(0U, &X86::RFP80RegClass);
     case 'y':   // MMX_REGS if MMX allowed.
       if (!Subtarget.hasMMX()) break;
       return std::make_pair(0U, &X86::VR64RegClass);
-    case 'Y':   // SSE_REGS if SSE2 allowed
-      if (!Subtarget.hasSSE2()) break;
-      LLVM_FALLTHROUGH;
     case 'v':
     case 'x':   // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
       if (!Subtarget.hasSSE1()) break;
       bool VConstraint = (Constraint[0] == 'v');
 
       switch (VT.SimpleTy) {
       default: break;
       // Scalar SSE types.

         return std::make_pair(0U, &X86::VR512_0_15RegClass);
       }
       break;
     }
   } else if (Constraint.size() == 2 && Constraint[0] == 'Y') {
     switch (Constraint[1]) {
     default:
       break;
-    case 'i':
-    case 't':
-    case '2':
-      return getRegForInlineAsmConstraint(TRI, "Y", VT);
-    case 'm':
-      if (!Subtarget.hasMMX()) break;
-      return std::make_pair(0U, &X86::VR64RegClass);
     case 'z':
-    case '0':
       if (!Subtarget.hasSSE1()) break;
       switch (VT.SimpleTy) {
       default: break;
       // Scalar SSE types.
       case MVT::f32:
       case MVT::i32:
         return std::make_pair(X86::XMM0, &X86::FR32RegClass);
       case MVT::f64:

llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp

 //===- InstCombineCasts.cpp -----------------------------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
Instruction *InstCombiner::PromoteCastOfAllocation(BitCastInst &CI,
   New->setUsedWithInAlloca(AI.isUsedWithInAlloca());
 
   // If the allocation has multiple real uses, insert a cast and change all
   // things that used it to use the new cast.  This will also hack on CI, but it
   // will die soon.
   if (!AI.hasOneUse()) {
     // New is the allocation instruction, pointer typed. AI is the original
     // allocation instruction, also pointer typed. Thus, cast to use is BitCast.
+    BasicBlock::iterator It(New);
+    while (isa<AllocaInst>(*It) || isa<DbgInfoIntrinsic>(*It))
+      ++It;
+
     Value *NewCast = Builder.CreateBitCast(New, AI.getType(), "tmpcast");
     replaceInstUsesWith(AI, NewCast);
     eraseInstFromFunction(AI);
   }
   return replaceInstUsesWith(CI, New);
 }
 
 /// Given an expression that CanEvaluateTruncated or CanEvaluateSExtd returns

llvm/test/MC/X86/x86-GCC-inline-asm-Y-constraints.ll

 ; RUN: llc -mtriple=x86_64-apple-darwin -mcpu skx < %s | FileCheck %s
 ; This test compliments the .c test under clang/test/CodeGen/. We check 
 ; if the inline asm constraints are respected in the generated code.
 
 ; Function Attrs: nounwind
-define void @f_Ym(i64 %m.coerce) {
-; Any mmx regiter constraint
-; CHECK-LABEL: f_Ym:
-; CHECK:         ## InlineAsm Start
-; CHECK-NEXT:    movq %mm{{[0-9]+}}, %mm1
-; CHECK:         ## InlineAsm End
-
-entry:
-  %0 = tail call x86_mmx asm sideeffect "movq $0, %mm1\0A\09", "=^Ym,~{dirflag},~{fpsr},~{flags}"() 
-  ret void
-}
-
-; Function Attrs: nounwind
-define void @f_Yi(<4 x float> %x, <4 x float> %y, <4 x float> %z) {
-; Any SSE register when SSE2 is enabled (GCC when inter-unit moves enabled)
-; CHECK-LABEL: f_Yi:
-; CHECK:         ## InlineAsm Start
-; CHECK-NEXT:    vpaddq %xmm{{[0-9]+}}, %xmm{{[0-9]+}}, %xmm{{[0-9]+}}
-; CHECK:         ## InlineAsm End
-
-entry:
-  %0 = tail call <4 x float> asm sideeffect "vpaddq $0, $1, $2\0A\09", "=^Yi,^Yi,^Yi,~{dirflag},~{fpsr},~{flags}"(<4 x float> %y, <4 x float> %z) 
-  ret void
-}
-
-; Function Attrs: nounwind
-define void @f_Yt(<4 x float> %x, <4 x float> %y, <4 x float> %z) {
-; Any SSE register when SSE2 is enabled
-; CHECK-LABEL: f_Yt:
-; CHECK:         ## InlineAsm Start
-; CHECK-NEXT:    vpaddq %xmm{{[0-9]+}}, %xmm{{[0-9]+}}, %xmm{{[0-9]+}}
-; CHECK:         ## InlineAsm End
-
-entry:
-  %0 = tail call <4 x float> asm sideeffect "vpaddq $0, $1, $2\0A\09", "=^Yt,^Yt,^Yt,~{dirflag},~{fpsr},~{flags}"(<4 x float> %y, <4 x float> %z)
-  ret void
-}
-
-; Function Attrs: nounwind
-define void @f_Y2(<4 x float> %x, <4 x float> %y, <4 x float> %z) {
-; Any SSE register when SSE2 is enabled
-; CHECK-LABEL: f_Y2:
-; CHECK:         ## InlineAsm Start
-; CHECK-NEXT:    vpaddq %xmm{{[0-9]+}}, %xmm{{[0-9]+}}, %xmm{{[0-9]+}}
-; CHECK:         ## InlineAsm End
-
-entry:
-  %0 = tail call <4 x float> asm sideeffect "vpaddq $0, $1, $2\0A\09", "=^Y2,^Y2,^Y2,~{dirflag},~{fpsr},~{flags}"(<4 x float> %y, <4 x float> %z)
-  ret void
-}
-
-; Function Attrs: nounwind
 define void @f_Yz(<4 x float> %x, <4 x float> %y, <4 x float> %z) {
 ; xmm0 SSE register(GCC)
 ; CHECK-LABEL: f_Yz:
 ; CHECK:         ## InlineAsm Start
 ; CHECK-NEXT:    vpaddq %xmm{{[0-9]+}}, %xmm{{[0-9]+}}, %xmm0
 ; CHECK-NEXT:    vpaddq %xmm0, %xmm{{[0-9]+}}, %xmm{{[0-9]+}}
 ; CHECK:         ## InlineAsm End
 entry:
-  %0 = tail call { <4 x float>, <4 x float> } asm sideeffect "vpaddq $0,$2,$1\0A\09vpaddq $1,$0,$2\0A\09", "=^Yi,=^Yz,^Yi,0,~{dirflag},~{fpsr},~{flags}"(<4 x float> %y, <4 x float> %z)
+  %0 = tail call { <4 x float>, <4 x float> } asm sideeffect "vpaddq $0,$2,$1\0A\09vpaddq $1,$0,$2\0A\09", "=x,=^Yz,x,0,~{dirflag},~{fpsr},~{flags}"(<4 x float> %y, <4 x float> %z)
   ret void
 }
-
-; Function Attrs: nounwind
-define void @f_Y0(<4 x float> %x, <4 x float> %y, <4 x float> %z) {
-; xmm0 SSE register
-; CHECK-LABEL: f_Y0:
-; CHECK:         ## InlineAsm Start
-; CHECK-NEXT:    vpaddq %xmm{{[0-9]+}}, %xmm{{[0-9]+}}, %xmm0
-; CHECK-NEXT:    vpaddq %xmm0, %xmm{{[0-9]+}}, %xmm{{[0-9]+}}
-; CHECK:         ## InlineAsm End
-
-entry:
-  %0 = tail call { <4 x float>, <4 x float> } asm sideeffect "vpaddq $0,$2,$1\0A\09vpaddq $1,$0,$2\0A\09", "=^Yi,=^Y0,^Yi,0,~{dirflag},~{fpsr},~{flags}"(<4 x float> %y, <4 x float> %z)
-  ret void
-}
-