[RISCV][NFC] Add Test for (select (or B1, B2), X, Y)

[lenary]

Summary

As shown, LLVM is keen to avoid logic and introduce selects (in DAGCombiner, and
other places). This leads to control flow on RISC-V which we should attempt to
avoid.

[luismarques]

LGTM.

llvm/test/CodeGen/RISCV/select-or.ll

7–8

Nit: if the codegen improvement isn't expected to be merged quickly then consider writing something more generic like "illustrates whether we use conditional jumps or additional logic", since for now it might be a bit confusing that the test does generate several branches.

[lenary]

Update comment in test to more generally talk about what the test is looking
for, rather than the specific hook in the optimisation.

[lenary]

I might actually add a few other tests, given i know (select (and A, B), C, D) is also a pattern that appears places.

[lenary]

• Added (select (and A, B), X, Y) test.

[lenary]

• Expand select(or/and) tests to include if(or/and) cases

[lenary]

• Simplify and test to ensure branchy code is generated.

llvm/test/CodeGen/RISCV/select-or.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV32I %s
+; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV64I %s
+
+;; This tests that we don't unneccessarily introduce too many selects, where we
+;; could instead do more complex logic before a single select.
+
+define signext i32 @select_of_or(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind {
+; RV32I-LABEL: select_of_or:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    mv a4, a0
+; RV32I-NEXT:    bne a2, a3, .LBB0_3
+; RV32I-NEXT:  # %bb.1:
+; RV32I-NEXT:    bne a0, a1, .LBB0_4
+; RV32I-NEXT:  .LBB0_2:
+; RV32I-NEXT:    ret
+; RV32I-NEXT:  .LBB0_3:
+; RV32I-NEXT:    mv a4, a1
+; RV32I-NEXT:    beq a0, a1, .LBB0_2
+; RV32I-NEXT:  .LBB0_4:
+; RV32I-NEXT:    mv a0, a4
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: select_of_or:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    mv a4, a0
+; RV64I-NEXT:    bne a2, a3, .LBB0_3
+; RV64I-NEXT:  # %bb.1:
+; RV64I-NEXT:    bne a0, a1, .LBB0_4
+; RV64I-NEXT:  .LBB0_2:
+; RV64I-NEXT:    ret
+; RV64I-NEXT:  .LBB0_3:
+; RV64I-NEXT:    mv a4, a1
+; RV64I-NEXT:    beq a0, a1, .LBB0_2
+; RV64I-NEXT:  .LBB0_4:
+; RV64I-NEXT:    mv a0, a4
+; RV64I-NEXT:    ret
+  %1 = icmp eq i32 %a, %b
+  %2 = icmp eq i32 %c, %d
+  %3 = or i1 %1, %2
+  %4 = select i1 %3, i32 %a, i32 %b
+  ret i32 %4
+}