[PowerPC-QPX] adjust operands order of qpx vector fma instructions.

[shchenz]

Summary

Now after isel, operand order for qpx vector fma instruction qvfmadd is like:

%3 = QVFMADD %2, %0, %1, implicit $rm

This stands for %3 = %2 * %1 + %0. This is a little different with QPX ISA's description and also not same with other Power arch vector fma instrucions, like xvmaddadp

It should be like %3 = QVFMADD %2, %1, %0, implicit $rm

[shchenz]

rebase

[steven.zhang]

llvm/lib/Target/PowerPC/PPCInstrQPX.td

179

So what about the QVFNMADD ? And it would be great if you could post the ISA definition of QPX FMA instruction here.

[shchenz]

add more opcodes and test cases

[shchenz]

Thanks for your quick review. Patch updated.

llvm/lib/Target/PowerPC/PPCInstrQPX.td

179

QVFNMADD should have same issue. I already add it together with msub related opcodes.

Here is QPX ISA (May 9, 2012) says about QVFMADD:

4.4.2 Quad-Vector Floating-Point Multiply-Add Instructions

qvfmadds QRT,QRA,QRC,QRB

The operations are performed:
QRT0 ← [(QRA0)×(QRC0)] + (QRB0) 
QRT1 ← [(QRA1)×(QRC1)] + (QRB1) 
QRT2 ← [(QRA2)×(QRC2)] + (QRB2) 
QRT3 ← [(QRA3)×(QRC3)] + (QRB3)

[steven.zhang]

llvm/lib/Target/PowerPC/PPCInstrQPX.td

902

This is not right as we didn't respect the nsz flag here. But it is not relative with this patch. D76585 miss to handle the QPX. @qiucf

[hfinkel]

This LGTM for consistency. Also, it reminds me that it's probably time for an RFC to remove QPX support in general.

[jsji]

Good suggestion. Will you send the RFC? Or you would like us to send it? Thanks. @hfinkel

[shchenz]

Thanks for reviewing. @hfinkel . Since you already sent RFC about removing the QPX support, I will hold this patch until we get the decision.

[shchenz]

I will commit this first as I have one patch based on this.
if we start to remove qpx support in future, this should be easy to delete.

llvm/lib/Target/PowerPC/PPCInstrQPX.td

def QVFMULSs : AForm_3<0, 25,
                           "qvfmuls $FRT, $FRA, $FRC", IIC_FPGeneral,
                           [(set v4f32:$FRT, (fmul v4f32:$FRA, v4f32:$FRC))]>;
   }
   def QVFXMUL : QPXA3_Int<4, 17, "qvfxmul", int_ppc_qpx_qvfxmul>;
   def QVFXMULS : QPXA3_Int<0, 17, "qvfxmuls", int_ppc_qpx_qvfxmuls>;
 
   // Multiply-add instructions
   def QVFMADD : AForm_1<4, 29,
-                      (outs qfrc:$FRT), (ins qfrc:$FRA, qfrc:$FRB, qfrc:$FRC),
+                      (outs qfrc:$FRT), (ins qfrc:$FRA, qfrc:$FRC, qfrc:$FRB),
                       "qvfmadd $FRT, $FRA, $FRC, $FRB", IIC_FPFused,
                       [(set v4f64:$FRT, (fma v4f64:$FRA, v4f64:$FRC, v4f64:$FRB))]>;
   let isCodeGenOnly = 1 in
     def QVFMADDS : QPXA1_Int<0, 29, "qvfmadds", int_ppc_qpx_qvfmadds>;
   def QVFMADDSs : AForm_1<0, 29,
-                        (outs qsrc:$FRT), (ins qsrc:$FRA, qsrc:$FRB, qsrc:$FRC),
+                        (outs qsrc:$FRT), (ins qsrc:$FRA, qsrc:$FRC, qsrc:$FRB),
                         "qvfmadds $FRT, $FRA, $FRC, $FRB", IIC_FPFused,
                         [(set v4f32:$FRT, (fma v4f32:$FRA, v4f32:$FRC, v4f32:$FRB))]>;
   def QVFNMADD : AForm_1<4, 31,
-                      (outs qfrc:$FRT), (ins qfrc:$FRA, qfrc:$FRB, qfrc:$FRC),
+                      (outs qfrc:$FRT), (ins qfrc:$FRA, qfrc:$FRC, qfrc:$FRB),
                       "qvfnmadd $FRT, $FRA, $FRC, $FRB", IIC_FPFused,
                       [(set v4f64:$FRT, (fneg (fma v4f64:$FRA, v4f64:$FRC,
                                                    v4f64:$FRB)))]>;
   let isCodeGenOnly = 1 in
     def QVFNMADDS : QPXA1_Int<0, 31, "qvfnmadds", int_ppc_qpx_qvfnmadds>;
   def QVFNMADDSs : AForm_1<0, 31,
-                        (outs qsrc:$FRT), (ins qsrc:$FRA, qsrc:$FRB, qsrc:$FRC),
+                        (outs qsrc:$FRT), (ins qsrc:$FRA, qsrc:$FRC, qsrc:$FRB),
                         "qvfnmadds $FRT, $FRA, $FRC, $FRB", IIC_FPFused,
                         [(set v4f32:$FRT, (fneg (fma v4f32:$FRA, v4f32:$FRC,
                                                      v4f32:$FRB)))]>;
   def QVFMSUB : AForm_1<4, 28,
-                      (outs qfrc:$FRT), (ins qfrc:$FRA, qfrc:$FRB, qfrc:$FRC),
+                      (outs qfrc:$FRT), (ins qfrc:$FRA, qfrc:$FRC, qfrc:$FRB),
                       "qvfmsub $FRT, $FRA, $FRC, $FRB", IIC_FPFused,
                       [(set v4f64:$FRT, (fma v4f64:$FRA, v4f64:$FRC,
                                              (fneg v4f64:$FRB)))]>;
   let isCodeGenOnly = 1 in
     def QVFMSUBS : QPXA1_Int<0, 28, "qvfmsubs", int_ppc_qpx_qvfmsubs>;
   def QVFMSUBSs : AForm_1<0, 28,
-                      (outs qsrc:$FRT), (ins qsrc:$FRA, qsrc:$FRB, qsrc:$FRC),
+                      (outs qsrc:$FRT), (ins qsrc:$FRA, qsrc:$FRC, qsrc:$FRB),
                       "qvfmsubs $FRT, $FRA, $FRC, $FRB", IIC_FPFused,
                       [(set v4f32:$FRT, (fma v4f32:$FRA, v4f32:$FRC,
                                              (fneg v4f32:$FRB)))]>;
   def QVFNMSUB : AForm_1<4, 30,
-                      (outs qfrc:$FRT), (ins qfrc:$FRA, qfrc:$FRB, qfrc:$FRC),
+                      (outs qfrc:$FRT), (ins qfrc:$FRA, qfrc:$FRC, qfrc:$FRB),
                       "qvfnmsub $FRT, $FRA, $FRC, $FRB", IIC_FPFused,
                       [(set v4f64:$FRT, (fneg (fma v4f64:$FRA, v4f64:$FRC,
                                               (fneg v4f64:$FRB))))]>;
   let isCodeGenOnly = 1 in
     def QVFNMSUBS : QPXA1_Int<0, 30, "qvfnmsubs", int_ppc_qpx_qvfnmsubs>;
   def QVFNMSUBSs : AForm_1<0, 30,
-                      (outs qsrc:$FRT), (ins qsrc:$FRA, qsrc:$FRB, qsrc:$FRC),
+                      (outs qsrc:$FRT), (ins qsrc:$FRA, qsrc:$FRC, qsrc:$FRB),
                       "qvfnmsubs $FRT, $FRA, $FRC, $FRB", IIC_FPFused,
                       [(set v4f32:$FRT, (fneg (fma v4f32:$FRA, v4f32:$FRC,
                                               (fneg v4f32:$FRB))))]>;
   def QVFXMADD : QPXA1_Int<4, 9, "qvfxmadd", int_ppc_qpx_qvfxmadd>;
   def QVFXMADDS : QPXA1_Int<0, 9, "qvfxmadds", int_ppc_qpx_qvfxmadds>;
   def QVFXXNPMADD : QPXA1_Int<4, 11, "qvfxxnpmadd", int_ppc_qpx_qvfxxnpmadd>;
   def QVFXXNPMADDS : QPXA1_Int<0, 11, "qvfxxnpmadds", int_ppc_qpx_qvfxxnpmadds>;
   def QVFXXCPNMADD : QPXA1_Int<4, 3, "qvfxxcpnmadd", int_ppc_qpx_qvfxxcpnmadd>;
def : Pat<(int_ppc_qpx_qvfadd v4f64:$A, v4f64:$B),
           (QVFADD $A, $B)>;
 def : Pat<(int_ppc_qpx_qvfsub v4f64:$A, v4f64:$B),
           (QVFSUB $A, $B)>;
 def : Pat<(int_ppc_qpx_qvfmul v4f64:$A, v4f64:$B),
           (QVFMUL $A, $B)>;
 
 // Additional QVFNMSUB patterns: -a*c + b == -(a*c - b)
 def : Pat<(fma (fneg v4f64:$A), v4f64:$C, v4f64:$B),
-          (QVFNMSUB $A, $B, $C)>;
+          (QVFNMSUB $A, $C, $B)>;
 def : Pat<(fma v4f64:$A, (fneg v4f64:$C), v4f64:$B),
-          (QVFNMSUB $A, $B, $C)>;
+          (QVFNMSUB $A, $C, $B)>;
 def : Pat<(fma (fneg v4f32:$A), v4f32:$C, v4f32:$B),
-          (QVFNMSUBSs $A, $B, $C)>;
+          (QVFNMSUBSs $A, $C, $B)>;
 def : Pat<(fma v4f32:$A, (fneg v4f32:$C), v4f32:$B),
-          (QVFNMSUBSs $A, $B, $C)>;
+          (QVFNMSUBSs $A, $C, $B)>;
 
 def : Pat<(int_ppc_qpx_qvfmadd v4f64:$A, v4f64:$B, v4f64:$C),
           (QVFMADD $A, $B, $C)>;
 def : Pat<(int_ppc_qpx_qvfnmadd v4f64:$A, v4f64:$B, v4f64:$C),
           (QVFNMADD $A, $B, $C)>;
 def : Pat<(int_ppc_qpx_qvfmsub v4f64:$A, v4f64:$B, v4f64:$C),
           (QVFMSUB $A, $B, $C)>;
 def : Pat<(int_ppc_qpx_qvfnmsub v4f64:$A, v4f64:$B, v4f64:$C),

llvm/test/CodeGen/PowerPC/qpx-qvfmadd.ll

 ; RUN: llc -verify-machineinstrs -stop-after=finalize-isel < %s -mcpu=a2q | FileCheck %s
 target triple = "powerpc64-bgq-linux"
 
 define <2 x double> @test_qvfmadd(<2 x double> %0, <2 x double> %1, <2 x double> %2) {
 ; CHECK: test_qvfmadd
-; CHECK: QVFMADD %2, %0, %1, implicit $rm
+; CHECK: QVFMADD %2, %1, %0, implicit $rm
 ;
   %4 = fmul reassoc nsz <2 x double> %2, %1
   %5 = fadd reassoc nsz <2 x double> %4, %0
   ret <2 x double> %5
 }
 
 define <4 x float> @test_qvfmadds(<4 x float> %0, <4 x float> %1, <4 x float> %2) {
 ; CHECK: test_qvfmadds
-; CHECK: QVFMADDSs %2, %0, %1, implicit $rm
+; CHECK: QVFMADDSs %2, %1, %0, implicit $rm
 ;
   %4 = fmul reassoc nsz <4 x float> %2, %1
   %5 = fadd reassoc nsz <4 x float> %4, %0
   ret <4 x float> %5
 }
 
 define <2 x double> @test_qvfnmadd(<2 x double> %0, <2 x double> %1, <2 x double> %2) {
 ; CHECK: test_qvfnmadd
-; CHECK: QVFNMADD %2, %0, %1, implicit $rm
+; CHECK: QVFNMADD %2, %1, %0, implicit $rm
 ;
   %4 = fmul reassoc nsz <2 x double> %2, %1
   %5 = fadd reassoc nsz <2 x double> %4, %0
   %6 = fneg reassoc nsz <2 x double> %5
   ret <2 x double> %6
 }
 
 define <4 x float> @test_qvfnmadds(<4 x float> %0, <4 x float> %1, <4 x float> %2) {
 ; CHECK: test_qvfnmadds
-; CHECK: QVFNMADDSs %2, %0, %1, implicit $rm
+; CHECK: QVFNMADDSs %2, %1, %0, implicit $rm
 ;
   %4 = fmul reassoc nsz <4 x float> %2, %1
   %5 = fadd reassoc nsz <4 x float> %4, %0
   %6 = fneg reassoc nsz <4 x float> %5
   ret <4 x float> %6
 }
 
 define <2 x double> @test_qvfmsub(<2 x double> %0, <2 x double> %1, <2 x double> %2) {
 ; CHECK: test_qvfmsub
-; CHECK: QVFMSUB %2, %0, %1, implicit $rm
+; CHECK: QVFMSUB %2, %1, %0, implicit $rm
 ;
   %4 = fmul reassoc nsz <2 x double> %2, %1
   %5 = fsub reassoc nsz <2 x double> %4, %0
   ret <2 x double> %5
 }
 
 define <4 x float> @test_qvfmsubs(<4 x float> %0, <4 x float> %1, <4 x float> %2) {
 ; CHECK: test_qvfmsubs
-; CHECK: QVFMSUBSs %2, %0, %1, implicit $rm
+; CHECK: QVFMSUBSs %2, %1, %0, implicit $rm
 ;
   %4 = fmul reassoc nsz <4 x float> %2, %1
   %5 = fsub reassoc nsz <4 x float> %4, %0
   ret <4 x float> %5
 }
 
 define <2 x double> @test_qvfnmsub(<2 x double> %0, <2 x double> %1, <2 x double> %2) {
 ; CHECK: test_qvfnmsub
-; CHECK: QVFNMSUB %2, %0, %1, implicit $rm
+; CHECK: QVFNMSUB %2, %1, %0, implicit $rm
 ;
   %4 = fmul reassoc nsz <2 x double> %2, %1
   %5 = fsub reassoc nsz <2 x double> %4, %0
   %6 = fneg reassoc nsz <2 x double> %5
   ret <2 x double> %6
 }
 
 define <4 x float> @test_qvfnmsubs(<4 x float> %0, <4 x float> %1, <4 x float> %2) {
 ; CHECK: test_qvfnmsubs
-; CHECK: QVFNMSUBSs %2, %0, %1, implicit $rm
+; CHECK: QVFNMSUBSs %2, %1, %0, implicit $rm
 ;
   %4 = fmul reassoc nsz <4 x float> %2, %1
   %5 = fsub reassoc nsz <4 x float> %4, %0
   %6 = fneg reassoc nsz <4 x float> %5
   ret <4 x float> %6
 }