[RISCV] RISCBoy Scheduling Model

[lenary]

Summary

As a way to learn how to write a Scheduling Model for RISC-V cores, I decided to
see if I could write one for a well-documented open-source core.

I'm not sure if I have all the information in the model correct yet, in
particular I know RISCBoy has some forwarding that I don't think I've modelled,
and I probably missed how to correctly model a five-stage in-order pipeline.

[lenary]

I still need to implement Forwarding, LoopMicroOpBufferSize should definitely be zero, and the whole model should refer to the Core, which is now officially called Hazard5 (and is being used in more projects).

llvm/lib/Target/RISCV/RISCV.td

 
 include "RISCVSchedule.td"
 include "RISCVRegisterInfo.td"
 include "RISCVCallingConv.td"
 include "RISCVInstrInfo.td"
 include "RISCVRegisterBanks.td"
 include "RISCVSchedRocket32.td"
 include "RISCVSchedRocket64.td"
+include "RISCVSchedRISCBoy.td"
 
 //===----------------------------------------------------------------------===//
 // RISC-V processors supported.
 //===----------------------------------------------------------------------===//
 
 def : ProcessorModel<"generic-rv32", NoSchedModel, [FeatureRVCHints]>;
 
 def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit,
                      FeatureRVCHints]>;
 
 def : ProcessorModel<"rocket-rv32", Rocket32Model, [FeatureRVCHints]>;
 
 def : ProcessorModel<"rocket-rv64", Rocket64Model, [Feature64Bit,
                      FeatureRVCHints]>;
 
+// https://github.com/Wren6991/RISCBoy
+def : ProcessorModel<"riscboy", RISCBoyModel, [FeatureStdExtM, FeatureStdExtC]>;
 
 //===----------------------------------------------------------------------===//
 // Define the RISC-V target.
 //===----------------------------------------------------------------------===//
 
 def RISCVInstrInfo : InstrInfo {
   let guessInstructionProperties = 0;
 }

llvm/lib/Target/RISCV/RISCVSchedRISCBoy.td

+//==- RISCVSchedRISCBoy.td - RISCBoy Scheduling Definitions -*- tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+// ===---------------------------------------------------------------------===//
+// The following is a scheduling model for RISCBoy, a very well-documented open-
+// source RISC-V chip. It implements the RV32IMC instruction set, using a
+// conventional 5-stage in-order pipeline.
+//
+// There are lots of documents about the core in the following document:
+// https://github.com/Wren6991/RISCBoy/blob/master/doc/riscboy_doc.pdf
+// Section references in comments below are to this document.
+//
+
+// ===---------------------------------------------------------------------===//
+// The following definitions describe the simpler per-operand machine model.
+// This works with MachineScheduler. See MCSchedule.h for details.
+
+def RISCBoyModel : SchedMachineModel {
+  // RISCBoy is in-order
+  let MicroOpBufferSize = 0;
+
+  // RISCBoy is single-issue
+  let IssueWidth = 1;
+
+  // RISCBoy has some funky instruction fetch fun
+  let LoopMicroOpBufferSize = 2;
+
+  // I'm entirely not sure about this.
+  // let LoadLatency = 2;
+
+
+  // From Table in §2.1.4
+  let MispredictPenalty = 2;
+
+  // RISCBoy has plugins (§2.6) so we won't claim to be complete.
+  let CompleteModel = 0;
+
+  let UnsupportedFeatures = [
+    IsRV64, // 64-bit
+    HasStdExtA, // Atomics
+    HasStdExtF, // Floats
+    HasStdExtD, // Doubles
+    // Bitwise Manipulation
+    HasStdExtB,
+    HasStdExtZbb,
+    HasStdExtZbc,
+    HasStdExtZbe,
+    HasStdExtZbf,
+    HasStdExtZbm,
+    HasStdExtZbp,
+    HasStdExtZbr,
+    HasStdExtZbs,
+    HasStdExtZbt,
+    HasStdExtZbproposedc,
+  ];
+} // RISCBoyModel
+
+//===----------------------------------------------------------------------===//
+// Define each kind of processor resource and number available.
+//
+// Modeling each pipeline as a ProcResource using the BufferSize = 0 since
+// RISCBoy is in-order.
+
+let BufferSize = 0 in {
+
+def RISCBoyUnitALU : ProcResource<1>; // ALU
+def RISCBoyUnitMemory : ProcResource<1>; // Load/Store
+def RISCBoyUnitBranch : ProcResource<1>; // Branch
+def RISCBoyUnitMPlugin : ProcResource<1>; // Multiply Plugin (§2.6.1, §2.6.2)
+
+} // BufferSize = 0
+
+
+let SchedModel = RISCBoyModel in {
+
+// Branches
+def : WriteRes<WriteJmp, [RISCBoyUnitBranch]>;
+def : WriteRes<WriteJal, [RISCBoyUnitBranch]>;
+def : WriteRes<WriteJalr, [RISCBoyUnitBranch]>;
+def : WriteRes<WriteJmpReg, [RISCBoyUnitBranch]>;
+
+// ALU
+def : WriteRes<WriteIALU, [RISCBoyUnitALU]>;
+def : WriteRes<WriteShift, [RISCBoyUnitALU]>;
+
+// Use worst-case §2.6.1 M-small plugin: 1 cycle per bit, 32 bits.
+let Latency = 32, ResourceCycles = [32] in {
+  def : WriteRes<WriteIMul, [RISCBoyUnitMPlugin]>;
+  def : WriteRes<WriteIDiv, [RISCBoyUnitMPlugin]>;
+} // Latency = 32, ResourceCycles = [32]
+
+// Memory
+def : WriteRes<WriteSTB, [RISCBoyUnitMemory]>;
+def : WriteRes<WriteSTH, [RISCBoyUnitMemory]>;
+def : WriteRes<WriteSTW, [RISCBoyUnitMemory]>;
+def : WriteRes<WriteLDB, [RISCBoyUnitMemory]>;
+def : WriteRes<WriteLDH, [RISCBoyUnitMemory]>;
+def : WriteRes<WriteLDW, [RISCBoyUnitMemory]>;
+
+// CSRs
+def : WriteRes<WriteCSR, [RISCBoyUnitMemory]>;
+
+// Nop
+def : WriteRes<WriteNop, []>;
+
+//===----------------------------------------------------------------------===//
+// RISCBoy supports forwarding (operand bypass) §2.2.1
+
+// def : ReadAdvance<
+def : ReadAdvance<ReadJmp, 0>;
+def : ReadAdvance<ReadJalr, 0>;
+def : ReadAdvance<ReadCSR, 0>;
+def : ReadAdvance<ReadStoreData, 0>;
+def : ReadAdvance<ReadMemBase, 0>;
+def : ReadAdvance<ReadIALU, 0>;
+def : ReadAdvance<ReadShift, 0>;
+def : ReadAdvance<ReadIDiv, 0>;
+def : ReadAdvance<ReadIMul, 0>;
+
+let Unsupported = 1 in {
+
+// FP Load/Store
+def : WriteRes<WriteFST32, []>;
+def : WriteRes<WriteFST64, []>;
+def : WriteRes<WriteFLD32, []>;
+def : WriteRes<WriteFLD64, []>;
+
+// Atomic Arithmetic/Load/Store
+def : WriteRes<WriteAtomicW, []>;
+def : WriteRes<WriteAtomicLDW, []>;
+def : WriteRes<WriteAtomicSTW, []>;
+
+// FP ALU
+def : WriteRes<WriteFALU32, []>;
+def : WriteRes<WriteFALU64, []>;
+def : WriteRes<WriteFSGNJ32, []>;
+def : WriteRes<WriteFSGNJ64, []>;
+def : WriteRes<WriteFMinMax32, []>;
+def : WriteRes<WriteFMinMax64, []>;
+def : WriteRes<WriteFClass32, []>;
+def : WriteRes<WriteFClass64, []>;
+def : WriteRes<WriteFCmp32, []>;
+def : WriteRes<WriteFCmp64, []>;
+def : WriteRes<WriteFMul32, []>;
+def : WriteRes<WriteFMulAdd32, []>;
+def : WriteRes<WriteFMulSub32, []>;
+def : WriteRes<WriteFMul64, []>;
+def : WriteRes<WriteFMulAdd64, []>;
+def : WriteRes<WriteFMulSub64, []>;
+def : WriteRes<WriteFDiv32, []>;
+def : WriteRes<WriteFDiv64, []>;
+def : WriteRes<WriteFSqrt32, []>;
+def : WriteRes<WriteFSqrt64, []>;
+
+// FP Convert/Move
+def : WriteRes<WriteFCvtF32ToF64, []>;
+def : WriteRes<WriteFCvtF64ToF32, []>;
+def : WriteRes<WriteFCvtI32ToF32, []>;
+def : WriteRes<WriteFCvtI32ToF64, []>;
+def : WriteRes<WriteFCvtF32ToI32, []>;
+def : WriteRes<WriteFCvtF64ToI32, []>;
+def : WriteRes<WriteFMovF32ToI32, []>;
+def : WriteRes<WriteFMovI32ToF32, []>;
+def : WriteRes<WriteFCvtI64ToF32, []>;
+def : WriteRes<WriteFCvtI64ToF64, []>;
+def : WriteRes<WriteFCvtF64ToI64, []>;
+def : WriteRes<WriteFCvtF32ToI64, []>;
+def : WriteRes<WriteFMovI64ToF64, []>;
+def : WriteRes<WriteFMovF64ToI64, []>;
+
+// 64-bit ALU
+def : WriteRes<WriteIALU32, []>;
+def : WriteRes<WriteShift32, []>;
+def : WriteRes<WriteIMul32, []>;
+def : WriteRes<WriteIDiv32, []>;
+
+// 64-bit Load/Store
+def : WriteRes<WriteLDWU, []>;
+def : WriteRes<WriteSTD, []>;
+def : WriteRes<WriteLDD, []>;
+
+// 64-bit Atomic Arithmetic/Load/Store
+def : WriteRes<WriteAtomicD, []>;
+def : WriteRes<WriteAtomicLDD, []>;
+def : WriteRes<WriteAtomicSTD, []>;
+
+// Reads
+def : ReadAdvance<ReadIALU32, 0>;
+def : ReadAdvance<ReadShift32, 0>;
+def : ReadAdvance<ReadIDiv32, 0>;
+def : ReadAdvance<ReadIMul32, 0>;
+def : ReadAdvance<ReadAtomicWA, 0>;
+def : ReadAdvance<ReadAtomicWD, 0>;
+def : ReadAdvance<ReadAtomicDA, 0>;
+def : ReadAdvance<ReadAtomicDD, 0>;
+def : ReadAdvance<ReadAtomicLDW, 0>;
+def : ReadAdvance<ReadAtomicLDD, 0>;
+def : ReadAdvance<ReadAtomicSTW, 0>;
+def : ReadAdvance<ReadAtomicSTD, 0>;
+def : ReadAdvance<ReadFMemBase, 0>;
+def : ReadAdvance<ReadFALU32, 0>;
+def : ReadAdvance<ReadFALU64, 0>;
+def : ReadAdvance<ReadFMul32, 0>;
+def : ReadAdvance<ReadFMulAdd32, 0>;
+def : ReadAdvance<ReadFMulSub32, 0>;
+def : ReadAdvance<ReadFMul64, 0>;
+def : ReadAdvance<ReadFMulAdd64, 0>;
+def : ReadAdvance<ReadFMulSub64, 0>;
+def : ReadAdvance<ReadFDiv32, 0>;
+def : ReadAdvance<ReadFDiv64, 0>;
+def : ReadAdvance<ReadFSqrt32, 0>;
+def : ReadAdvance<ReadFSqrt64, 0>;
+def : ReadAdvance<ReadFCmp32, 0>;
+def : ReadAdvance<ReadFCmp64, 0>;
+def : ReadAdvance<ReadFSGNJ32, 0>;
+def : ReadAdvance<ReadFSGNJ64, 0>;
+def : ReadAdvance<ReadFMinMax32, 0>;
+def : ReadAdvance<ReadFMinMax64, 0>;
+def : ReadAdvance<ReadFCvtF32ToI32, 0>;
+def : ReadAdvance<ReadFCvtF32ToI64, 0>;
+def : ReadAdvance<ReadFCvtF64ToI32, 0>;
+def : ReadAdvance<ReadFCvtF64ToI64, 0>;
+def : ReadAdvance<ReadFCvtI32ToF32, 0>;
+def : ReadAdvance<ReadFCvtI32ToF64, 0>;
+def : ReadAdvance<ReadFCvtI64ToF32, 0>;
+def : ReadAdvance<ReadFCvtI64ToF64, 0>;
+def : ReadAdvance<ReadFCvtF32ToF64, 0>;
+def : ReadAdvance<ReadFCvtF64ToF32, 0>;
+def : ReadAdvance<ReadFMovF32ToI32, 0>;
+def : ReadAdvance<ReadFMovI32ToF32, 0>;
+def : ReadAdvance<ReadFMovF64ToI64, 0>;
+def : ReadAdvance<ReadFMovI64ToF64, 0>;
+def : ReadAdvance<ReadFClass32, 0>;
+def : ReadAdvance<ReadFClass64, 0>;
+
+} // Unsupported = 1
+
+} // SchedModel = RISCBoyModel
 No newline at end of file